JP2989840B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device including MIS field-effect transistors, and more particularly to a semiconductor memory device having a redundant memory cell for replacing a defective memory cell. Related to the device.

[Prior Art] In a conventional semiconductor memory device having a redundant memory cell,
When a specific memory cell does not operate normally, a redundant memory cell row or a redundant memory cell column is used instead of using the memory cell row or the memory cell column to which the memory cell belongs.

FIG. 2 is a block diagram of a conventional semiconductor memory device having a redundant memory cell row. In the semiconductor memory device shown in FIG. 1, when there is no defective cell in the normal memory cell array 1, the memory device performs a normal operation in which a specific memory cell in the normal memory cell array is selected by the column decoder 3 and the row decoder 4. Do. If a defective cell exists in the normal memory cell array 1, the address of the memory cell row including the defective cell is stored in the ROM 9 provided on the chip by the RO.
The data is written via the M writing circuit 8. In the use state of the semiconductor memory device, if the input address and the contents of the ROM 9 are compared and matched by the address comparison circuit 7, a drive signal is sent from the drive signal switching circuit 6 to the redundant memory cell row decoder 5 side, and the redundant memory cell Row 2 is selected. If the input address does not match the ROM address, the row on the regular memory cell array 1 side is selected.

In the above description, the row selected by the ROM is switched, but the method of writing the address of the defective cell in the ROM and disconnecting the word line or digit line to which the defective cell is connected from the row decoder or the column decoder is also available. Some have been adopted.

[Problems to be Solved by the Invention] In the above-described conventional method for relieving a partially defective product, the digit line is connected to the precharge level line and charging to the precharge level is repeated, so that the following inconvenience occurs.

If the digit line and word line are shorted,
During standby, a current constantly flows from the digit line at the precharge level to the word line at the GND level, resulting in a standby current failure.

Even if a current failure does not occur, the potential of that word line rises even if it is not selected due to a small current flowing from the digit line to the word line, and adversely affects the sensing operation when another normal word line is selected. Exert.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a normal memory cell,
It has means for preventing a digit line connected to a defective normal memory cell from being selected when a defect occurs in a normal memory cell, and redundant memory cells for replacing the defective normal memory cell. Each digit line in the normal memory cell array has a disconnection which can completely completely separate the digit line from the precharge level line and the sense amplifier when the memory cell connected to the digit line is defective. Means are provided.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. As shown in the figure, word lines WL1, WL2 and digit lines
The memory cells MS1 to MS4 are connected at the positions where they intersect with DL1 and DL2. A CMOS circuit (MOS transistor Q) to which word line drive signals WD1 and WD2 are input is connected to the word lines WL1 and WL2.
7, Q8 or Q9, Q10) applies high or low level voltage. Each digit line DL1 to DL4 is a fuse Fu
1 to Fu4, connected to sense amplifiers SA1, SA2, and transistors Q1, Q3, Q4, Q6 and fuses Fu5, F
It is connected to the precharge level line PL via u6.
Transistors Q1 to Q6 are precharge control signals PC
The digit lines are precharged to a precharge level after the sensing operation is completed via these transistors.

An electrical test is performed on the semiconductor storage device in a wafer state. If this test reveals that the memory cell MS1 is defective, the digit line to which the cell is connected is not selected, and the fuses Fu1, Fu2, and Fu5 are cut. In this way, since the digit lines DL1 and DL2 can be separated from other portions, even if these digit lines and the word line are short-circuited, they are not affected by the short-circuit. Chips can be remedied as good products.

[Effects of the Invention] As described above, the semiconductor memory device of the present invention has a redundant memory cell, and each digit line in the normal memory cell array can completely separate the digit line from the others. According to the present invention, when a defective cell occurs in the normal memory cell array, the digit line to which the defective cell is connected is completely electrically isolated from the others. Can be separated. Therefore, according to the present invention, it is possible to prevent a standby current failure, a floating of a non-selected word line, and the like, to improve the product yield, and to stabilize the operation of the semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG.
It is a block diagram showing a conventional example. DL1 to DL4: Digit wire, Fu1 to Fu6: Fuse, MS
1 to MS4: Memory cell, PC: Precharge control signal, PL: Precharge level line, Q1 to Q10: MOS
Transistor, SA1, SA2 Sense amplifier, WD1, WD2
... word line drive signal, WL1, WL2 ... word line.

Claims (1)

(57) [Claims] 1. A normal memory cell connected to a digit line, means for preventing a digit line connected to a defective normal memory cell from being selected when the normal memory cell becomes defective, and a defective normal memory cell; In a semiconductor memory device having a redundant memory cell replaced with a memory cell, when a normal memory cell becomes defective, a digit line connected to the defective memory cell is connected to each digit line by a precharge level line and a sense line. A semiconductor memory device further comprising disconnecting means capable of being completely electrically separated from an amplifier.