JP2990751B2 - Series-parallel analog-to-digital converter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial-parallel analog-to-digital converter.

2. Prior Art FIG. 8 shows a typical conventional serial-parallel A / D converter.
The analog input signal 2 is roughly subjected to high-order A / D conversion in the high-order A / D conversion circuit 13 to generate a high-order A / D conversion output 7. Further, this higher-order A / D conversion output is converted to a D / A
It is converted back to an analog voltage, and a subtractor 15 performs subtraction and amplification between the analog input signal 2 and the output of this D / A conversion. Lower A / D conversion is performed, and a lower A / D conversion output 12 is obtained.

Such a serial-parallel A / D converter has an advantage that the circuit scale is extremely small as compared with a parallel A / D converter conventionally used. For example, in a configuration with a resolution of 10 bits, the number of comparators is extremely small, ie, 1/16, so that significant reduction in power consumption and chip size can be achieved.

However, in such a conventional serial-parallel A / D converter, the gain and offset voltage of the subtracter 15 are accurately matched with the full-scale voltage and offset voltage of the lower A / D conversion circuit 16. It is necessary to adjust the full-scale voltage and offset voltage of the internal D / A conversion circuit 14, so there are many adjustment points, and the stability of conversion accuracy is lacking. Have difficulty.

The difficulty in satisfying the DC accuracy of such a conventional serial-parallel A / D converter will be described more specifically with reference to FIG.

FIG. 9 shows a voltage relationship of each part of the serial / parallel A / D converter shown in FIG.

The first required voltage accuracy is the relative accuracy between the reference voltage of the upper A / D conversion circuit and the output voltage of the D / A conversion circuit. From the principle of conversion, when the analog input signal Vin is larger than the reference voltage Vr, i of the upper A / D converter and smaller than Vr, i + 1, assuming that the output of the D / A converter generates Vd, i, The error ΔVo, i (= Vd, i−Vr, i) between the two voltages usually needs to satisfy the final accuracy of this serial-parallel A / D converter.
In the case of an A / D converter with 0-bit accuracy, this voltage error ΔVo, i
It requires 0.05% accuracy for the full-scale voltage of the output of the A conversion circuit. Such accuracy is difficult to achieve without any voltage adjustment means, and it is desirable that the reference voltage of the upper A / D conversion circuit can be varied by an external signal. When it is changed, it is more difficult to follow the signal to secure the accuracy.

The second required voltage accuracy is the relative accuracy between the voltage obtained by multiplying the unit voltage of the output voltage of the D / A conversion circuit by the gain of the subtractor and the reference voltage of the lower A / D conversion circuit. Now, the gain of the subtractor is K, and the unit voltage of the output voltage of the D / A conversion circuit is Vu (= Vd, i +
1−Vd, i), assuming that the full-scale voltage of the reference voltage of the lower A / D conversion circuit is Vfs, an error ΔVo2 between these two voltages
(= Vfs−Vu) must be at least as high as the resolution of the lower A / D converter. For example, when the lower A / D converter has a resolution of 5 bits, ΔVo2 is the full scale of the lower A / D converter. It must be set within 1.5% of the voltage Vfs. This is not always easy because it is necessary to match three variables of the unit voltage Vu of the output voltage of the D / A converter, the gain K of the subtractor, and the full scale voltage Vfs of the lower A / D converter.

In addition, the offset voltage of the subtractor must also satisfy the final accuracy of the serial / parallel A / D converter.

Next, since it is necessary to satisfy AC accuracy, this will be briefly described with reference to FIG. FIG. 10 shows the transient response of the input voltage of the lower A / D conversion circuit. The input voltage falls within a certain voltage range over time,
A certain settling time is required. In particular, since the subtractor is an operational amplifier to which a large amount of negative feedback has been applied, the phase characteristics are poor and the settling time tends to be long. For this reason, the conversion speed of the serial / parallel A / D converter is reduced, and in some cases, oscillation is caused. Furthermore, noise such as system noise leaking from the lower A / D conversion circuit is mixed in, and the conversion accuracy is degraded, making high-speed high-precision conversion difficult.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a high-speed and high-accuracy serial-parallel A / D converter suitable for a monolithic IC with a simple configuration.

Means for Solving the Problems The present invention provides a reference voltage generating means for generating a plurality of reference voltages, an analog input signal commonly input to one input terminal, and each reference voltage input to the other input terminal. It consists of a plurality of differential conversion circuits numbered in the order of the magnitude of the reference voltage, which converts the potential difference between the input terminals into an output current, and includes an even-numbered differential conversion circuit and an odd-numbered differential conversion circuit. A differential conversion circuit train having a reverse comparison polarity, a load resistance train serving as a load of the output current of the differential conversion circuit, and a high-order A / D that performs high-order conversion by comparing an analog input signal with a reference voltage. A conversion circuit, two differential conversion circuits of one comparison polarity whose reference voltage is closest to the analog input signal above and below the analog input signal, and the reference voltage is the analog input signal. And the comparison of the other nearest neighbors above and below First switch means for selecting two differential conversion circuits having polarities and supplying an output current of the selected differential conversion circuit to the load resistance string; and four types of output voltages generated in the load resistance string And a first resistor string for dividing the output voltage of the differential conversion circuit having one of the comparison polarities among the output voltages of the load resistor string. And a second resistor string dividing the output voltage of the differential conversion circuit having the other comparison polarity among the output voltages of the load resistor string, and a voltage divider by the voltage divider. A serial-parallel A / D converter comprising a lower A / D conversion circuit for performing lower A / D conversion by comparing the applied voltage with a voltage selected by the second switch means.

Operation In the present invention, high-order A / D conversion is performed in the same manner as in the conventional example. However, a D / A conversion circuit and a subtractor are not provided, an analog input signal is commonly input to one input terminal, each reference voltage is input to the other input terminal, and a potential difference between one input terminal and the other input terminal is provided. Is converted to an output current. A plurality of differential conversion circuits numbered in the order of the magnitude of the reference voltage (however, the comparison polarity is an even-numbered differential conversion circuit and an odd-numbered differential conversion circuit. Is provided, a subtraction and a differential amplification of the analog input signal and each reference voltage are performed, and a specific output current is selected from the plurality of output currents and supplied to the load resistor. By providing a switch means for generating a voltage necessary for lower-order A / D conversion. Further, the lower voltage A / D conversion is performed by comparing the voltage divided by the voltage dividing means for dividing the voltage between the specific output voltage selected from the voltage generated in the load resistor and the output voltage of the load resistor string. By doing so, a special reference voltage for the lower A / D conversion is not required, and the effect of the gain accuracy of the differential conversion circuit on the conversion accuracy is eliminated. The differential conversion circuit is not a negative feedback type circuit such as an operational amplifier, but a non-negative feedback type circuit such as a differential amplifier circuit is sufficient. A converter can be realized.

Embodiment FIG. 1 shows a circuit diagram of a serial-parallel A / D converter according to a first embodiment of the present invention.

An analog input signal 2 is commonly input to one input terminal of a differential conversion circuit array 1 including a plurality of differential conversion circuits for converting a potential difference between one input terminal and the other input terminal into an output current. Each of the reference voltages generated by dividing the voltage of the reference voltage 3 constituting the reference voltage generating means by the reference resistor 4 is input to the input terminal. Upper comparator row 5
The voltage at each voltage dividing point of the reference resistor 4 is input to one input terminal of each comparator, and the analog input signal 2 is input to the other input terminal in common. The output of the upper logic circuit 6 is input to the circuit 6 and determined, and a signal for selecting a specific output current among a plurality of output currents is given to the first switch means 7 to generate a voltage in the load resistance array 8. . The generated voltage is applied to the voltage dividing means 10
Where the pressure is divided. Each of the comparators constituting the lower comparator row 12 includes a divided voltage and a higher-level logic circuit 6 including, as a part thereof, second selecting means for selecting a specific voltage among the divided voltages. The output voltage of the second switch means 11 switched by the output is compared, and the comparison output is input to the lower logic circuit 13 and the output of the lower logic circuit 13 is determined. By adding the determined outputs of the upper logic circuit 6 and the lower logic circuit 13 in the adder 14, the A / D
The conversion output 15 is obtained.

Next, the operation of the first embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 2 shows (a) the outputs Ia0, Ia4,... Ia16 of the respective differential converters A0, A4,..., A16 for the analog input signal Vs, and the respective differential converters A2, A6,.・, A18 output Ib2, Ib6,
..., Ib18, (b) comparison output of each of the comparators C0 to C7,
(C) Switches Sa0, Sa4,..., Sa16, Sb2, Sb6,.
This shows a selection state of b18, Sca, and Scb.

As shown in FIG. 2A, each of the differential conversion circuits A0, A
If the reference voltage of 2, ..., A18 is V0, V2, ..., V18,
Each output Ia0, Ia4, ..., Ia16, Ib2, Ib6, ..., Ib18
In the vicinity of each reference voltage, (1-1) and (1-2)
Given by the formula.

Iai = g (Vs−Vi) + Ib (i = 0, 4,..., 16) (1
-1) Ibi = −g (Vs−Vi) + Ib (i = 2, 6,..., 18)
(1-2) In the above equation, g is the transconductance of the differential conversion circuit, and Ib is the bias current.

The comparison output of the comparators C2 to C16 constituting the upper comparator row 5 shown in FIG. 2B is given by the following equation (2).

Ci = sgn (Vs−Vi) (i = 2, 4,..., 16) (2) In the above equation, the sgn function is defined and used as follows.

sgn (x) = 1: x ≧ 0 sgn (x) = 0: x <0 As apparent from the equation (2), the comparison output of each comparator is [1] when the input signal is larger than the reference voltage. Take. Therefore, if these comparison outputs are input to the logic circuit 6, a high-order A / D conversion output can be obtained.

FIG. 2C shows the open / closed state of each switch of the switch means 7 and the connected state of each switch of the switch means 11. In the figure, [1] is ON state, [0] is OF
Indicates the F state, and [+] indicates the connection state to the + terminal.
[-] Indicates a connection state to the-terminal.

As described above, the differential conversion circuit generates a linear output current according to the voltage level of the analog input signal, and is selectively switched.

Next, a method of performing lower A / D conversion using the output current generated as described above will be described. The output current of the differential conversion circuit is guided to the load resistance by the first switch means 7 and is converted into a voltage.

FIG. 3 shows the voltage at each node in the voltage dividing means with respect to the analog input signal 2. In this example, the resolution of the lower A / D conversion is assumed to be 3 bits, and the case where the voltage of the analog input signal 2 is between V2 and V3 is shown. As the voltage dividing means, one obtained by cascading the same resistors is used.
The output currents of the selected four adjacent differential conversion circuits are divided into voltages obtained by converting the output currents by the load resistors, and VA1 to VA1
VA3 and VB1 to VB3 are generated. The increase / decrease polarity of VA0 to VA4 and the increase / decrease polarity of VB0 to VB4 are uniquely determined by the level of the analog input signal. In consideration of the increase / decrease polarity, VA0 to VA4 and VB0 to VB over the entire input voltage range.
The state of B4 is shown in FIG. With the above configuration, it is possible to realize a serial-parallel A / D converter that doubles the minimum voltage range of upper A / D conversion and performs 3-bit lower A / D conversion.

Note that, as shown in FIG.
In the case where the buffer means 9 is inserted between
By inserting the buffer means 9 in addition to the method shown in the figure, the output voltage of the load resistance string 8 becomes less affected by the current flowing through the voltage dividing means 10, and the series-parallel configuration shown in FIG. Series-parallel A / D with higher accuracy than the A / D converter
A converter is obtained.

Next, a circuit diagram of a series-parallel A / D converter according to a second embodiment of the present invention is shown in FIG. This has the same configuration as that of the A / D converter of the first embodiment of the present invention except for the presence or absence of a load resistor, and the operation of the current / voltage conversion by the load resistor in the A / D converter of the first embodiment. Can be regarded as being omitted.

Next, a third embodiment will be described with reference to FIG. Although the upper comparator row and the lower comparator row are provided in the circuits of FIGS. 1 and 5, the third switch means 104 controlled by the third selecting means as shown in FIG. Resistance 4
1 and 5 can be used in a time-division manner for high-order conversion and low-order conversion. The number of comparators can be reduced as compared with the circuit shown in (1), and the circuit scale of the A / D converter can be reduced. The third switch means
104 is a second switch means 11 in the embodiment of FIG.
In addition, the conversion logic circuit 106 includes:
Upper logic circuit 6 and lower logic circuit 13 in the first embodiment
And the function of the adder 14.

Finally, a fourth embodiment will be described with reference to FIG. When performing lower-order conversion in each of the circuit configurations of FIGS. 1 and 5, one input terminal of each comparator in the comparator row always receives the voltage at the end of the voltage-dividing resistor as voltage-dividing means. Although the voltage is supplied through the switch means, it may not be the voltage at the end in some cases, and the input voltage of the comparator for interpolation is generated by using the outputs of a plurality of differential circuits. According to one of the ideas, each of the voltage dividing points of the voltage dividing means has a cross point of the input voltage of the lower comparator as shown in FIG. 6 when performing the lower conversion by the configuration as shown in FIG. May be given as an input of the comparator. Since the voltage at each voltage dividing point of the voltage dividing means 10 is used as an input to the lower comparator, the second switch means 11 in the embodiment shown in FIGS. 1 and 5 is naturally unnecessary.

Effects of the Invention According to the present invention, the following effects can be obtained.

(1) Since it is not necessary to match the full-scale voltage of the D / A converter circuit and the full-scale voltage of the upper A / D converter circuit as in the past, high-precision A / D conversion can be realized. No circuit means is required, the configuration is simplified, and the reference voltage can be freely varied by an external signal, which is convenient.

(2) Although a differential conversion circuit array is used without using a high-precision operational amplifier as in the related art, relative gain accuracy between adjacent differential conversion circuits is required, but absolute accuracy is not required. Therefore, a normal emitter-coupled transistor pair is sufficient for the differential conversion circuit without using an operational amplifier. The relative gain accuracy of the differential amplifier circuit can be sufficiently achieved by using integrated circuit technology. Since a high-precision operational amplifier is not used, there is no need for an adjustment portion, so that it is suitable for an integrated circuit, and a higher-speed serial-parallel A / D converter can be configured.

(3) Further, there is no need to match the reference voltage full-scale voltage of the lower A / D conversion circuit as in the related art. This is because the lower A / D conversion of the present embodiment does not use a fixed reference voltage as in the related art, but includes voltage dividing means for dividing a selected plurality of differential output voltages. This is because the lower A / D conversion is performed by comparing the voltages.In other words, the reference voltage for the input analog signal of the lower A / D conversion is obtained by dividing the reference voltage of the upper A / D conversion evenly. Because it is. From this, the consistency between the lower A / D conversion and the upper A / D conversion is extremely good, and conversion with higher accuracy is possible.

(4) In addition, in the present embodiment, since the input signal of the lower A / D conversion is of a differential type, it has an action of removing common mode noise such as power supply noise, and is more accurate and stable than the conventional one. A series-parallel A / D converter can be realized.

(5) By setting the conversion voltage range of the lower A / D converter to include the comparison range of one unit of the upper comparator and to make it wider,
More accurate conversion can be performed even on an input signal that fluctuates with time, and further A / D conversion can be further stabilized and high speed and high accuracy can be achieved.

(6) Further, since the input voltage of the differential amplifier circuit that is switched when the input signal changes between adjacent upper comparators 1 unit is the voltage farthest from the adjacent voltage, the upper comparator 1 unit Lower A /
Since the method of generating the input voltage of the D-conversion comparator is guaranteed to be unique, uniformity (that is, uniqueness) of the conversion output code can be ensured between one adjacent higher-order comparator unit. .

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 (a) shows an output of a differential conversion circuit inside an A / D converter of the embodiment. FIG. 2B is an explanatory diagram showing a comparison output of each comparator, FIG. 2C is an explanatory diagram showing a switch state, and FIG. 3 is a lower A / D in the embodiment. FIG. 4 is an explanatory diagram showing a state of conversion, FIG. 4 is an explanatory diagram showing a state of lower-order conversion over the entire input voltage range, FIG. 5 is a circuit configuration diagram of an embodiment including a voltage buffer means in the first embodiment, and FIG. FIG. 7 is an explanatory diagram when an intersection of input voltages of a comparator for lower conversion is set to a different point from the embodiment shown in FIG. 1; FIG. 7 is a circuit configuration diagram of a second embodiment of the present invention; Fig. 9 is a circuit diagram of a conventional serial-parallel A / D converter, Fig. 9 is a diagram showing the voltage relationship of each part of the conventional serial-parallel A / D converter, and Fig. 10 is a conventional serial-parallel A / D converter. Lower A of container FIG. 11 is a voltage waveform diagram showing a transient response of the input voltage of the / D conversion circuit, FIG. 11 is a circuit diagram of a third embodiment of the present invention, and FIG.
FIG. 11 is a circuit diagram of a fourth embodiment of the present invention. 1 ... Differential conversion circuit row, 4 ... Reference resistance, 5 ... High order comparator row, 6 ... High order logic circuit, 7 ... First switch means, 10 ... Voltage dividing means, 11 ... Second switch means,
12 ... lower comparator row, 13 ... lower logic circuit, 14 ... adder.

Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 1/00-1/88

Claims (2)

(57) [Claims] A reference voltage generating means for generating a plurality of reference voltages, an analog input signal is commonly input to one input terminal, and respective reference voltages are input to the other input terminal. It consists of a plurality of differential conversion circuits numbered in the order of the magnitude of the reference voltage, which converts the potential difference of the reference voltage into an output current.The comparison polarities of the even-numbered and odd-numbered differential conversion circuits are opposite. A certain differential conversion circuit sequence, a load resistance sequence serving as a load of an output current of the differential conversion circuit, a high-order A / D conversion circuit for comparing an analog input signal with a reference voltage and performing high-order conversion, Among the differential conversion circuits, two differential conversion circuits having one comparison polarity whose reference voltage is closest to the analog input signal above and below the analog input signal; Two differential conversions of adjacent comparison polarities A first switch means for selecting a circuit and supplying the output current of the selected differential conversion circuit to the load resistance string; and selecting one of four types of output power generated in the load resistance and selecting the next one. A second switch means for sending to a stage, a first resistor string for dividing a voltage between the output voltages of the differential conversion circuit having one comparison polarity among output voltages of the load resistor string, and an output of the load resistor string. A voltage divider comprising a second resistor string for dividing a voltage between the output voltages of the differential conversion circuit having the other comparison polarity; and a voltage divided by the voltage divider and the second resistor string. A / D by comparing the voltage selected by the switch means
A series-parallel A / D converter equipped with a low-order A / D conversion circuit that performs conversion. A reference voltage generating means for generating a plurality of reference voltages; an analog input signal commonly input to one input terminal; and respective reference voltages input to the other input terminal. It consists of a plurality of differential conversion circuits numbered in the order of the magnitude of the reference voltage, which converts the potential difference of the reference voltage into an output voltage.The comparison polarity of the even-numbered and odd-numbered differential conversion circuits is reversed. A certain differential conversion circuit row, a high-order A / D conversion circuit that performs high-order conversion by comparing an analog input signal with a reference voltage, and among a plurality of differential conversion circuits, the reference voltage of which is above and below the analog input signal. Select the two differential conversion circuits of one comparison polarity closest to the bottom and the two differential conversion circuits of the other comparison polarity whose reference voltage is closest to the analog input signal above and below the analog input signal Output voltage of the selected differential conversion circuit A first switch for supplying to the next stage, a second switch for selecting any one of the four types of output voltages selected by the first switch and transmitting the output voltage to the next stage, and the first switch Means for dividing a voltage between the output voltages of the differential conversion circuit having one comparison polarity selected by the first switch means, and a differential resistor circuit having the other comparison polarity selected by the first switch means. A voltage dividing means comprising a second resistor string for dividing the voltage between output voltages; and comparing the voltage divided by the voltage dividing means with the voltage selected by the second switch means, the lower A / D
A serial-parallel A / D converter that includes a low-order A / D conversion circuit that performs conversion.