JP2990774B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an insulated gate field effect transistor (MOSF) having enhanced radiation resistance.
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[Conventional technology]

The use of semiconductor devices in space and around nuclear reactors is increasing. In such an environment, exposure to radiation causes various radiation damages.

When ionizing radiation such as X-rays or gamma rays is applied to the gate oxide film of a MOSFET, an interface state is generated at the boundary between the semiconductor substrate and the gate oxide film, and positive charges are trapped in hole traps inside the gate oxide film. Captured fixed positive charge accumulation occurs.

Of the electron-hole pairs generated in the gate oxide film by the irradiation of radiation, radiation damage occurs due to the involvement of holes.

The generation of interface states and the accumulation of fixed positive charges fluctuate the threshold voltage of the MOSFET and reduce the mobility of carriers in the channel. If these fluctuations exceed the allowable value of the semiconductor device, the function of the element is lost.

To suppress such radiation damage, it is necessary to dope the polysilicon film of the gate electrode with a high concentration of phosphorus and increase the phosphorus concentration at the interface between the gate oxide film and the silicon substrate to 10 ²⁰ cm ^-3 or more. It is valid. In this way, a very small amount of phosphorus is introduced into the gate oxide film and acts as a recombination center, and recombination and annihilation of holes generated in the oxide film due to radiation irradiation and interface states generated at the oxide film / silicon interface. Thus, the radiation resistance of the semiconductor element is improved.

FIG. 4 shows the interface state density generated at the gate oxide film / silicon substrate interface when gamma rays are irradiated to MOS capacitors having various phosphorus concentrations at the interface between the polysilicon film of the gate electrode and the gate oxide film. . The phosphorus doping changes the phosphorus concentration by adjusting the heat treatment time by thermal diffusion at 840 ° C. The absorbed dose of gamma rays is 1 Mrad (Si), and the gate bias is 1 MV / cm.

As the phosphorus concentration increases, the interface state density decreases,
^When it exceeds ²⁰ cm ^-3 , it decreases greatly, saturates at 5 × 10 ²⁰ cm ^-3 or more, and becomes about 1/10 the value at 5 × 10 ¹⁹ cm ^-3 or less.

It can be seen that in order to increase the radiation resistance of the gate oxide film, the phosphorus concentration at the interface between the gate electrode and the gate oxide film must be 1 × 10 ²⁰ cm ⁻³ or more. Normally, the thickness of the polysilicon film serving as the gate electrode is set to 5000 mm. In such a thick film thickness, the phosphorus concentration in the interface between the gate oxide film and the gate electrode to the 10 ²⁰ cm ^-3 or more, it is necessary high temperature and long-time heat treatment. However, a heat treatment at a high temperature for a long time increases the amount of hole traps in the gate oxide film and increases the amount of change in the threshold voltage during radiation irradiation. In particular, if a heat treatment at a temperature higher than the gate oxidation temperature is performed after forming the gate oxide film,
It is known that the radiation resistance of the device is significantly reduced. Therefore, the heat treatment for phosphorus doping needs to be performed at a temperature lower than the gate oxidation temperature.

Therefore, in the conventional method of manufacturing a semiconductor device with enhanced radiation resistance, the gate electrode thickness is reduced to 3,000 mm or less, so that high-concentration phosphorus is doped into the gate electrode by a low-temperature, short-time heat treatment to form the gate electrode and the gate oxide. The phosphorus concentration at the interface with the film is set to 1 × 10 ²⁰ cm ⁻³ or more.

[Problems to be solved by the invention]

If the thickness of the gate oxide film is reduced to 3000 °, the implanted ions cannot be shielded by the gate electrode in the ion implantation step for forming the source / drain. Implanted ions as primary particles or secondary particles (silicon, oxygen, electrons, etc.) by knock-on implantation of the implanted ions and the gate electrode material reach the gate oxide film and leave surface damage. There is a problem in that the number of hole traps in the gate oxide film is increased, the amount of shift of the threshold value upon irradiation with radiation is increased, and the radiation resistance of the device is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device in which an impurity ion implanted for forming a source / drain does not damage a gate oxide film and improves the radiation resistance of an element.

[Means for solving the problem]

In the semiconductor device of the present invention, an insulating film having the same planar shape as the gate electrode is formed on a gate electrode made of a phosphorus-doped polysilicon film, the thickness of the gate electrode is 3000 mm or less, and the film of the gate electrode is formed. An insulated gate field effect transistor characterized in that the sum of the thickness and the thickness of the insulating film is 4000 ° or more.

Alternatively, in the semiconductor device of the present invention, an insulating film having the same planar shape as the gate electrode is formed on a gate electrode made of a phosphorus-doped polysilicon film, and the thickness of the gate electrode is 3000
Å or less, and the insulated gate field effect transistor is characterized in that the adjacent concentration near the interface between the gate oxide film and the gate electrode is 10 ²⁰ cm ⁻³ or more.

In the method of manufacturing a semiconductor device according to the present invention, when manufacturing the above-described semiconductor device, the polysilicon film of the gate electrode is doped with phosphorus at a temperature lower than a gate oxide film forming temperature.

[Action]

An insulating film having the same planar shape as the gate electrode is formed on the gate electrode to protect the gate oxide film by shielding the implanted ions so that the polysilicon film of the gate electrode has a thickness of 3000 mm or less. 3000Å polysilicon film thickness
In order to improve the radiation resistance of the device, phosphorus is doped into the gate electrode by a heat treatment at a temperature equal to or lower than the gate oxide film forming temperature, and the phosphorus concentration at the gate electrode / gate oxide film interface is reduced to 1 × 10 ²⁰ cm ⁻ Must be ³ or more.

Further, in order to shield the implanted ions, the sum of the gate electrode film thickness and the silicon oxide film thickness on the gate electrode needs to be 4000 ° or more.

Fig. 5 shows the oxide film on the gate electrode with a fixed charge density that accumulates in the gate oxide film when a MOS capacitor with a silicon oxide film formed on the polysilicon gate electrode as an insulating film for shielding implanted ions is irradiated with gamma rays. Shows thickness dependence. Here, since the phosphorus concentration at the interface between the gate oxide film and the gate electrode is about 10 ¹⁹ cm ⁻³ , there is no effect of improving the radiation resistance by phosphorus doping. The thickness of the gate electrode is 1000 °. In order to evaluate the change in radiation resistance due to ion implantation damage, a sample subjected to arsenic ion implantation for forming a source / drain after forming an insulating film on a gate electrode is compared with a sample not subjected to ion implantation.

If ion implantation is not performed, the charge density does not depend on the oxide film thickness. However, if ion implantation is performed, the charge density decreases as the oxide film thickness increases. At 3000 mm or more, it shows the same charge density as the sample without ion implantation.

In order to shield the implanted ions and remove the damage to the gate oxide film, a silicon oxide film having a thickness of 3000 mm is required on the gate electrode.

Furthermore, since the ranges of the implanted ions between the silicon oxide film and the polysilicon film are almost the same, if the sum of the film thicknesses of the polysilicon film and the silicon oxide film is 4000 mm, the implanted ions are shielded at an arbitrary thickness ratio. can do.

The range of the implanted ions in the silicon nitride film, which is a typical insulating material together with the silicon oxide film, is shorter than the range in the silicon oxide film. In order to use a silicon nitride film as a shielding film, the sum with the thickness of the polysilicon electrode is 4000 膜厚.
It is enough.

〔Example〕

FIGS. 1 (a) to 1 (a) show a first embodiment of the present invention.
This will be described with reference to FIG.

As shown in the completed view of FIG. 1 (d), a gate oxide film 2, an N ⁺ type source / drain 5 are formed on a P-type silicon substrate 1, and a gate electrode made of polysilicon is formed on the gate oxide film 2. 3 and an aluminum electrode 7 is formed on the N ⁺ type source / drain 5 to form an N-channel MOSFET.

Further, an oxide film 4 having the same planar shape as the gate electrode is formed on gate electrode 3. Gate electrode 3 and aluminum electrode 7 are insulated by silicon oxide film 6.

 Next, the manufacturing process will be described.

First, as shown in FIG. 1A, a gate oxide film 2 is formed on a P-type silicon substrate 1 by a thermal oxidation method. Next, a 2000-nm-thick polysilicon film serving as the gate electrode 3 is grown by the CVD method.

Next, the polysilicon film is doped with phosphorus by thermal diffusion. Gate electrode 3 and gate oxide film 2 at a temperature of 850 ° C. or less
The concentration of phosphorus at the interface with is set to 1 × 10 ²⁰ cm ⁻³ or more.

Next, as shown in FIG. 1 (b), a 2000-nm-thick silicon oxide film 4 is grown on the entire surface by CVD. Further, unnecessary silicon oxide film 4 and polysilicon film are etched by lithography to form gate electrode 3 and silicon oxide film 4 on gate electrode 3.

Next, using the gate electrode 3 and the oxide film 4 thereon as a mask, for example, arsenic is ion-implanted in a self-aligning manner, and then annealed in a nitrogen atmosphere to form an N ⁺ type source / drain 5.
To form

Next, as shown in FIG. 1C, an interlayer insulating film 6 is formed by a CVD method, and an N ⁺ type source
The interlayer insulating film 6 on the drain 5 is etched to form a contact opening.

Finally, as shown in FIG. 1 (d), after an aluminum film is deposited on the entire surface, an aluminum electrode 7 is formed by lithography and etching to complete the element portion.

FIG. 3 shows a graph comparing the sub-threshold current characteristics before and after gamma irradiation of the N-channel MOSFET (solid line) and the conventional N-channel MOSFET (dashed line) thus formed. In a conventional MOSFET, only a 2000-nm-thick polysilicon electrode is used as an ion implantation mask for forming a source / drain. The absorbed dose is 1 MRad (S
i), the source / drain and the substrate were grounded as the bias conditions during irradiation, and the gate voltage was set to 5V.

Before gamma irradiation, there is no difference between the two characteristics. However, the amount of negative shift in characteristics due to gamma ray irradiation was
Is smaller. This reduces ion implantation damage to the gate oxide, reduces the amount of holes trapped in the gate oxide,
This reflects the decrease in the fixed charge accumulation amount.

In the conventional MOSFET, while the slope of the characteristic after irradiation becomes abnormally large, in the present embodiment, the fluctuation of the slope of the characteristic is suppressed to a small value. The amount of interface states generated at the boundary between the silicon substrate and the gate oxide film is reduced, and the leakage current in the gate voltage region where the channel is cut off is reduced by 10%.
It is as small as ^-12 A.

The fixed positive charge density accumulated in the gate oxide film during irradiation and the interface state density generated at the boundary between the silicon substrate and the gate oxide film are reduced, and the radiation resistance of the device is greatly improved.

Next, a second embodiment of the present invention will be described with reference to FIG.

A gate oxide film 2 is formed on a P-type silicon substrate 1 and an aluminum electrode 7 is formed on an N ⁺ -type source / drain 5 to constitute an N-channel MOSFET.

In this embodiment, a 2000-nm-thick silicon nitride film 8 is formed on the polysilicon gate electrode 3 as an ion implantation mask. The silicon nitride film has a higher implanted ion shielding power than the silicon oxide film, so that the thickness can be made smaller than when a silicon oxide film is used as a mask, and there is an advantage that the flatness of the element is improved.

〔The invention's effect〕

When performing ion implantation for source / drain formation, an insulating film having the same planar shape as the gate electrode is formed on the gate electrode, and the sum of the thicknesses of the insulating film and the gate electrode is reduced.
It is over 4000Å. Therefore, even if the thickness of the gate electrode is set to 3000 mm or less in order to improve the radiation resistance of the device, it is possible to prevent a decrease in radiation resistance due to ion implantation damage.

However, in order to improve the radiation resistance of the device by setting the gate electrode film pressure to 3000 ° or less, phosphorus is doped into the gate electrode by thermal diffusion below the gate oxidation temperature, and the phosphorus concentration at the gate electrode / gate oxide film interface is reduced to 1%. × 10 ²⁰ cm ^-3 or more.

In this way, the radiation resistance of the device was significantly improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) to 1 (d) are sectional views showing a first embodiment of the present invention in the order of steps, FIG. 2 is a sectional view showing a second embodiment of the present invention, FIG. 3 is a graph showing the sub-threshold current characteristics of the MOSFET before and after gamma ray irradiation, FIG. 4 is a graph showing the relationship between the phosphorus concentration at the interface between the gate electrode and the gate oxide film and the interface state density, and FIG. 4 is a graph showing the dependency of the density of positive charges accumulated in a gate oxide film on the thickness of an insulating film when a MOS capacitor having an insulating film formed on a gate electrode is irradiated with gamma rays. 1 ... P-type silicon substrate, 2 ... Gate oxide film, 3 ...
Gate electrode, 4 ... silicon oxide film, 5 ... N ⁺ type source / drain, 6 ... interlayer insulating film, 7 ... aluminum electrode, 8 ... silicon nitride film.

Claims (3)

(57) [Claims] An insulating film having the same planar shape as the gate electrode is formed on a gate electrode made of a phosphorus-doped polysilicon film, the thickness of the gate electrode is 3000 mm or less, and the thickness of the gate electrode is A semiconductor device including an insulated gate field effect transistor, wherein the sum of the thickness of the insulating film and the thickness of the insulating film is 4000 ° or more. 2. An insulating film having the same planar shape as the gate electrode is formed on a gate electrode made of a phosphorus-doped polysilicon film, wherein the thickness of the gate electrode is 3000 mm or less, and a gate oxide film and the gate electrode are formed. next concentration in the vicinity of the interface between the, 10 ²⁰
A semiconductor device including an insulated gate field effect transistor having a size of cm ^-3 or more. 3. The semiconductor device according to claim 1, wherein the doping of the polysilicon film of the gate electrode with phosphorus is performed at a temperature lower than a gate oxide film forming temperature. Manufacturing method.