JP2990915B2 - Control device for voltage fluctuation suppression device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a voltage fluctuation suppressing device installed in an AC power supply system, and more particularly to a TSC for controlling a voltage fluctuation by opening and closing a plurality of phase-advancing capacitors installed on a system bus. (Thyristor Switched Capacit
or) control method.

[0002]

TSC used in the Background of the Invention inhibit voltage fluctuation of the system bus purpose, as shown in FIG. 5, the phase advance capacitor C ₁ -C _n installed in the system bus 1, the thyristors Th ₁ ~
Opening / closing control is performed at Th _n to supply advanced power according to the voltage fluctuation to the system, thereby suppressing the voltage fluctuation due to the variable load 2 or the like.

In FIG. 5, a system bus 1 has a substation power supply E
Substation side Inpi the _S - connected through dance X _S, to supply the load 2 such as trains arriving. 3 ₁ ~3 _n the system bus 1
, The capacitors C _{1 to} C _n are connected to reactors L having a capacity of about several percent of the capacity of the capacitors.
And ₁ ~L _n, thyristor Th ₁ to TH _n and the diode D
It constituted a parallel circuit 4 ₁ to 4 _n of ₁ to D _n are connected in series.
The parallel circuit 4 ₁ to 4 _n, by on-off control of the current half-wave period in the thyristor Th ₁ to TH _n, and performs off-on-pulling capacitor C ₁ -C _n, in the OFF capacitor C ₁ -C _n waits in a state of being charged in the forward direction of the diode D ₁ to D _n.

[0004] 6 in the control device of the TSC, the system voltage V _l of the detected value V _in a set for each TSC was turned levels V _ref1 ~
Compared with V _refn , if it falls below this, the corresponding TSC
3 ₁ was charged to 3 _n capacitors C ₁ -C _n of, exceeds this level recovered voltage, tripping it.

[0005] In the control device 6, 7 in the power supply synchronous circuit, step-down transformer PT _1, connected to the system bus 1 through an input transformer PT _2, making the voltage synchronization signal from the system voltage V _l. 8 is a block zone circuit, for generating a block zone signal defining a non-ignition period of the thyristor Th ₁ to TH _n from the power source synchronization signal. 9 is a voltage detection circuit,
Voltage transformer PT _1, via the input transformer PT ₃ detects the bus voltage V _l of the system, and outputs the effective value as a voltage detection value V _in. 10 ₁ to 10 _n are setter for setting a charged level V _ref1 ~V _refn for each TSC3 ₁ ~3 _n, 11 ₁
In to 11 _n are subtracters, charged level V from the voltage detection value V _{in
ref1 to Vrefn} are subtracted. In 12 ₁ to 12 _n are adders adds the block zone signal to the subtraction value, and raising the subtraction value in the block zone period, the state that does not require this system voltage V _l is sufficiently high capacitor charged Shall correspond to 13 ₁ to 13 _n in the comparators a hysteresis function to prevent chattering, the adder 12 ₁ to 1
The output of the 2 _n is, (indicating that the voltage detection value V _in falls below the turned level V _ref1 ~V _refn) when below a certain level of voltage, generates a trigger signal of the thyristor, the corresponding TS
The gate of the thyristor Th ₁ to TH _n of C3 ₁ to 3 _n, and outputs through the amplifiers A ₁ to A _n. With this output, a number of phase-advancing capacitors C _{1 to} C _n corresponding to the decrease of the system voltage V _l
Is supplied to the system bus 1 to suppress voltage fluctuation.

[0006]

In the above conventional control method, the input level (tripping level) of the phase advance capacitors C _{1 to} C _n is a fixed value V _{ref1 to} V _refn , and only the voltage fluctuation ΔV due to the load fluctuation is obtained. Instead, it responds to the fluctuation of the power supply E _S.

For this reason, as shown in FIG. 6, there is a case where no response is made to the voltage fluctuation ΔV due to the load fluctuation, which is the original control target, or the capacity becomes insufficient. For example, if the voltage of the substation power supply E _S is large, even if there is a voltage dip ΔV due to a load change, the voltage value will be
b, the maximum value V of the input levels V _{ref1 to} V _refn
May exceeds the _MAX, not performed on of the power capacitor C ₁ -C _n is about that exceed the portion, not compensated. Further, when the voltage of the substation power supply E _S is low, the number of phase-advancing capacitors corresponding to the voltage is always turned on. Therefore, even if there is a voltage dip ΔV due to a load change as shown in FIG. Furthermore, the capacity of the capacitor to be supplied is insufficient, and the amount cannot be compensated.

In this case, if the total capacity of the capacitor is increased, it is possible to suppress the voltage dip ΔV when the system voltage E _S is low, but it is difficult to suppress the voltage dip ΔV when the system voltage E _S is high. There is a problem that the equipment cost also increases.

As described above, since the conventional equipment responds to the fluctuation of the power supply voltage E _S , the voltage fluctuation ΔV due to the load fluctuation, which is the original control purpose, cannot be completely compensated. There was a problem that the rate was low. Therefore, an object of the present invention is to provide a control device that can reliably compensate for a voltage change ΔV due to a load change if a phase-advancing capacitor having a capacity corresponding to the size of the load change is provided.

[0010]

SUMMARY OF THE INVENTION According to the present invention, a plurality of capacitors installed in a power supply system to supply advancing reactive power are controlled to open and close, and the number of the capacitors is switched in a stepwise manner to reduce a voltage change due to a load change in the system. A voltage detection circuit that detects a system voltage, a low-pass filter that extracts a long-period component of the detected system voltage and uses the voltage as a voltage reference value,
From this voltage reference value, a level determination circuit that determines the closing level and tripping level of the capacitor that follows the long-period component of the system voltage is compared with these levels and the detected system voltage. And a control circuit for increasing and decreasing the number of capacitors to be inserted so as to intervene.

[0011]

With the above arrangement, the long-period component of the power supply voltage not to be suppressed is detected by a low-pass filter, and this is set as a reference value, and the input level and trip level of the phase-advancing capacitor are determined so as to follow the reference value. Since the voltage fluctuation ΔV due to the load fluctuation to be controlled occurs in a form superimposed on this long-period component, if the number of phase-advancing capacitors is increased or decreased according to these levels, only the voltage fluctuation due to the load fluctuation is compensated. it can. Furthermore, if the TSC has a capacitor capacity of a size corresponding to the load fluctuation, the purpose of use can be achieved.
High facility utilization is obtained.

[0012]

FIG. 1 shows an embodiment of the present invention, which will be described below. Parts common to those in FIG. 5 are denoted by the same reference numerals. In Figure 1, 1 is the substation side Inpi from the substation supply E _S - the system bus to be powered through dance X _S, 2
Is a variable load such as a train load. In 3 ₁ ~3 _n is TSC,
A phase advancing capacitor C ₁ -C _n, a reactor L ₁ ~L _n with a capacity of about several% of phase advancing capacitor, the diode D ₁ reverse parallel circuit to D _n and the thyristor Th ₁ ~Th _n 4 ₁ ~4 _n are connected in series. This TSC3
The total capacity of _{1 to} 3 _n is large enough to suppress voltage fluctuation ΔV due to load fluctuation occurring in the system, that is,% Z (=
ΔV) = (total capacity of TSC) / (system short-circuit capacity P _S )
The relationship may be set as follows. In this embodiment, as an opening and closing circuit of a capacitor C ₁ -C _n, but using reverse parallel circuit 4 ₁ to 4 _n diode and a thyristor, it is used after reverse parallel connection pairs thyristor Good.

Reference numeral 14 denotes a control device for controlling the opening and closing of the thyristors Th _{1 to} Th _n of the TSC according to the load fluctuation of the system bus 1. In this control device 14, reference numeral 7 denotes a power supply synchronization circuit constituted by a PLL circuit, and a step-down transformer P
T _1, via the input transformer PT ₂ connected to the system bus 1, taking the power synchronization signal bus voltage V _l. 8 is a block zone circuit receives the power-supply sync signal, is energized to the diode D ₁ to D _n, as shown in the figure, the thyristor T
to h ₁ to TH _n period of not energized (hatched portion) for generating a block zone signal V _B. In addition, the thyristor Th ₁ ~Th
_n energization period (the gate pulse generation period) is approximately 90 ° to a current bus voltage V _l flowing through the capacitor C ₁ -C _n
Since the relationship is advanced, the period is as shown by the diagonal lines in FIG.

[0014] 9 is the voltage detection circuit, the step-down the bus voltage V _l transformer PT _1, received through the input transformer PT _3, and outputs the effective value as a voltage detection value V _in. 15 receives the voltage detection value V _in, a low-pass filter for outputting the long-period components as extraction voltage reference value V _S, for example, the gain K ≧ 1, the time constant ST ₁ used after a few tens of seconds.

[0015] 16 in the level determination circuit, for example, a resistor R _1, R _2, R ₃ as shown is composed of a voltage dividing circuit connected in series, the voltage reference value V _s of the output of the low pass filter 15, a predetermined by applying in a ratio minutes, phase advancing capacitor C ₁ ~
Determining a charged level V _REFI and trip level V _REFO of C _n. In this embodiment, the input level is V _{refI
= K · V in · R 3} / (R 1 + R 2 + R 3), pull-off _{level, V refO = K · V in} · (R 2 + R 3) / (R 1 + R 2 + R
₃ ) However, K · V _in = V _S.

Reference numeral 17 denotes first and second comparators 18 ₁ , 1
8 ₂ compares the up-down counter 19, with the opening and closing control circuit of a capacitor and an output circuit 20, the voltage detection value V _in a charged level V _REFI and pull-off levels V _REFO,
The voltage detection value V _in to increase or decrease the feed amount of the capacitor C ₁ -C _n to fall between these levels _V refI, V refO.

[0017] In this switching control circuit 17, first comparator 18 _1, when the voltage detection value V _in falls below the turned level V _REFI, and outputs a count-up signal to the up-down counter 19. Second comparator 18 _2, the voltage detection value V _in when exceeds the tripping level V _REFO, and outputs a count-down signal to the up-down counter 19. The up / down counter 19 has a decode output in which the output terminals from the minimum digit to the digit corresponding to the count value are set to a high level (capacitor input command), and the digits ₁ to _n of the output terminal are TSC3 _{1 to} 3 respectively. _There is a one-to-one correspondence with _n . The output circuit 20, an adder 2 for forcibly low the decoded output during the generation period of the block zone signal V _B
And 1 ₁ through 21 _n, and amplifies the decoded output that has passed through the adder, and outputs to the gate of the thyristor Th ₁ to TH _n corresponding TSC as a trigger pulse is composed of a amplifier A ₁ to A _n . This configuration is such that the thyristors Th _{1 to} Th of the TSC corresponding to the high-level digit of the decode output
_n is made conductive at a predetermined timing shown in FIG. 2, and the capacitors C _{1 to} C _n are supplied to the system bus 1.

The operation of the apparatus shown in FIG. 1 will be described with reference to waveform diagrams shown in FIGS. When power E _S that varies long period (several minutes), as shown in FIG. 3 is supplied to the system bus 1, and the train load 2 arrives, drawing a, b, a voltage such as c dip ΔV Consider the case where this occurs, which is suppressed by the device of the present invention. In this case, the total capacitance of the TSC capacitor is, as described above, the voltage drop Δ
Because it is set by assuming the size and V, these are the voltage adjustment range of the capacitor C ₁ -C _n.

The charged level V _REFI and trip level V _REFO output by the level determining circuit 16, so follow the bus voltage V _l to the voltage reference value V _S is taken out of the long-period component, the voltage dip a, b, c even at the time of the throat, these levels V _REFI, V _REFO a voltage detection value V _in of the bus voltage V _l
Has a relationship as shown in FIG.

[0020] Beginning a voltage dip ΔV by the train load 2 arrives, when the voltage detection value V _in attempts to lower than charged level V _REFI, and the first comparator 18 ₁ detects this,
The up / down counter 19 counts up by one.
As a result, only the least significant digit of the output terminal becomes high level,
The output circuit 20 is connected to the thyristor Th of the corresponding TSC.
_{At 1} , the trigger pulse output at the timing shown in FIG. 2 is started. Thus, the system voltage V _l, the capacitor C ₁
And the voltage fluctuation is suppressed. Bus voltage V _l power supply to the load 2 becomes larger is gradually lowered, when the voltage detection value V _in attempts to lower than charged level V _REFI again, the first comparator 18 ₁ again, the up-down The counter 19 is incremented by one. Thus, the output circuit 20 are thyristors TSC Th _1, Th ₂
Is conducted, the number of capacitors supplied to the system bus 1 increases by one, and the voltage dip ΔV is suppressed again. This additional charging operation of the capacitor is performed in response to an increase in the power supply to the load 2, and when the power supplied to the load does not change, there is no increase or decrease in the number of capacitors. When the train load 2 away decrease in the power supply begins, because the system voltage V _l rises, the voltage detection value V _in to try to Uwamawaro the tripping level _V refO. This is detected by the second comparator 18 _2, each time, the up-down counter 1
9 is counted down one by one, and the number of capacitors C _{1 to} C _n of the TSC to the system bus 1 is decreased by one.
The bus voltage _Vl is prevented from becoming larger. Thus, the capacitors C ₁ to
Since it increased or decreased stepwise feed amount of C _n, turned finish voltage V _l of the system bus 1 level V _REFI and tripping level V
can be maintained during _refO , and voltage fluctuation due to load fluctuation Δ
V can always be suppressed.

[0021]

According to the present invention, only the voltage fluctuation ΔV due to the load fluctuation can be suppressed without being affected by the power fluctuation. In particular, the capacitor C ₁ -C _n of TSC is because it is used only for voltage fluctuation ΔV due to load fluctuations, be determined by corresponding the capacitance to the load variation of the system, ensures the voltage variation ΔV It is possible to reduce the installed capacity of the capacitor and improve the equipment utilization rate as compared with the conventional equipment which can suppress the power supply and respond to the power supply fluctuation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a voltage fluctuation suppressing device according to an embodiment of the present invention.

FIG. 2 is a conduction timing diagram of a thyristor and a diode of the capacitor switching circuit in FIG. 1;

FIG. 3 is a voltage waveform diagram showing a state in which voltage fluctuation is suppressed by opening and closing a phase-advancing capacitor in the voltage fluctuation suppressing device shown in FIG. 1;

FIG. 4 is an enlarged waveform diagram showing a portion corresponding to a load change in the voltage waveform diagram shown in FIG. 3 in correspondence with the number of input phase-advancing capacitors;

FIG. 5 is a block diagram showing a conventional voltage fluctuation suppressing device using a phase advance capacitor.

6 is a bus voltage waveform chart when voltage fluctuation is suppressed by the device shown in FIG. 5;

[Explanation of symbols]

Reference Signs List 1 system bus 2 variable load 9 voltage detection circuit 15 low-pass filter 17 control circuit 3 _{1 to} 3 _n TSC C _{1 to} C _n advance capacitor Th _{1 to} Th ₂ thyristor

Claims (1)

(57) [Claims] 1. A system in which a plurality of capacitors installed in a power supply system for supplying leading phase power are controlled to open and close, and the number of capacitors is switched in a stepwise manner to suppress voltage fluctuations due to load fluctuations in the system. A voltage detection circuit for detecting, a low-pass filter that extracts a long-period component of the detected system voltage and uses it as a voltage reference value, and a level determination circuit that determines a closing level and a tripping level of a capacitor corresponding to the voltage reference value. ,
A control circuit for comparing the two levels with the detected system voltage, and increasing or decreasing the number of inserted capacitors so that the system voltage falls between the two levels. .