JP2991753B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2991753B2 JP2991753B2 JP2225797A JP22579790A JP2991753B2 JP 2991753 B2 JP2991753 B2 JP 2991753B2 JP 2225797 A JP2225797 A JP 2225797A JP 22579790 A JP22579790 A JP 22579790A JP 2991753 B2 JP2991753 B2 JP 2991753B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- extended drain
- drain region
- conductivity type
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
- H10D62/314—Channel regions of field-effect devices of FETs of IGFETs having vertical doping variations
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置とその製造方法に関し、特にドレ
イン−ソース間の降伏電圧を高くする必要があるMOSFET
として利用できるものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a MOSFET that requires a high drain-source breakdown voltage.
It can be used as
従来の技術 第２図に従来の高耐圧横型MOSFETの断面を示す。ドレ
イン20−ソース23間の降伏電圧を高くするため、半導体
基板25内に不純物濃度の低い延長ドレイン領域21を形成
し、ドレイン20−ソース23間が逆バイアスされた場合、
延長ドレイン領域21に空乏層が広がるようにしている。
なお、図中、16はドレイン電極、17はソース電極、18は
シリコン酸化膜、19はゲート電極、22はアンテパンチス
ルー領域、24は基板コンタクト領域である。2. Prior Art FIG. 2 shows a cross section of a conventional high breakdown voltage lateral MOSFET. In order to increase the breakdown voltage between the drain 20 and the source 23, an extended drain region 21 having a low impurity concentration is formed in the semiconductor substrate 25, and when a reverse bias is applied between the drain 20 and the source 23,
The depletion layer extends in the extended drain region 21.
In the figure, 16 is a drain electrode, 17 is a source electrode, 18 is a silicon oxide film, 19 is a gate electrode, 22 is an antenna punch-through region, and 24 is a substrate contact region.
発明が解決しようとする課題 上記のような延長ドレイン領域をもうけた従来構造で
は、逆電圧がかかったとき、延長ドレイン領域21と半導
体基板25間の接合より空乏層が広がるが、ドレイン20−
ソース23間降伏電圧を高くするため延長ドレイン領域21
が空乏化するように延長ドレイン領域21の濃度を低くし
なければならない。このことによって高耐圧は実現でき
るが、延長ドレイン領域21内の抵抗成分が大きくなり、
MOSFETのドレイン20−ソース23間オン抵抗が大きくなっ
てしまい、動作時の損失が大きくなり、大電流を流すた
めには、素子サイズを大きくしなければならなくなると
いう欠点があった。According to the conventional structure having the extended drain region as described above, when a reverse voltage is applied, a depletion layer expands from the junction between the extended drain region 21 and the semiconductor substrate 25.
Extended drain region 21 to increase breakdown voltage between sources 23
, The concentration of the extended drain region 21 must be reduced so that the depletion occurs. Although a high withstand voltage can be realized by this, the resistance component in the extended drain region 21 increases,
The on-resistance between the drain 20 and the source 23 of the MOSFET is increased, the loss during operation is increased, and the element size must be increased in order to flow a large current.
課題を解決するための手段 上記の問題点を解決するため、本発明では、第１導電
型半導体基板の一表面に設けられた第２導電型のソース
領域と、前記半導体基板の一表面に設けられた第２導電
型の延長ドレイン領域と、前記ソース領域と前記延長ド
レイン領域との間に設けられたチャネル領域と、前記チ
ャネル領域上にゲート酸化膜を介して設けられたゲート
電極と、前記延長ドレイン領域内であって基板表面に面
して設けられたドレインコンタクトを備え、前記延長ド
レイン領域内に設けられ、前記延長ドレイン領域と逆バ
イアスされた第１導電型の埋め込み領域を設けた構造と
なる。また、前記第２導電型の延長ドレイン領域内に第
１導電型の不純物としてボロン注入後、そのイオン注入
された第２導電型領域表面を酸化することにより前記第
１導電型の埋め込み領域を形成する。Means for Solving the Problems To solve the above problems, according to the present invention, a source region of a second conductivity type provided on one surface of a semiconductor substrate of a first conductivity type, and a source region provided on one surface of the semiconductor substrate are provided. An extended drain region of the second conductivity type, a channel region provided between the source region and the extended drain region, a gate electrode provided on the channel region via a gate oxide film, A structure comprising a drain contact provided in the extended drain region and facing the substrate surface, and a buried region of a first conductivity type provided in the extended drain region and reversely biased to the extended drain region. Becomes In addition, after boron is implanted as an impurity of the first conductivity type into the extended drain region of the second conductivity type, the surface of the ion-implanted second conductivity type region is oxidized to form the buried region of the first conductivity type. I do.
作用 このような本発明の構造をとることで高耐圧を実現し
つつ、ドレイン−ソース間オン抵抗を大幅に低下するこ
とができる。Action By adopting such a structure of the present invention, it is possible to greatly reduce the drain-source on-resistance while realizing a high breakdown voltage.
実 施 例 第１図に本発明の半導体装置の一実施例におけるＮチ
ャネルMOSFETの断面を示す。延長ドレイン領域11の表面
濃度は約１×1016cm-3とし、この延長ドレイン領域11内
にＰ型領域10を形成し、このＰ型領域10の濃度は５×10
16cm-3以上とした。半導体基板15の濃度は３×1014cm-3
とし、半導体基板15の表面のシリコン酸化膜８の厚さは
２μｍ以上とした。ゲート電極７には多結晶シリコン膜
を使用した。ゲート電極７下に位置するシリコン酸化膜
がゲート酸化膜となる。Ｐ型領域10を形成するには、ま
ず延長ドレイン領域11を、半導体基板15へのイオン注
入、不純物ドープ、拡散で形成した後、Ｐ型領域10の不
純物をドープするため延長ドレイン領域11にボロンをイ
オン注入し、若干の熱処理をおこなった後、半導体基板
15の表面を熱酸化する。このことでシリコン酸化膜８と
シリコン間のボロンの偏析係数が異なることから、基板
15表面のボロン濃度が低下しＮ型となり、Ｐ型領域10は
Ｎ型延長ドレイン領域11中に埋め込まれた構造となる。
Ｐ型領域10はドレインコンタクト領域９とゲート電極７
との間に配置される。このＰ型領域10をドレイン領域11
と逆バイアスすることで延長ドレイン領域11と半導体基
板15間、及び上記延長ドレイン領域11中のＰ型領域10と
延長ドレイン領域11間に空乏層が広がる。したがって従
来構造の場合とちがって、延長ドレイン領域11の濃度を
高くしても、延長ドレイン領域11を空乏化できる。した
がってドレイン−ソース間オン抵抗を従来構造のMOSFET
よりも小さくすることができる。このことで従来構造の
MOSFETと比較して単位面積当りのドレイン−ソース間オ
ン抵抗は1/5〜1/6にできた。FIG. 1 shows a cross section of an N-channel MOSFET in an embodiment of the semiconductor device of the present invention. The surface concentration of the extended drain region 11 is about 1 × 10 16 cm −3, and a P-type region 10 is formed in the extended drain region 11, and the concentration of the P-type region 10 is 5 × 10 16
It was 16 cm -3 or more. The concentration of the semiconductor substrate 15 is 3 × 10 14 cm −3
The thickness of the silicon oxide film 8 on the surface of the semiconductor substrate 15 was 2 μm or more. A polycrystalline silicon film was used for the gate electrode 7. The silicon oxide film located under the gate electrode 7 becomes a gate oxide film. To form the P-type region 10, first, the extended drain region 11 is formed by ion implantation, impurity doping, and diffusion into the semiconductor substrate 15, and then boron is added to the extended drain region 11 to dope the P-type region 10 with impurities. After a slight heat treatment, the semiconductor substrate
Thermal oxidation of 15 surfaces. As a result, the segregation coefficient of boron between the silicon oxide film 8 and silicon is different.
The boron concentration on the surface 15 is reduced to N-type, and the P-type region 10 has a structure embedded in the N-type extended drain region 11.
The P-type region 10 includes a drain contact region 9 and a gate electrode 7.
And placed between. This P-type region 10 is
The depletion layer spreads between the extended drain region 11 and the semiconductor substrate 15 and between the P-type region 10 and the extended drain region 11 in the extended drain region 11 by reverse biasing. Therefore, unlike the case of the conventional structure, even if the concentration of the extended drain region 11 is increased, the extended drain region 11 can be depleted. Therefore, the on-resistance between drain and source is
Can be smaller than This makes the conventional structure
The drain-source on-resistance per unit area was reduced to 1/5 to 1/6 compared to MOSFET.
発明の効果 以上のように本発明によれば、高耐圧横型MOSFETのチ
ップサイズを縮小することができる。Advantageous Effects of the Invention As described above, according to the present invention, the chip size of a high breakdown voltage lateral MOSFET can be reduced.
第１図は本発明の一実施例におけるＮチャネルMOSFETの
断面図、第２図は従来の高耐圧横型MOSFETの断面図であ
る。 １……ドレイン端子、２……延長ドレイン中Ｐ型領域電
極端子、３……ゲート電子、４……ソース端子、５……
ドレイン電極、６……ソース電極、７……ゲート電極、
８……シリコン酸化膜、９……ドレインコンタクト領
域、10……延長ドレイン領域内Ｐ型領域、11……延長ド
レイン領域、12……アンチパンチスルー領域、13……ソ
ース領域、14……基板コンタクト領域、15……半導体基
板。FIG. 1 is a sectional view of an N-channel MOSFET according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional high breakdown voltage lateral MOSFET. 1 ... Drain terminal, 2 ... P-type region electrode terminal in extended drain, 3 ... Gate electron, 4 ... Source terminal, 5 ...
Drain electrode, 6 ... source electrode, 7 ... gate electrode,
8 ... silicon oxide film, 9 ... drain contact region, 10 ... P-type region in extended drain region, 11 ... extended drain region, 12 ... anti-punch through region, 13 ... source region, 14 ... substrate Contact area, 15 ... Semiconductor substrate.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 川崎 英夫 大阪府門真市大字門真1006番地 松下電 子工業株式社内 (72)発明者 進藤 裕之 大阪府門真市大字門真1006番地 松下電 子工業株式社内 (72)発明者 宇野 利彦 大阪府門真市大字門真1006番地 松下電 子工業株式社内 (56)参考文献 特開 平１−238062（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 29/78 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideo Kawasaki 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Denko Kogyo Co., Ltd. 72) inventor Toshihiko Uno Osaka Prefecture Kadoma Oaza Kadoma 1006 address Matsushita electronic industrial stock company (56) reference Patent flat 1-238062 (JP, a) (58 ) investigated the field (Int.Cl. 6, DB Name) H01L 29/78
Claims (4)
た第２導電型のソース領域と、前記半導体基板の一表面
に設けられた第２導電型の延長ドレイン領域と、 前記ソース領域と前記延長ドレイン領域との間に設けら
れたチャネル領域と、前記チャネル領域上にゲート酸化
膜を介して設けられたゲート電極と、前記延長ドレイン
領域内であって基板表面に面して設けられたドレインコ
ンタクト領域 を備えた半導体装置であって、 前記延長ドレイン領域内に設けられ、前記延長ドレイン
領域と逆バイアスされた第１導電型の埋め込み領域を設
けた半導体装置。A second conductive type source region provided on one surface of the first conductive type semiconductor substrate; a second conductive type extended drain region provided on one surface of the semiconductor substrate; and the source region. A channel region provided between the semiconductor device and the extended drain region, a gate electrode provided on the channel region via a gate oxide film, and provided in the extended drain region and facing a substrate surface. A semiconductor device comprising: a drain contact region; a buried region of a first conductivity type provided in the extended drain region and reversely biased to the extended drain region.
レインコンタクト領域と前記ゲート電極との間の前記延
長ドレイン領域内に配置した請求項１記載の半導体装
置。2. The semiconductor device according to claim 1, wherein said buried region of said first conductivity type is disposed in said extended drain region between said drain contact region and said gate electrode.
って、第２導電型の延長ドレイン領域を設ける工程と、
前記延長ドレイン領域内に第１導電型の不純物をボロン
のイオン注入で埋め込む工程とを設けた半導体装置の製
造方法。3. The method for manufacturing a semiconductor device according to claim 1, wherein an extended drain region of a second conductivity type is provided;
Embedding a first conductivity type impurity in the extended drain region by boron ion implantation.
のイオン注入された第２導電型領域表面を酸化すること
で前記第１導電型領域を形成する請求項３記載の半導体
装置の製造方法。4. The semiconductor device according to claim 3, wherein after the ion implantation for forming the first conductivity type region, the surface of the second conductivity type region implanted with the ion is oxidized to form the first conductivity type region. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2225797A JP2991753B2 (en) | 1990-08-27 | 1990-08-27 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2225797A JP2991753B2 (en) | 1990-08-27 | 1990-08-27 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04107877A JPH04107877A (en) | 1992-04-09 |
| JP2991753B2 true JP2991753B2 (en) | 1999-12-20 |
Family
ID=16834933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2225797A Expired - Fee Related JP2991753B2 (en) | 1990-08-27 | 1990-08-27 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2991753B2 (en) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5482888A (en) * | 1994-08-12 | 1996-01-09 | United Microelectronics Corporation | Method of manufacturing a low resistance, high breakdown voltage, power MOSFET |
| US6168983B1 (en) | 1996-11-05 | 2001-01-02 | Power Integrations, Inc. | Method of making a high-voltage transistor with multiple lateral conduction layers |
| US6639277B2 (en) | 1996-11-05 | 2003-10-28 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
| US6207994B1 (en) * | 1996-11-05 | 2001-03-27 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
| JP3175923B2 (en) * | 1997-11-05 | 2001-06-11 | 松下電子工業株式会社 | Semiconductor device |
| JP3142057B2 (en) * | 1997-11-13 | 2001-03-07 | 日本電気株式会社 | Semiconductor device, manufacturing method thereof, and driving device |
| US6534829B2 (en) * | 1998-06-25 | 2003-03-18 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP3059423B2 (en) | 1998-10-19 | 2000-07-04 | 松下電子工業株式会社 | Method for manufacturing semiconductor device |
| US6768171B2 (en) | 2000-11-27 | 2004-07-27 | Power Integrations, Inc. | High-voltage transistor with JFET conduction channels |
| US6509220B2 (en) | 2000-11-27 | 2003-01-21 | Power Integrations, Inc. | Method of fabricating a high-voltage transistor |
| US6424007B1 (en) | 2001-01-24 | 2002-07-23 | Power Integrations, Inc. | High-voltage transistor with buried conduction layer |
| US6635544B2 (en) | 2001-09-07 | 2003-10-21 | Power Intergrations, Inc. | Method of fabricating a high-voltage transistor with a multi-layered extended drain structure |
| US6573558B2 (en) | 2001-09-07 | 2003-06-03 | Power Integrations, Inc. | High-voltage vertical transistor with a multi-layered extended drain structure |
| US7786533B2 (en) | 2001-09-07 | 2010-08-31 | Power Integrations, Inc. | High-voltage vertical transistor with edge termination structure |
| US6555873B2 (en) | 2001-09-07 | 2003-04-29 | Power Integrations, Inc. | High-voltage lateral transistor with a multi-layered extended drain structure |
| US6555883B1 (en) | 2001-10-29 | 2003-04-29 | Power Integrations, Inc. | Lateral power MOSFET for high switching speeds |
| US7595523B2 (en) | 2007-02-16 | 2009-09-29 | Power Integrations, Inc. | Gate pullback at ends of high-voltage vertical transistor structure |
| US7859037B2 (en) | 2007-02-16 | 2010-12-28 | Power Integrations, Inc. | Checkerboarded high-voltage vertical transistor layout |
| CN102544092A (en) * | 2010-12-16 | 2012-07-04 | 无锡华润上华半导体有限公司 | CMOS (complementary metal oxide semiconductor) device and manufacturing method thereof |
| US9660053B2 (en) | 2013-07-12 | 2017-05-23 | Power Integrations, Inc. | High-voltage field-effect transistor having multiple implanted layers |
| US10325988B2 (en) | 2013-12-13 | 2019-06-18 | Power Integrations, Inc. | Vertical transistor device structure with cylindrically-shaped field plates |
-
1990
- 1990-08-27 JP JP2225797A patent/JP2991753B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04107877A (en) | 1992-04-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2991753B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3158973B2 (en) | Silicon carbide vertical FET | |
| JPH0330310B2 (en) | ||
| JP2002124671A (en) | Semiconductor device and manufacturing method thereof | |
| JPH02203566A (en) | Mos type semiconductor device | |
| US5912491A (en) | MOS device | |
| JP2004207492A (en) | Method for manufacturing semiconductor device | |
| JPH04125972A (en) | Mos semiconductor element and manufacture thereof | |
| JPS6241428B2 (en) | ||
| JP2817247B2 (en) | Semiconductor device | |
| JP4797280B2 (en) | Semiconductor device | |
| KR100252747B1 (en) | Flash memory device and manufacturing method thereof | |
| JP2864499B2 (en) | Field effect thin film transistor | |
| JPH0851198A (en) | Semiconductor device | |
| JP3274254B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH04256370A (en) | Semiconductor device | |
| JPS61203679A (en) | Mos transistor of high withstand voltage | |
| KR970024287A (en) | Silicon-On-Insulator MOS transistor and fabricating method | |
| JP3167046B2 (en) | Static induction semiconductor device | |
| JP2658163B2 (en) | Method of manufacturing MIS type semiconductor device | |
| JPS63133677A (en) | Field-effect semiconductor device | |
| JPH03242976A (en) | Semiconductor device | |
| JPH0770723B2 (en) | Dual gate MOS field effect transistor | |
| JPS6369271A (en) | Semiconductor device and manufacture thereof | |
| JPH05102466A (en) | Mos type semiconductor device and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081015 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091015 Year of fee payment: 10 |
|
| LAPS | Cancellation because of no payment of annual fees |