JP2991767B2 - Quantization circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quantization circuit for compressing and encoding input image data, and more particularly to a quantization circuit suitable for applying to a high-efficiency compression encoding technique for natural images. is there.

[Conventional technology]

As a high-efficiency compression coding technology for natural images (still images), a method combining orthogonal transform with variable-length code is considered to be effective, and this method will be adopted as an international standard for color still image coding. (See Journal of the Institute of Image Electronics Engineers of Japan; Vol. 18, No. 6, pp. 398-407).

FIG. 5 is a schematic diagram showing the processing procedure of the “baseline system” of the international standardization system. This system converts input image data into n × n pixels of one block, for example, 8
It is divided into a plurality of blocks of × 8 pixels, and two-dimensional discrete cosine transform (DCT: Discrete Cosine Transfor
m) (Process P1), and obtain the obtained n × n DCT coefficients by n
Quantization is performed by dividing by each threshold of a quantization matrix composed of × n thresholds (process P2). FIG. 6 shows an example of the quantization matrix.

DCT is a type of orthogonal transform in the frequency domain. The transform coefficient is Fuv (u, v = 0, 1,..., N−1), and the input image data for one block is fij (i, j = 0, 1,. , n-1), Is defined by The obtained transform coefficient Fuv represents a component obtained by decomposing one block of input image data into spatial frequencies, and the coefficient F00 represents a value (DC component) proportional to the average value of 8 × 8 pixels of the input image data fij. , The components (AC components) having higher spatial frequencies as the variables u and v increase.

The DC component of the quantized DCT coefficients is different from the DC component quantized in the previous block (process P3), and the number of bits of the difference is Huffman-coded (process P4). The alternating current (AC) component is converted into a one-dimensional sequence by performing a zigzag scan within the block, and the number of consecutive invalid coefficients (zero) is run-length coded (process P3). Two-dimensional Huffman coding is performed with the number of bits (process P4). FIG. 7 shows an example of a zigzag scan.

At the time of quantization in the process P2, each threshold of the quantization matrix is multiplied by a coefficient 2 ^S (S = 0, ± 1, ± 2,...), And then DCT coefficient division is performed. Width S of the coefficient 2 ^S is referred to as scale factor, the image quality and compression rate after the compression can be adjusted by the scale factor S.

FIG. 8 is a schematic diagram showing a procedure of a rounding process at the time of quantization. In this processing, when the DCT coefficient Fuv is divided by each threshold value Quv of the quantization matrix, when the DCT coefficient Fuv is positive, “Quv /
When "2" is added, the division is performed, and when it is negative, "Quv / 2" is subtracted and then divided (processing P5), and the decimal part is truncated (processing P6). In this way, the rounding can be performed symmetrically with respect to positive and negative. For example, “+4.5” in decimal notation becomes “+
5 "and" -4.5 "can be rounded to" -5 ", respectively.

[Problems to be Solved by the Invention] By the way, the above-mentioned “baseline system” is a DSP (Digital Signal Process
Although some examples of hardware implementation using r) have been reported, the processing is time-consuming and not practical.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a quantization circuit which realizes high-speed quantization processing of image data by realizing hardware of the above-described quantization processing and rounding processing.

[Means for solving the problem]

A quantization circuit according to the present invention includes a quantization table in which a quantization table value for quantizing input data at a predetermined quantization step width is stored. A first barrel shifter for bit-shifting, a reciprocal table for outputting the quantization table value or a reciprocal of the output of the first barrel shifter, and an output of the reciprocal table on the LSB side according to the scale factor value. A second barrel shifter for shifting, a multiplier for multiplying the input data by an output of the reciprocal table or an output of the second barrel shifter to quantize the input data, and rounding an output of the multiplier A rounding circuit for converting the quantization table value to the first barrel when the value of the scale factor is negative. After the bit is shifted to the LSB side by the lid, it is converted to the reciprocal by the reciprocal table. When the value of the scale factor is positive, the quantization table value is converted to the reciprocal by the reciprocal table, and the LSB is converted by the second barrel shifter. The bits are shifted to the side and input to the multipliers.

The rounding circuit adds an n-bit pattern of “01... 1” to the lower n bits when the output of the multiplier is negative, and “10... 0” when the output of the multiplier is positive.
Are added and the lower n bits are rounded down to round off symmetrically.

(Operation)

In the present invention, quantization of input data is performed by reading the reciprocal of the quantization table value stored in the quantization table from the reciprocal table and multiplying the input data by the reciprocal. Further, to adjust the data amount after quantization by changing the quantization step size by multiplying the coefficient 2 ^S to the quantization table value.

Multiplying the coefficient 2 ^S into a digital (binary) data, S is the MSB side digital data is a positive case, S is when the negative equivalent to S bits respectively shifted to the LSB side. Therefore, in the present invention, digital data, that is, quantization table values are bit-shifted by the first and second barrel shifters. In this case, after taking the reciprocal of the quantization table value when the scale factor S is negative, if this reciprocal is shifted to the MSB side, a correct value cannot be obtained. Therefore, the reciprocal is calculated after shifting the quantization table value to the LSB side. Need to take. When the scale factor S is positive, if the reciprocal is obtained after shifting the quantization table value, the number of address bits of the reciprocal table increases and a large capacity memory is required for the reciprocal table. In the case of a positive value, the reciprocal of the quantization table value is calculated and then shifted to the LSB side.

Therefore, according to the present invention, when the scale factor S is negative, the quantization table value is shifted S bits to the LSB side by the first barrel shifter, and then the reciprocal is obtained by the reciprocal table.
When the scale factor S is positive, the reciprocal of the quantization table value is obtained by the reciprocal table, and then the second barrel shifter
An S-bit shift is performed to the LSB side.

In addition, the rounding process of the output data of the multiplier, that is, the quantization data, is performed in a positive / negative symmetry by adding 1/2 LSB and rounding down when the quantization data is positive, and subtracting and rounding up 1/2 LSB when the quantization data is negative. Round off. For example, in the case of 2-bit data after the decimal point, if the data is negative, "0"
... 0.01 "are added and then two bits after the decimal point are rounded down. If positive," 0 .. 0.10 "is added and then two bits after the decimal point are rounded down.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a quantization circuit according to the present invention, in which the processing P2 in FIG. 5 and the processing P5 in FIG. 8 are implemented in hardware.

This quantization circuit uses 8 × 8 as a quantization table value.
ROM-based quantization table 1 in which each threshold data group of the quantization matrices is stored.
The bit shift circuit 2 takes the reciprocal of each of the threshold data output from, and performs bit shift by the scale factor S. The DCT coefficient is multiplied by the output (reciprocal of the threshold data) of the bit shift circuit 2 to quantize the DCT coefficient. A multiplier 3, a rounding circuit 4 for rounding the output of the multiplier 3, and a switching circuit 5 for selectively switching and outputting the output of the rounding circuit 4 and the DCT coefficient. The switching circuit 5 is output from the bit shift circuit 2. The switching is controlled by the switching signal SW1.

FIG. 2 is a block diagram showing an example of the bit shift circuit 2. The barrel shifter 20 shifts each threshold data of the quantization matrix output from the quantization table 1 to the LSB side by S bits, and is output from the quantization table 1. Circuit 21 for selectively switching and outputting threshold data and data output from barrel shifter 20, reciprocal table 22 for reciprocal of the data selected by switching circuit 21, and reciprocal table
Barrel shifter 2 that shifts the output of 22 to the LSB side by S bits
3, a switching circuit 24 for selectively switching and outputting between the output of the reciprocal table 22 and the output of the barrel shifter 23, wherein the barrel shifter 20 is shift-controlled by the output of the decoder 25, and the barrel shifter 23 is shift-controlled by the output of the decoder 26. Is done. A scale factor S is input to both decoders 25 and 26. A detection circuit 27 is connected to an output of the switching circuit 21. The detection circuit 27 determines whether the threshold data after the shift in the barrel shifter 20 is “0” or “1”.
In this case, the switching circuit 5 is switched and controlled to output the DCT coefficient without quantization.

FIG. 3 is a block diagram showing an example of the rounding circuit 4. The exclusive OR (EXO) of the sign bit (MSB) of the 16-bit data output from the multiplier 3 and the fixed data "10000" is shown in FIG.
R) EXOR circuit 30, which takes R), an adder 31 that adds the output of the EXOR circuit 30 to the lower 5 bits of the 16-bit data and outputs the upper 11 bits after the addition, and the output of the adder 31 and the maximum positive value Switching circuit 3 for switching between data "011 ... 1" (11 bits)
2. Compare the sign bit of the input threshold value data with the sign bit of the data output from the adder 31, and when the sign bit is inverted from positive to negative, the switching circuit 32 outputs the maximum positive value data. And a sign bit check circuit 33 for switching the switching circuit 32.

In this configuration, each threshold data of the quantization matrix output from the quantization table 1 is multiplied by a coefficient 2 ^S in a bit shift circuit 2, and the reciprocal thereof is input to a multiplier 3. Multiplication factor 2 ^S in a digital circuit a target data can be achieved by S bit shift. In the bit shift circuit 2, when the scale factor S is negative, the threshold data is shifted to the LSB side by the barrel shifter 20, and when the scale factor S is positive, the reciprocal is obtained by a reciprocal table, and then the barrel shifter 23 shifts the threshold data to the LSB side. shift. In this case, in the decoder 25, when the lower three bits of the 5-bit scale factor S are “0”, “8”,
"1" is "7", ..., "6" is "2",
When it is "7", it is converted to "1" (both in decimal notation) and output.

When the scale factor S is negative, the switching circuit 21
Selects the output of the barrel shifter 20 and the switching circuit 24 selects the output of the reciprocal table 22. When the scale factor S is positive, the switching circuit 21 selects the input threshold data, and the switching circuit 24 selects the output of the barrel shifter 23. Therefore, when the scale factor S is negative, the input threshold data is shifted to the LSB side by the barrel shifter 20, converted into an inverse by the reciprocal table 22, and output.
Also, when the scale factor S is positive, the input threshold data is converted into an inverse by the reciprocal table 22 and is converted by the barrel shifter 23.
It is shifted to the LSB side and output. As described above, when the scale factor S is positive, the reciprocal of the threshold data is obtained, and then the bit shift is performed, thereby preventing the number of input (address) bits of the reciprocal table 22 from increasing. When the shifted threshold data in the barrel shifter 20 becomes “0” or “1” when the scale factor S is negative,
The detection circuit 27 detects the state and controls the switching circuit 5,
Output the DCT coefficients without quantization.

By the way, since the quantization is a division, when the quantization is performed using the multiplier 3, it is necessary to find the reciprocal using the reciprocal table 22. Therefore, it is conceivable to have the reciprocal of the threshold data as a table in the quantization table 1 from the beginning and omit the reciprocal table 22. However, in this case, if the threshold data is shifted by the barrel shifter 20 in a direction in which the threshold data is reduced, there is a disadvantage that correct quantization is not performed. For example, if the threshold value data “11” (decimal) is bit-shifted by the scale factor “−2” and then the reciprocal is obtained,
Since "11" is "00001011" in a binary number, if this is shifted by two bits to the LSB side, it becomes "00000010" and becomes "2" in a decimal number. Therefore, this reciprocal is “0.5” in decimal. On the other hand, when the reciprocal of the quantization table value “11” (decimal) is bit-shifted by the scale factor “−2”, the reciprocal of “11” is “1/11”, so that the binary number is “0.00”.
010111010001 ", which is shifted to the MSB side by 2 bits to be" 0.010111010001 ", which is" 0.3636 "in decimal.
… ”, With incorrect results. Therefore, in this embodiment, the quantization table 1 and the reciprocal table 22 are separately provided.

Also, the rounding circuit 4 rounds the quantized threshold data in a positive / negative symmetric manner, so that when the output of the multiplier 3 is positive, 1 /
2LSB is added and rounded down, and when negative, 1 / 2LSB is subtracted and rounded up. In the case of a positive value, “0... 0.10” may be added, and then the fractional part may be ignored. In the case of a negative value, “1... 1.10” is added in two's complement notation. However, if there is at least one bit “1” in all bits below the decimal point, 1 LSB may be added. When "0.11" is added, it becomes "0 ... 0.01" (= "1-1.10" + "0 ... 0.11"), and after adding "0 ... 0.01", the fractional part may be ignored. FIG. 4 shows an example in which all 5-bit data of 2 bits after the decimal point are rounded off to the right and negative symmetrically.

In the configuration of FIG. 3, in order to round the quantized data of 16 bits (the lower 5 bits are data after the decimal point) output from the multiplier 3 to the upper 11 bits after the decimal point, the quantized data is If the value is negative, the fixed data “10
000 "is inverted, and the adder 31 adds the inverted data" 01111 "to the 5 bits after the decimal point of the quantized data. If the quantized data is positive, the fixed data" 10000 "is quantized as it is. The data after the decimal point is added to 5 bits after the decimal point, each decimal point is rounded down, and only the upper 11 bits are output.When the quantized data is positive, the result of the addition in the adder 31 is: When an overflow occurs, the MSB becomes “1” and the value after addition becomes negative, so the sign bit check circuit 33 compares the sign bit before addition with the sign bit after addition, and determines that the sign bit is positive. When it changes to a negative value, the switching signal SW2 is output and the switching circuit 32
To output a positive maximum value “011... 1”.

〔The invention's effect〕

According to the present invention, the quantization table and the reciprocal table are separately provided, and the threshold data is set according to the scale factor.
When shifting to the LSB side, the reciprocal is calculated after bit shifting, so that correct quantization processing can be performed.When the threshold data is shifted to the MSB side by the scale factor, the reciprocal is calculated. After the bit shift, the number of input bits of the reciprocal table can be reduced, and the memory capacity of the reciprocal table can be reduced.

In the rounding process after quantization, when data to be rounded is negative, a bit pattern of “01... 1” is added to the lower n bits, and when positive, a bit pattern of “10. Since each addition is rounded down, it can be rounded symmetrically.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a quantization circuit according to the present invention, FIG. 2 is a block diagram of a bit shift circuit in FIG. 1, FIG. 3 is a block diagram of a rounding circuit in FIG. Fig. 5 is a table showing an example of a rounding process. Fig. 5 is a schematic diagram showing a processing procedure of a baseline system. Fig. 6 is a table showing an example of a quantization matrix. Fig. 7 is a table showing an example of a zigzag scan. FIG. 8 is a schematic diagram showing a processing procedure of the rounding processing. 1 ... quantization table, 2 ... bit shift circuit, 3 ...
... Multiplier, 4 ... Rounding circuit, 20,23 ... Barrel shifter, 2
2 ... Reciprocal table, 31 ... Adder.

──────────────────────────────────────────────────の Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 7/50 H03M 7/30

Claims (2)

(57) [Claims] 1. A quantization table in which a quantization table value for quantizing input data at a predetermined quantization step width is stored, and the quantization table value is determined by a scale factor value.
A first barrel shifter for bit shifting to the LSB side, a reciprocal table for outputting the quantization table value or the reciprocal of the output of the first barrel shifter, and an output of the reciprocal table according to the scale factor value. A second barrel shifter for bit-shifting the input data; a multiplier for multiplying the input data by an output of the reciprocal table or an output of the second barrel shifter to quantize the input data; A rounding circuit for performing a rounding process. When the value of the scale factor is negative, the quantization table value is bit-shifted to the LSB side by the first barrel shifter, and then converted to the reciprocal by the reciprocal table. Is positive, the quantization table value is converted to the reciprocal by the reciprocal table, and then the second Bits shifted into the LSB side Rushifuta each quantization circuit, characterized in that the input to the multiplier. 2. The rounding circuit adds an n-bit pattern of "01... 1" to lower n bits when an output of the multiplier is negative, and adds "10" when an output of the multiplier is positive.
.. 0 "are added, and the lower n
2. The quantization circuit according to claim 1, wherein the bits are rounded off symmetrically by truncating the bits.