JP2993072B2 - Shift register circuit - Google Patents

Abstract

PURPOSE:To shorten time for transfer and to prevent the time from being overlapped between adjacent bit output signals by forming a bit part by a transfer gate, the inverse parallel circuit of an inverter and a clocked inverter, and a NOR circuit, etc. CONSTITUTION:A shift register circuit 1A is composed of first and second bit parts A1 and A2 which are serially connected with similar circuit configuration while inverting the phase of a clock signal. An input signal SIN is inputted through a transfer gate TG of the bit part A1 to the inverse parallel circuit of an inverter INV and a clocked inverter CINV, and a latch signal SL is outputted. While inputting the signals SIN and SL, a NOR circuit NR outputs a bit output signal SO1. A NOR gate NR is provided for an output to an output terminal. Similarly, a shift output SO2 is outputted from the similar second bit part A2 in the next step at high transfer speed in the case of an inverted clock without overlapping bit output signals.

Description

Description: TECHNICAL FIELD The present invention relates to a shift register circuit.

[Conventional technology]

2. Description of the Related Art Shift register circuits are often used in video signal sample and hold circuits and the like.

FIG. 5 is a circuit diagram of an example of a conventional shift register circuit.

The shift register circuit 1C cascade-connects bit units C1 and C2 having the same configuration.

The bit part C1 has one end of the transfer gate TG connected to the input terminal IN, the other end connected to the input terminal of the inverter INV and the output terminal of the clock inverter CINV, and
A latch section La in which the output terminal of V and the input terminal of the clocked inverter CINV are connected to the output terminal H1, and a synchronization signal input to the transfer gate TG and the clocked inverter CINV with the same circuit configuration as the latch section La. , and a latch unit Lb which receives a synchronizing signal having the opposite phase and φ as an input is cascaded.

Each bit section C1, C2 outputs a bit output signal SO1, SO2.

The synchronous signal Φ and the input signal SI are supplied to the shift register circuit 1C in which the bit units C1 and C2 having such a circuit configuration are cascaded via the node M at the timing shown in FIG.
Give N.

First, the operation of the bit section C1 of the shift register circuit 1C will be described.

From time t0 to t1, TG is off and the input signal SIN
Is not input to the inverter INV.

From time t1 to t2, the TG of the latch section La is turned on, the “H” level of SIN is input to the inverter INV, and the “L” level of the output signal SH1 is output to the output terminal H1.

From time point t2 to time point t3, the TG of the latch section La is turned off and the inverter CINV is turned on, so that the “L” level of SH1 is held.

Since the TG of the latch unit Lb is turned on, the "L" level of SH1 is input to the inverter INV, and the first bit output signal SO1 = "H" is output to the bit output terminal OUT1.

From the time point t3 to the time point t4, the TG of the latch section La turns on, and SIN =
“L” is input to the inverter INV of the latch section La, and the output signal SH1 = “H” is output.

Also, since the TG of the latch section Lb turns off and CINV turns on
SO1 = "H" is held.

From time t4 to time t7, the TG of the latch section La is turned off, and CINV
Is turned on, SH1 = "H" is held.

Further, since the TG of the latch circuit section Lb is turned on, SH1 = "H" is input to the inverter INV of the latch section Lb, and SO1 = "L" is output.

Thus, the input signal SIN = "H" from the time point t0 to the time point t2 is shifted from the time point t2 to the time point t4 and output as the output signal SO1 = "H" of the bit part C1.

The bit portion C2 of the shift register circuit 1C operates in the same manner as the bit portion C1, and the bit output signal SO2 = "H" from time t4 to t8.
Is output.

As described above, the bit portion of the conventional shift register circuit shifts to the upper bit portion of the data for each cycle of the synchronization signal φ.

[Problems to be solved by the invention]

In the above-described conventional shift register circuit, data is transferred to the higher-order bit portion in one cycle of the synchronization signal φ.
The transfer of one pulse of data requires a period of one cycle of the synchronizing signal φ, which is a disadvantage.

Further, since the bit output signal of the shift register changes from “H” to “L” and from “L” to “H”, the time from t4 to t6 and from t4 to t5 in FIG. There is a time (from the time point t4 to the time point t5) at which the bit output signal at the same time becomes an intermediate value between “H” and “L”.

FIG. 7 shows that FE is connected to each bit output terminal of the shift register circuit 1C.
A sample and hold circuit having a configuration in which a gate of a T switch F, a source thereof is connected to a video signal input terminal VIN, and a drain is connected to a hold capacitor C is shown.

F at each bit output signal SO1, SO2 of the shift register circuit 1C
When the ET switch F is turned on and off and the FET switch F is on, the voltage of the video signal SV
Is held.

Here, when the output signals of the adjacent bit units C1 and C2 simultaneously have SO1 and SO2 at an intermediate value between “H” and “L”, both of the adjacent FET switches F are turned on, and the drains of the FET switches are turned on. Since the transfer of charges occurs between the hold capacitors C connected to the video signal, the video input signal SV is not properly held in the hold capacitor C.

For example, when a sample-and-hold circuit is realized by a high-voltage CMOS process, the difference between the input voltage of the sample-and-hold circuit and the voltage after sample-and-hold is several tens mV to several hundred mV.
Had become.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a shift register circuit in which the data transfer time is short and there is no overlap time between adjacent bit output signals.

[Means for solving the problem]

In the shift register circuit according to the present invention, the input signal is input to one end of a transfer gate, and the other end is connected to the input terminal of the inverter of an anti-parallel circuit of an inverter and a clocked inverter to output a latch signal. A first latch unit having a latch unit and a NOR gate having one input terminal receiving the input signal and the other input terminal receiving the latch signal and outputting a NOR signal as a bit output signal to a first bit output terminal; A bit portion, an input terminal of which receives the bit output signal, has the same circuit configuration as the first latch portion, and supplies a clock signal supplied to a transfer gate and a clocked inverter to the first latch portion. A second latch unit having an opposite phase relationship with the second latch unit, a NOR gate corresponding to the NOR gate, and a second bit output terminal corresponding to the first bit output terminal. It is configured to include a bit portion, having.

In the shift register circuit according to the present invention, the input signal is input to one end of the transfer gate and the other end is connected to the input terminal of the inverter of the anti-parallel circuit of the inverter and the clocked inverter to output a latch signal. And a NAND gate having one input terminal receiving the input signal and the other input terminal receiving the latch signal and outputting a NAND signal as a bit output signal to a first bit output terminal. 1 bit portion, the input end of which receives the bit output signal, and a clock signal supplied to a transfer gate and a clocked inverter having the same circuit configuration as the first latch portion corresponds to the first latch portion And a second latch unit having an opposite phase relationship, a NAND gate corresponding to the NAND gate, and a second bit output terminal corresponding to the first bit output terminal. Having a bit portion.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The shift register circuit 1A has the same circuit configuration and is configured by serially connecting first and second bit units A1 and A2 whose clock signals are in opposite phases.

The first bit portion A1 is configured such that the input signal SIN is input to one end of the transfer gate TG and the other end is connected to the inverter INV of the anti-parallel circuit of the inverter INV and the clocked inverter CINV.
A first latch unit L1 connected to the input terminal of V to output a latch signal SL, and one input terminal receives the input signal SIN and the other input terminal receives the latch signal SL to output a NOR signal to a bit output signal NOR gate that outputs SO1 to the first bit output terminal
NR.

The second bit unit A2 has the same circuit configuration as the first bit unit A1, and the synchronization signal φ input to the transfer gate TG and the clocked inverter CINV has a phase opposite to that of the first bit unit A1. A synchronization signal, φ, is input.

First and second bit sections of this shift register circuit 1A
A1 and A2 are supplied with the synchronizing signal φ and the input signal SIN at timings as shown in FIG.

From time t0 to t1, the TG of the bit unit A1 is turned on, the “H” level of the input signal SIN is input to the bit unit A1, and the “L” level is input to the NOR gate NR via the inverter INV.

SIN = “H” is input to the other input terminal of the NOR gate NR, and the bit output signal SO1 = “L” of NR is output.

 At this time, the TG of the second bit portion A2 is off.

From time t1 to t2, the TG of the bit section A1 is turned off and the clocked inverter CINV is turned on, so that the output of INV is kept at "L" and "L" is inputted to NR.

SIN is input to the other input terminal of NR, but SIN =
Since it is not "L", the NR output signal SO1 = "L" is output.

At this time, since the TG of the bit section A2 is turned on, the signal SO1 =
“L” is input to NR as “H” via INV.

Since SO1 = "L" is input to the other input terminal of NR, an NR output signal SO2 = "L" is output.

From time t2 to time t3, the input signal SIN becomes "L", so that the two input signals SIN and SL of the NR of the bit portion A1 both become "L", and the NR output signal SO1 = "H" is output. .

At this time, since TG of the shift register circuit A2 is on, SO1 = "H" is input to NR through INV and "L" is input.

Since SO1 = "H" is input to the other input of NR, NR
Output signal SO2 = “L”.

From the time point t3 to the time point t4, the TG of the bit unit A1 is turned on, and the input signal SIN = “L” is input to the NR via the INV to “H”.

Therefore, the output signal SO1 of the NR starts to change from “H” to “L”.

At this time, since the first bit output signal SO1 is input to the NR input terminal of the second bit portion A2, the NR output signal SO1
= “L” is output.

At time t4 to t5, the signal SO1 becomes “L”, and the TG of the bit portion A2 is turned on and CINV is turned on.
, The state “L” is held, “L” is input to both input terminals of the NR, and the NR output signal SO2 = “H” is output.

As described above, the input signal SIN is shifted to a higher-order jitter portion in a half cycle of the synchronization signal φ.

Since the output is started after one lower output signal level becomes "L", the outputs of the adjacent bit portions do not simultaneously take the intermediate value between "H" and "L".

 FIG. 3 is a circuit diagram of a second embodiment of the present invention.

The difference from the first embodiment in the circuit configuration is that the NOR gate NR is used in the first embodiment, but the NAND gate NA is used in the present embodiment.

A synchronous signal φ is applied to a circuit in which the bit units B1 and B2 having such a circuit configuration are connected in series at the timing shown in FIG.
And the input signal SIN.

From the time point t0 to t1, the TG of the bit section B1 turns on, the input signal SIN = "L" is input to INV, and the NAND gate NA receives INV.
Output “H” is input.

Since SIN = "L" is input to the other input terminal of NA, N
The A output signal SO1 = "H" is output.

 At this time, the TG of the bit section B2 is off.

From time t1 to t2, the TG of the bit section B1 is turned off and CINV is turned on, so that the output of INV is kept “H” and NA is “H”.
Is entered.

SIN is input to the other input terminal of NA, but SIN =
Since it is not "H", the NA output signal SO1 = "H" is output.

At this time, since the TG of the second bit portion B2 is turned on, the signal SO
1 = “H” is input to NA via INV as “L”.

Since SO1 = "H" is input to the other input terminal of NA, the NA output signal SO2 = "H" is output.

Since the input signal SIN becomes “H” from time t2 to t3,
Both the two input signals of NA of bit part B1 become “H”.
The NA output signal SO1 = "L" is output.

At this time, since the TG of the bit section B2 is on, SO1 =
“L” is input to NA via INV and “H” is input to NA.

Since SO1 = "L" is input to the other input of NA, NR
Output signal SO2 = "H" is output.

From time t3 to t4, the TG of the bit section B1 turns on, the input signal SIN = “H” is input to the NA via INV, and “L” is input to the NA, and SIN = “H” is input to the other input terminal of the NA. Is entered.

Therefore, the NA output signal SO1 starts to change from “L” to “H”.

At this time, the signals SO1 and C are input to the NA input terminals of the bit section B2.
Since the output “H” of INV held by INV is input, the NA output signal SO2 = “H” is output.

Since the signal SO1 becomes “H” from the time point t4 to t5, “H” is input to both of the input terminals of the NA of the bit portion B2,
Output signal SO2 = “L”.

As described above, the second embodiment has the same effect as the first embodiment, but both the input signal and the output signal have the second effect.
There is an opposite phase relationship between this embodiment and the first embodiment.

Accordingly, when the FET switch F is N-channel ("H" is turned on) in FIG.
When it is a P channel (ON at "L"), it can correspond to the second embodiment.

〔The invention's effect〕

As described above, according to the present invention, only one latch section is used for the bit section of the shift register circuit, so that the output signal of the bit section can be obtained in a half cycle of the synchronization signal.

Furthermore, by inputting the input and output of the latch unit to the logic gate, adjacent outputs do not simultaneously have an intermediate value between “H” and “L”.

As a result, when used in the shift register circuit and the sample and hold circuit, the video input signal can be properly held.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG.
3 is a circuit diagram of the second embodiment for explaining the operation of the circuit shown in FIG. 3, FIG. 3 is a circuit diagram of the second embodiment, and FIG. 4 is a timing diagram of each part signal for explaining the operation of the circuit of FIG. ,
FIG. 5 is a circuit diagram of an example of a conventional shift register circuit, FIG. 6 is a timing chart of signals of respective parts for explaining the operation of the circuit of FIG. 5, and FIG. 7 is a bit output signal of the shift register circuit. FIG. 3 is a circuit diagram of a sample-and-hold circuit that determines sampling timing. 1A-1B shift register circuit, A1, B1 first bit section, A2, B2 second bit section, L1, L2 first and second latch section, TG transfer gate , INV: Inverter, CINV: Clocked inverter, NR: NOR gate, NA: NAND gate, IN, VIN: Input terminals, OUT1 to OU
T2: first and second bit output terminals, φ, synchronization signal, SIN input signal, SO1 to SO2 bit output signals.

Claims (2)

(57) [Claims] (A) An input signal is input to one end of a transfer gate and the other end is connected to an input terminal of the inverter of an anti-parallel circuit of an inverter and a clocked inverter to output a latch signal. A first latch unit having a latch unit and a NOR gate having one input terminal receiving the input signal and the other input terminal receiving the latch signal and outputting a NOR signal as a bit output signal to a first bit output terminal; (B) an input terminal receives the bit output signal, and
A second latch unit having the same circuit configuration as that of the latch unit, and having a clock signal supplied to the transfer gate and the clocked inverter in an opposite-phase relationship corresponding to the first latch unit; A bit portion having a NOR gate corresponding to the NOR gate and a second bit output terminal corresponding to the first bit output terminal. 2. A first input signal is input to one end of a transfer gate and the other end is connected to an input terminal of the inverter in an anti-parallel circuit of an inverter and a clocked inverter to output a latch signal. A first latch unit having a latch unit and a NAND gate having one input terminal receiving the input signal and the other input terminal receiving the latch signal and outputting a NAND signal as a bit output signal to a first bit output terminal; (B) an input terminal receives the bit output signal, and
A second latch unit having the same circuit configuration as that of the first latch unit and having a phase relationship opposite to that of the clock signal supplied to the transfer gate and the clocked inverter and corresponding to the first latch unit; A bit portion having a corresponding NAND gate and a second bit output corresponding to the first bit output.