JP2993166B2 - Synchronization failure detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for detecting a synchronization failure of a digital multiplex transmission line in a digital line device.

In recent years, the introduction of ISDN (Integrated Services Digital Communication Network) has been rapidly progressing, and switching devices installed in homes, such as private branch exchanges, as well as central office exchanges, for example.
BX) and the like also accommodate digital multiplex lines.

In digital communication, in order to process digitally multiplexed data, it is a major premise that synchronization of digital signals is accurate. For this reason, various communication devices involved in digital communication monitor synchronization, respectively.
In many cases, a synchronization failure is detected in a digital line device called a trunk circuit for use. If the device monitoring the synchronization detects a synchronization failure, it sends an AIS (Alarm Indicate S) to the partner device of the digital line.
ignal) signal.

There are various methods for detecting a synchronization failure. In a synchronization failure detection circuit of an exchange, when a digital multiplex transmission line is normal, a logic level "0" occupying all bits of one frame is used. Paying attention to the fact that the bit ratio does not fall below a certain value, for example, by counting the number of “0” bits in one frame of the primary group interface, 1
When the number of “0” bits in a frame is equal to or less than a predetermined number, a method of determining that synchronization is poor is often used.

However, as is well known, the primary group interface has two types (hereinafter, referred to as 1.5M Mbps (hereinafter, referred to as 1.5M)) and 2.048Mbps (hereinafter, referred to as 2M). (Representing a sequence as a digital multiplex transmission line having a different transmission speed), it was necessary to separately design and manufacture two types of circuits suitable for the synchronization failure detection circuit.

Further, since the determination of the synchronization failure is made based on the number of "0" bits in one frame as described above, the state in which the number of "0" bits is small even though the synchronization is normal at some occasion. Occurs, an erroneous determination of "synchronization failure" is made, and an AIS signal may be transmitted.

For this reason, there is a need for a synchronization failure detection circuit that can be shared by the 1.5M system and the 2M system and that has few false detections.

[0008]

2. Description of the Related Art FIG. 3 is a circuit block diagram of a prior art synchronization failure detection circuit, showing an example of a 2M-system synchronization failure detection circuit.

In FIG. 1, a framer section is a circuit for identifying a frame, and is composed of counters 21a and 21b. Each of the counters 21a and 21b counts with a basic clock synchronized with the data bits of the digital multiplex line to be monitored, that is, a clock of 2.048 Mbps. This basic clock is used when an abnormality occurs in the digital multiplex line. Is supplied by a clock source (not shown) by self-running.

Since the 4-bit counter 21a is always operable, it counts the basic clock and counts it as a decimal number (hereinafter, a decimal number unless otherwise specified).
When counting up to 2, it returns to 0, but during the return to 0 after counting 32, the carry-out terminal CO outputs “1” (hereinafter, the high level of the logic level is described as “1” and the low level is described as “0”). Is output. The 4-bit counter 21b is the counter 21
When "1" is input from CO of a, operation becomes possible (enable) and counting is performed. However, since "1" is output to CO only when the counter 21a has counted 32,
It counts up every 32 bits of the basic clock. As a result, the two counters 21a and 21b count up to 256, and when 256 is counted, "1" is output from the CO of the counter 21b. That is, an output is sent from the CO of the counter 21b for each frame of the digital multiplex line of 2.048 Mbps. Hereinafter, the output from the CO of the counter 21b is referred to as a frame pulse.

The frame pulse is supplied to an inverter INV21.
Is input to the load terminal L of the counter 22 of the N-ary counter unit. However, since the level is inverted again at the L input unit, the counter 22 is loaded with an initial value when a frame pulse is output. It will be. When the first frame pulse is input to the L of the counter 22, the counter 22 is output from the sets the initial value output terminal Q ₀ to Q ₃ which is set to an initial value input terminal D ₀ to D _3, D
₀ because to D ₃ are connected all earthed (L level), the initial value "0" is output from the output terminal Q ₀ to Q _3.

Next, the counter 22 counts the basic clock. At this time, since the data of the digital multiplex line is inputted to the enable terminal E ₀ with the logical level inverted, the data is “0” (E ₀ Is incremented only when is "1"). The N-ary counter unit is a circuit for determining that the digital multiplex line is normal for the frame if the number of "0" bits in the data of one frame of the digital multiplex line is equal to or less than a fixed number n. N = 3 for convenience. Therefore, if the counter 22 counts 3, the frame is normal.

According to the above premise, if the first frame (first frame) is normal, the count value of the “0” bit in the data reaches 3 in one frame, and the output terminal Q _{1 of the} counter 22 As a result, "1" is output. This output is INV23
, The logic level is inverted, becomes “0” and the counter
It is input to the 22 E ₁ terminal, and stops the count in counter 22. Furthermore, is also input to the D _0, which is one of input data terminals of the M-ary counter part of the counter 23 at the same time. Counter 23
The clock terminal CK but the frame pulse is supplied from the framer unit and the output to the output terminal Q ₀ to Q ₃ for frame pulse is input at this time is not transmitted.

When the input of the data of the first frame is completed,
Since the second frame pulse is input to CK of the counter 23, the above-mentioned “0” input to D ₀ is output from Q ₀ and input to the NAND 21 and the input data terminal D ₁ of the counter 23. At this point, data of the second frame starts to be input. If the second frame is also normal, “0” is input to D ₀ of the counter 23 again. When the second frame is completed and the third frame pulse is input, “0” of the first frame is input to D ₁ and “0” of the second frame is input to D ₀ . “0” for Q ₀ and Q ₁
Is output.

[0015] Hereinafter, the respective frames in the same manner is completed the input of the normal four-frame, when the 5-th frame pulse has been input, and output are both "0" from the Q ₀ to Q ₃ of the counter 23 . Therefore, the output of the NAND 21 at this time is “1”, but the output of the NAND 21 is 4
If at least one of the frames has a normal frame, it becomes "1". If "1" is input for all four frames, that is, "0" only when the data bits are abnormal for four consecutive frames. ".

The M-ary counter section provides an AI for notifying the detection of a synchronization failure when m frames of abnormal data continue for m frames.
3 is a circuit for outputting an S signal.
= 4 is shown.

The output of the NAND 21 is input to a set terminal S of a set / reset type flip-flop (hereinafter referred to as FF) 24. Since the S terminal has a logic level inverting circuit at its input, "0" is output. Output terminal Q when input
"1" is sent out, and "0" is output when "1" is input.
Is sent. Therefore, if the data bit is abnormal for four consecutive frames, “0” is input from the NAND 21 and the FF
"1" from Q of 24, that is, AI that notifies detection of synchronization failure
An S signal is output.

The frame having abnormal data ends, and
When a frame is input, the input of the first normal frame is
At the end of the operation, the output of the NAND 21 becomes "1",
From the time point, "0" is input to S of the FF24. Meanwhile, Coun
Q23 of TA23₀~ QN_ThreeQ ₀~ Q_ThreeThe inverse logic level of
Output is sent out and input to NAND 22, but data error
Normal frames are being detected and normal frames are continuous for 4 frames
QN until detected₀~ QN_ThreeAre all "1"
The output of NAND22 will be the first abnormal frame.
Frames have been detected for four consecutive frames
It remains at "1" until it is subsequently detected. That is, the FF24
During this time, “0” is input to the set terminal R. this
Therefore, when the input of the first normal frame ends, NA
Even if the output of ND21 becomes "1", FF24 is reset.
And the normal frame is detected four consecutive frames
Reset, and the AIS signal stops.

As described above, in the circuit of FIG. 3, whether the number of “0” bits included in the data is n or more determines whether the data is normal or abnormal on a frame basis, and the abnormal frame is continuous for m frames. The AIS signal is transmitted when the signal is transmitted.
The number of bits in one frame changes depending on whether the system is the M system or the 2M system, and different values of n and m may be used due to differences in the number of bits and the frame configuration.

Since the framer shown in FIG. 3 is an example of a 2M system, the count value for transmitting a frame pulse is 256. In the 1.5M system, this count value is 19, for example.
Need to change to 3. Further, in FIG. 3, numerical values for explanation are used for n and m, but since a circuit is configured in accordance with given values of n and m, 1.5
When the values of n and m are different between the M system and the 2M system, it is necessary to adopt a circuit configuration suitable for each. That is, 1.5M
It is necessary to design different synchronization failure detection circuits for the system and the 2M system.

[0021]

A prior art synchronization failure detecting circuit for detecting a synchronization failure by monitoring the bit configuration of a digital signal on a digital multiplex line has a transmission speed of 1.5 M system. And the 2M system must have different configurations, and the synchronization failure is determined only by the bit configuration of the digital signal. Therefore, when a digital signal having a unique bit configuration is transmitted, the synchronization is not abnormal. In some cases, synchronization failure is erroneously detected.

An object of the present invention is to provide a synchronization failure detecting circuit which can be shared by digital multiplex lines having different transmission speeds and which has few detection errors.

[0023]

FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, reference numeral 1 denotes a basic clock synchronized with data bits of a digital multiplex line to be monitored, and outputs a frame identification signal when the same number as the number of bits constituting one frame of the digital multiplex line is counted. The frame identification signal generating means 2 receives the frame identification signal from the frame identification signal generating means 1 and the digital signal from the digital multiplex line, and determines the number of bits of the logical level "0" contained in the bits of the digital signal of one frame. An abnormal frame detecting means for outputting an abnormal frame detection signal when detecting that the number of bits is equal to or less than a numerical value (n) determined by the transmission speed of the digital multiplex line; 1, an abnormal frame detection signal from the abnormal frame detecting means 2 is input. The number of frames to which a frame detection signal is input is counted, and when it is detected that the abnormal frame detection signal has been input continuously for a fixed number of frames (m) determined by the transmission speed of the digital multiplex line, synchronization abnormality detection is performed. This is an abnormal frame number counting unit that outputs a signal.

Reference numeral 4 denotes an input of the synchronization abnormality detection signal from the abnormal frame number counting means 3 and synchronization monitoring information of the digital multiplexing circuit from the transmission device, and information indicating that the synchronization monitoring information has detected synchronization. Synchronization failure determination means for outputting a synchronization failure detection signal when the synchronization failure detection signal is input when the transmission is not being transmitted; and 5; a transmission rate identification signal for identifying a transmission rate of the digital multiplex line; Bit number information for identifying a frame with respect to the frame identification signal creating means 1; the numerical value (n) for detecting a frame abnormality with respect to the abnormal frame detecting means 2; Means for setting the frame numerical value (m) for detecting a synchronization error.

[0025]

In FIG. 1, a frame identification signal generating means 1 counts a basic clock synchronized with a data bit of a digital multiplex line (not shown) to be monitored, and sets the number of bits set in a synchronization failure detection condition setting means 5. Output a frame identification signal when is counted. The number of bits is set to the same value as the number of bits in one frame of the digital multiplex line by inputting a transmission speed identification signal for identifying the transmission speed of the digital multiplex line by the synchronization failure detection condition setting means 5. The signal generator 1 outputs a frame identification signal for each frame of the digital multiplex line.

The abnormal frame detecting means 2 inputs the frame identifying signal from the frame identifying signal creating means (1) and the digital signal from the digital multiplex line, and outputs the logical level "0" contained in the bit of the digital signal of one frame. The number of bits is counted, and it is checked whether or not the number of bits is equal to or less than a numerical value n determined by the transmission speed of the digital multiplex line. When the number of bits is detected to be n or less, an abnormal frame detection signal is output. The numerical value n is set in advance to a value determined as an abnormal frame detection condition in the digital multiplex line of the transmission speed by the poor synchronization detection condition setting means 5 to which the transmission speed identification signal of the digital multiplex line to be monitored is inputted. The abnormal frame detecting means 2 uses this numerical value n to determine whether or not the number of “0” bits in the data bits in one frame is equal to or greater than n.

When the abnormal frame detection signal is output from the abnormal frame detecting means 2, the abnormal frame number counting means 3 inputs the abnormal frame detecting signal, and receives the abnormal frame detecting signal based on the frame identifying signal input from the frame identifying signal generating means 1. The number of frames to be counted is counted. As a result, when it is detected that the abnormal frame detection signal has been input for m consecutive frames, a synchronization abnormality detection signal is output. The numerical value m
The synchronization failure detection condition setting means 5 to which the transmission rate identification signal of the digital multiplex line to be monitored is inputted, sets a numerical value defined as the synchronization failure detection condition in the digital multiplex line of the transmission speed, and sets an abnormal frame. The number counting means 3 uses this numerical value m to check whether or not the abnormal frame continues for m frames.

The abnormal synchronization detection signal output when the abnormal frame number counting means 3 detects that the abnormal frame continues for m frames is input to the poor synchronization judging means 4.
Synchronization monitoring is performed at each stage of the digital communication device. The synchronization failure determination means 4 inputs synchronization monitoring information of the corresponding digital multiplex line from another digital communication device such as a transmission device (not shown). When the synchronization abnormality detection signal is input while displaying that synchronization is being performed, the synchronization failure detection signal is not output, and when the synchronization monitoring information indicates that synchronization is not synchronized, synchronization abnormality detection is performed. The synchronization failure detection signal is output only when a signal is input. Thereby, for example, both the transmission device and the digital line device provided with the synchronization failure detection circuit of the present invention output the synchronization failure detection signal only when the synchronization failure is detected,
Synchronization failure is more reliably detected.

As described above, the synchronization failure detection circuit according to the present invention provides a transmission speed or a value used as a synchronization failure detection condition, for example, the number n of "0" bits in one frame of data bits or an abnormal frame. It is possible to share a number of consecutive meters for different digital multiplex lines,
When data having a unique number of “0” bits in a frame is transmitted, it is not erroneously detected as synchronization failure.

[0030]

FIG. 2 is a circuit block diagram showing an embodiment of the present invention.
FIG. 1 shows an example of a circuit block diagram of a synchronization failure detection circuit provided in a digital line device (not shown) connected to a 1.5M or 2M digital multiplex line.

In the figure, reference numeral 11 denotes a frame counter constituting a frame identification signal creating unit, 12 denotes an N-ary counter which constitutes an abnormal frame detecting unit, 13 denotes an M-ary counter which constitutes an abnormal frame number counting unit, and 14 denotes a set. Reset type flip-flops, 15 to 17 are components constituting a synchronization failure detection condition setting unit, 15 is a frame counter initial value setting circuit for setting an initial value of the frame counter 11, and 16 is an N-ary counter 12
Sets the count value at which an abnormal frame detection signal is output.
A decimal counter count value setting circuit 17 is a M-ary counter count value setting circuit for setting a count value at which the M-ary counter 13 outputs a synchronization abnormality detection signal. Also, INV1 to INV3 are inverters, NAND1 and NAND2 are NAND circuits,
AND is a logical product (AND) circuit.

The frame counter 11 shown in FIG. 2 is a counter capable of counting the number of bits in one frame of a 1.5M and 2M digital multiplex line. In this case, the frame counter 11 of one frame of a 2M digital multiplex line having a large number of bits is used. The number of bits, that is, 256 bits can be counted. When 256 is counted, CO outputs "1". The frame counter 11 supplies a basic clock synchronized with the data bit of the digital multiplex line to which the digital line device is connected to a clock input terminal C.
K, and the frame identification information synchronized with the data frame of the same digital multiplex line is input to the load terminal L.

When frame identification information is input to L, frame
Is the initial value input terminal D ₀~ D_ThreeEntered in
Data is set as the initial value. Initial input to D
The value is the Q of the frame counter initial value setting circuit 15.₀~ Q_ThreeYo
In this example, the initial value of the frame counter is set.
A signal for selecting 1.5M is input to the G terminal of the
Output “63” and input a signal to select 2M.
When a force is applied, "0" is output.

Therefore, the frame counter 11 has a capacity of 1.5M
In the case of a line, since the initial value "63" is set, a frame pulse output from the CO is sent every time the basic clock is counted 193 bits from "64" to "256".
In the case of the M line, since the initial value “0” is set, a frame pulse is transmitted each time the basic clock is counted from 256 bits from “1” to “256”.

[0035] The frame pulse output from the frame counter 11 is input to the L of the N-ary counter 12, the initial value to the N-ary counter 12 is set, the initial value D ₀ following all the bits in this case Because it is connected to the earth,
It becomes “0”. Because the N-ary counter 12 digital signal from the digital multiplex line are input to the E ₀ through INV1, counts the number after the initial value setting data bit "0", the count value of the N-ary counter count setting circuit 16 is input to the D ₀ following.

As described above, the N-ary counter 12 is a circuit for counting whether or not the number of "0" bits in the data bits of one frame is larger than a certain value n. Alternatively, the number of counting bits is determined such that counting can be performed on the one in which a larger n is specified in a 2M digital multiplex line. Thus, for example, if the maximum value of n is 64, 4-bit counter is used, D ₀ following input terminals of the N-ary counter count setting circuit 16 is constituted by four terminals.

The N-ary counter count value setting circuit 16 uses this D ₀
When the numerical value input to the following input terminal reaches a preset value of n, "1" is output from the Q terminal, but the number of data bits "0" is a fixed number. If n is greater than or equal to n, the frame is determined to be normal, and the frame for which "1" is output from the Q terminal is normal.

The output "1" of the Q is obtained by
Is input stops the counting of the N-ary counter 12 to ₁ is input to the D ₀ of M-ary counter 12, the output terminal Q ₀ of M-ary counter 12 when the next frame pulse from the frame counter 11 is outputted Is output. Output terminal Q ₀
The following output is inputted is one bit shifted below the input terminal D ₁ of the same M-ary counter 12, is shifted each time the same way frame pulse as described in the prior art is input is output from the Q ₀ or less You.

Q of the M-ary counter 12₀The following output is M
D of counter count value setting circuit 17₀Entered below, G
Specified by signals that select 1.5M and 2M input to
Only m m₁~ Q_mConfigured to output more
Have been. This value of m indicates that abnormal frames
For detecting synchronization failure when connected
Therefore, m is one of 1.5M and 2M digital multiplex lines.
Is set according to the larger value. Therefore, NAND
1 and the number of input terminals of NAND2 are also adjusted to the maximum value of m.
The number of times the M-ary counter count value is set
Road 17 Q₁~ Q _mWhen output more, m less than the capacity
Is set, all other terminals output "1".
Try to force.

Q _{1 to} Q of the M-ary counter count value setting circuit 17
_{The m} outputs from m are input to NAND1, but only when all m outputs "1", "0" indicating the detection of synchronization abnormality is output from NAND1. Is output from NAND1, "1" is sent out, and no synchronization abnormality is detected.

"0" output from NAND1 is FF14
And the FF 14 is set, and "1" is output from the output terminal Q as a synchronization abnormality detection signal to the AN of the synchronization failure determination unit.
Output to the D circuit. To another input terminal of the AND circuit of the synchronization failure determination unit, synchronization monitoring information of the corresponding digital multiplex line is input from another digital communication device such as a transmission device (not shown). A synchronization failure detection signal is output only when the synchronization failure detection signal is input when "1" indicating that synchronization has not been detected is input as the synchronization monitoring information. Therefore, both the data communication device such as the transmission device and the synchronization failure detection circuit of FIG. 2 output a synchronization failure detection signal only when the synchronization failure is detected, thereby improving the detection accuracy of the synchronization failure.

The operation of the NAND 2 circuit and the reset terminal R of the FF 14 is basically the same as that described in the prior art, and thus the description is omitted. FIG.
The embodiment of the present invention has been described with reference to FIG. 2. However, FIG. 2 shows only one embodiment of the present invention, and it goes without saying that the present invention is not limited to the circuit of FIG. For example, in FIG. 2, it is assumed that the constant value n counted by the N-ary counter 12 and the number m of continuous frames counted by the M-ary counter 13 are different between the 1.5M line and the 2M line. If there is a circuit capable of taking the same value between the 5M line and the 2M line, one of the N-ary counter count value setting circuit 16 and the M-ary counter count value setting circuit 17 is removed and N
It is clear that the same effect can be obtained even if a fixed value is set in the decimal counter 12 or the M-ary counter 13.

In FIG. 2, the frame identification information synchronized with the data bits of the digital multiplex line is input to the frame counter 11, but the detection of the synchronization failure is detected by 193 bits or 25 bits not synchronized with the data frame.
It is also possible to carry out with 6 bits. In this case, for example, 8 kbp not synchronized with the data bit of the digital multiplex line
Even if a signal of s (corresponding to one frame width) is input, the effect of the present invention can be obtained. Further, it goes without saying that the logic level of each signal shown in FIG. 2 may be different from that shown in FIG. 2 depending on circuit components such as an IC used.

[0044]

As described above, according to the present invention,
Even if the transmission speed of the digital multiplexing line for monitoring the synchronization failure is different and the number of “0” bits in the data bits of one frame used as the synchronization failure detection condition or the number of consecutive abnormal frames is the same, the same It is possible to use a synchronization failure detection circuit, and false detection of synchronization failure is also possible when data having a unique number of "0" bits in one frame is transmitted over a digital multiplex line. There is no. Further, since it can be shared by digital multiplex lines having different transmission speeds, it is easy to implement an LSI.

As described above, the present invention greatly contributes to unification of the synchronization failure detection circuit in the digital line device and improvement of the reliability, and a significant effect is achieved in realizing the downsizing of the synchronization failure detection circuit by adopting the LSI. .

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit block diagram of an embodiment of the present invention.

FIG. 3 is a circuit block diagram of a conventional technology.

[Explanation of symbols]

 1 Frame identification signal creation means 2 Abnormal frame detection means 3 Abnormal frame number counting means 4 Synchronization failure judgment means 5 Synchronization failure detection condition setting means

Claims (1)

(57) [Claims] A synchronization failure detecting circuit for detecting a synchronization failure by monitoring a bit configuration of a digital signal of a digital multiplex line, counting a basic clock synchronized with a data bit of the digital multiplex line to be monitored. A frame identification signal generating means (1) for outputting a frame identification signal when counting the same number as the number of bits constituting one frame of the digital multiplex line; and a frame identification signal from the frame identification signal generating means (1). A digital signal is input from a digital multiplex line, the number of bits of a logic level "0" included in bits of the digital signal of one frame is counted, and the number of bits is determined by a numerical value (n) determined by the transmission speed of the digital multiplex line. ) An abnormal frame detecting means (2) which outputs an abnormal frame detection signal when detecting that: ), A frame identification signal from the frame identification signal creation means (1), an abnormal frame detection signal from the abnormal frame detection means (2), and the number of frames to which the abnormal frame detection signal is input is counted. Abnormal frame number counting means (3) for outputting a synchronous abnormal detection signal when detecting that the abnormal frame detection signal is continuously inputted for a fixed number of frames (m) determined by the transmission speed of the line
The synchronization abnormality detection signal is input from the abnormal frame number counting means (3), the synchronization monitoring information of the digital multiplexing circuit is input from the transmission device, and information indicating that the synchronization monitoring information detects synchronization is transmitted. When the synchronization error detection signal is not input when the synchronization error detection signal is input, a synchronization error determination unit (4) that outputs a synchronization error detection signal, and a transmission rate identification signal that identifies the transmission rate of the digital multiplex line, The frame identification signal creating means (1)
Bit number information for identifying a frame, the numerical value (n) for detecting an abnormal frame with respect to the abnormal frame detecting means (2), and the synchronous information with respect to the abnormal frame number counting means (3). Synchronization failure detection characterized by comprising a synchronization failure detection condition setting means (5) for setting the frame numerical value (m) for detecting an abnormality, wherein synchronization failure of digital multiplex lines having different transmission speeds can be detected. circuit.