JP2993415B2 - Crossbar switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a crossbar switch, and more particularly to a crossbar switch which is a basic element in an ATM exchange.

[0002]

2. Description of the Related Art Asynchronous transfer mode (ATM) exchanges are expected as exchanges for future large-scale communication lines. At each node of the ATM switching system, cells are sorted to their respective destinations according to the information in the header of the inputted cells. This operation is performed by the cross point switch of the node, but a buffer for temporarily saving the cells is required to avoid collision between the cells.

[0003] In the case of ATM, the size of one cell is fixed at 53 bytes.
Since a buffer having a capacity of about 0 cells is prepared, a considerable amount of buffers is required in total. This large amount of buffer is one of the problems of the ATM switching system. The switch portion of the ATM switch is usually composed of semiconductor transistors, but is a relatively small-scale circuit. For example, it is expected that the switch will operate at a clock frequency of 10 GHz or more by using a compound semiconductor or the like. .

However, since the buffer portion has a large capacity, it is difficult to realize it with a compound semiconductor, and a FIFO using CMOS is generally used. For this reason, there is no prospect that the buffer will operate at a clock frequency of 10 GHz or higher. In order to solve this problem, studies have been made to construct a buffer using a delay line because of its simple construction. An example in which an optical fiber with relatively little signal degradation is used as the delay line is disclosed in IEE Journal on Selected.
Areas in Communications, Vol. 6, No. 7, page 1096 (IEEE JOURNAL ON SELECTED AREAS I
N COMMUNICATIONS, VOL. 6, NO. 7, p. 1096, 1988).

FIG. 6 is a schematic circuit diagram showing an example of a conventional crossbar switch using the above optical fiber as a delay line. In the figure, an optical fiber 61 is connected between one input / output terminal of a crossbar switch 62, and this optical fiber 61 is used as a delay line buffer.

[0006]

However, it is difficult to make the optical fiber physically small, and there is a problem that when the above-mentioned large-capacity buffer is constructed, it becomes physically very large. In addition, it is conceivable to integrate a metal strip line on the chip for miniaturization.However, since the resistance of the metal wiring is severely deteriorated, it is difficult to form a large-capacity delay line buffer. is there.

[0007] The present invention has been made in view of the above points,
It is an object of the present invention to provide a crossbar switch having a small configuration and a large capacity buffer function by using a superconducting delay line.

[0008]

Means for Solving the Problems In order to achieve the above object, the present invention provides first and second input terminals and first and second input terminals.
Having an output terminal and a control signal terminal, and a first input terminal or
The cell input to the second input terminal is input to the control signal terminal.
Cross operation or bar operation is performed by the input control signal
Output to the first output terminal or the second output terminal
And a second input terminal and a second output terminal of the crossbar switch body operated by the switch.
And the second of the crossbar switch body
Delay the cell output from the output terminal of
Have a superconducting delay line for input to the second input terminal of the switch body, the crossbar switch body, the first input terminal
The input cell performs bar operation according to the control signal.
Output to the first output terminal when the
Output to the second output terminal when controlled to operate
Then, the cell input to the second input terminal is controlled by the control signal.
1st output when controlled to perform cross operation
Output to the terminal and when the bar is controlled to operate,
2 is configured to output to the output terminal .

[0009]

A superconducting delay line using a Josephson junction and a superconducting line is a crossbar as a serial memory using the high-speed switching characteristics, low power consumption characteristics, and the distortion-free signal transmission characteristics of the superconducting line. A buffer for temporarily saving an input cell input to the switch body can be configured.

The amount of information Cm stored on the superconducting delay line can be expressed as Cm = f · Tc, where f is the transfer rate and Tc is the delay time. When a high-speed switch element is used for the input / output gate, it is possible to increase the transfer rate f to 10 GHz or more, and to realize a lossless long-distance line on a chip by using a superconducting line. Can be.

When the Josephson transmission line is used as a delay line, the running speed of the fluxon introduced into the Josephson transmission line is determined by the bias voltage applied to the voltage terminal (upper electrode) of the Josephson transmission line. Can be controlled by The delay time Tc of the Josephson transmission line can be expressed as Tc = L / α where α is the running speed and L is the distance of the Josephson transmission line. Accordingly, by reducing the traveling speed α, it is possible to increase the delay time Tc, that is, to increase the information amount Cm in the Jossenson transmission lines of the same length.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a schematic circuit diagram of a first embodiment of the present invention. This embodiment has a configuration including a superconducting stripline 1 and a crossbar switch main body 2. The crossbar switch body 2 is a two-input two-output switch having first and second input terminals 3 and 5, first and second output terminals 4 and 6, and a control signal terminal 7. In this configuration, superconducting stripline 1 is connected between output terminal 6 and second input terminal 5.

Next, the operation of this embodiment will be described. When a cell is input to the first input terminal 3, the control signal input to the control signal terminal 7 at the same time determines whether the crossbar switch body 2 performs a cross operation or a bar operation. When the output destination is busy, the control signal controls the crossbar switch main body 2 to perform a cross operation, and the cell input to the first input terminal 3 is transferred from the second output terminal 6 to the superconducting stripline 1. Sent and stored.

The stored cells propagate through the superconducting stripline 1, are delayed for a predetermined time, and are input to the second input terminal 5 of the crossbar switch main body 2. At this time, when the crossbar switch main body 2 is controlled to perform the cross operation by the control signal input from the control signal terminal 7, the signal is output from the first output terminal 4 and is controlled to perform the bar operation. Then, the signal is sent from the second output terminal 6 to the superconducting stripline 1 again.

On the other hand, if the output destination is not busy, the crossbar switch main body 2 is controlled by the control signal so as to perform a bar operation, and the cell input to the first input terminal 3 is the first input terminal 3.
Is output from the output terminal 4.

The crossbar switch body 2 is realized by, for example, a transistor using a compound semiconductor and has a 10 GHz
It can be operated with a high-speed clock of about z. Since the signal loss of the superconducting stripline 1 is very small, the cell information input to the superconducting stripline 1 from the second output terminal 6 is hardly attenuated. Input to terminal 5. Therefore, the crossbar switch body 2 does not need to amplify the signal, or it is very simple.

FIG. 2 shows an image diagram when the crossbar switch of FIG. 1 is mounted. In FIG. 2, a multi-chip module 10 includes a superconducting delay line chip 11 corresponding to the superconducting stripline 1 and a crossbar switch chip 12 corresponding to the crossbar switch body 2.
Are mounted, and the superconducting delay line chip 11 and the crossbar switch chip 12 are connected by a superconducting wiring 13.

The crossbar switch chip 12 has a first input terminal 14 corresponding to the first input terminal 3, a first output terminal 15 corresponding to the first output terminal 4, and a control signal corresponding to the control signal terminal 7. It has a terminal 16. Note that a second input terminal 5 of the crossbar switch chip 12
And the second output terminal corresponding to the second output terminal 6 are connected to the superconducting delay line chip 11 via the superconducting wiring 13 respectively.

Superconducting delay line chip 11 and superconducting wiring 1
3 needs to be operated in a low-temperature environment, so that the entire multi-chip module 10 is mounted in a low-temperature environment. For example, when a high-temperature superconducting material is used as the superconductor, it is mounted on a 50K refrigerator or the like.

The size of the superconducting delay line chip 11 is estimated as follows. 10G clock for input / output gate
Hz, a 50 m delay line can store about 5 kbits of information (pulse propagation speed is 1
× 10 ⁸ m / s). Assuming that the superconducting strip lines are laid out with a width of 1 μm and a pitch of 2 μm, a 5 kbit buffer can be realized with a chip of about 10 mm square.

Next, a second embodiment of the present invention will be described. FIG. 3 shows a schematic circuit diagram of the second embodiment of the present invention. As shown in the figure, this embodiment has a configuration including a Josephson transmission line 21 and a crossbar switch main body 22. The crossbar switch main body 22 has first and second input terminals 23 and 25.
And a two-input, two-output switch having first and second output terminals 24 and 26 and a control signal terminal 27. A Josephson transmission line is provided between the second output terminal 26 and the second input terminal 25. 21 is a connected configuration.

Next, the operation of this embodiment will be described. When a cell is input to the first input terminal 23, the control signal input to the control signal terminal 27 at the same time determines whether the crossbar switch main body 22 performs a cross operation or a bar operation. When the output destination is busy, the control signal controls the crossbar switch main body 22 to perform a cross operation, and the cell input to the first input terminal 23 is transferred from the second output terminal 26 to the Josephson transmission line 21. Sent and stored.

The stored cells propagate through the Josephson transmission line 21, and are input to the second input terminal 25 of the crossbar switch main body 22 after being delayed for a predetermined time. At this time, when the crossbar switch body 22 is controlled to perform the cross operation by the control signal input from the control signal terminal 27, the crossbar switch body 22 is output from the first output terminal 24 and controlled to perform the bar operation. When the signal is transmitted, the signal is transmitted from the second output terminal 26 to the Josephson transmission line 21 again.

On the other hand, if the output destination is not busy, the crossbar switch main body 22 is controlled by the control signal so as to perform a bar operation, and the cell input to the first input terminal 23 is output from the first output terminal 24. Is done.

The crossbar switch body 22 is realized by, for example, a transistor using a compound semiconductor, and
It can be operated with a high-speed clock of about Hz. Since the signal loss of the Josephson transmission line 21 is very small, the cell information input to the Josephson transmission line 21 from the second output terminal 26 is almost not attenuated.
2 to the second input terminal 25. Therefore, the crossbar switch body 22 does not need to amplify the signal, or it is very simple.

The information input to the Josephson transmission line 21 functioning as a delay line is represented as a single flux quantum by the Josephson transmission line 21.
And the propagation speed of the information can be controlled by the voltage applied to the voltage terminal 28. That is,
The Lorentz force generated between the electric field generated by the voltage applied to the voltage terminal 28 and the magnetic field of the single flux quantum becomes the driving force of the single flux quantum.

FIG. 4 is an image diagram when the crossbar switch of FIG. 3 is mounted. In FIG. 4, the multi-chip module 30 includes a superconducting delay line chip 31 corresponding to the Josephson transmission line 21.
And a crossbar switch chip 32 corresponding to the crossbar switch main body 22 are mounted. The superconducting delay line chip 31 and the crossbar switch chip 32 are connected by a superconducting wiring 33.

The crossbar switch chip 32 has a first input terminal 34 corresponding to the first input terminal 23, a first output terminal 35 corresponding to the first output terminal 24, and a control signal corresponding to the control signal terminal 27. It has a terminal 36. A second input terminal corresponding to the second input terminal 25 of the crossbar switch chip 32 and a second output terminal corresponding to the second output terminal 26 are each connected to a superconducting delay via a superconducting wiring 33. It is connected to the line chip 31.

Superconducting delay line chip 31 and superconducting wiring 3
3 needs to be operated in a low-temperature environment, so that the entire multi-chip module 30 is mounted in a low-temperature environment. For example, when a high-temperature superconducting material is used as the superconductor, it is mounted on a 50K refrigerator or the like.

The size of the superconducting delay line chip 31 is estimated as follows. 10G clock for input / output gate
Assuming that the propagation speed of a single flux quantum is 2 × 10 ⁴ m / s, a delay line of 50 m can store about 25 Mbits of information. Assuming that the Josephson transmission lines are laid out with a width of 1 μm and a pitch of 2 μm, a 25 Mbit buffer can be realized with a chip of about 10 mm square.

Next, a third embodiment of the present invention will be described. FIG. 5A is a schematic circuit diagram of a third embodiment of the present invention, and FIG. 5B is an enlarged view of the cross point switch in FIG. As shown in FIG. 2A, this embodiment is based on a configuration in which m × n cross point switches 41 arranged in a two-dimensional matrix of m rows and n columns and m cross switches arranged in a vertical direction. An input terminal group 42 separately connected to each input terminal of the point switch 41 and commonly connected to each input terminal of n cross point switches arranged in the horizontal direction, and m input terminals 42 arranged in the vertical direction. An output terminal group 43 commonly connected to each output terminal of the cross point switch 41 and separately connected to each output terminal of the n cross point switches 41 arranged in the horizontal direction.
It is a configuration consisting of

Each cross point switch 41 is shown in FIG.
As shown in (B), an address filter 51 connected to one corresponding input terminal of the input terminal group 42, a first input terminal connected to an output terminal of the address filter 51, and The output terminal includes a crossbar switch 52 with a delay line buffer connected to a corresponding one of the output terminals 43. The crossbar switch 52 with a delay line buffer is the crossbar switch of the first embodiment or the second embodiment described with reference to FIGS.

Next, the operation of this embodiment will be described. The cells input to the input terminal group 42 are input to the cross point switch 41, where the traveling direction is determined by the address filter 51 in the cross point switch 41 according to the respective header information. When the bus in the traveling direction is busy, the signal is stored in a buffer (superconducting stripline 1 or Josephson transmission line 21) by a crossbar switch 52 with a delay line buffer in crosspoint switch 41. The stored cells are output to the output terminal group 43 as the output destination bus stops being busy.

[0035]

As described above, according to the present invention,
Since a superconducting delay line is provided between the input and output terminals of the crossbar switch body, when a high-speed switch element is used for the input / output gate in the crossbar switch body, the transfer rate can be increased to 10 GHz or more. It is possible to realize a long-distance line with no loss by a superconducting delay line on a chip, so that a small-sized and large-capacity buffer can be realized. In addition, since it is a superconducting delay line, it does not consume power and can be mounted at a high density.

Further, according to the present invention, since the Josephson transmission line is used as the superconducting delay line, the traveling speed of the pulse on the Josephson transmission line can be reduced by the applied voltage, so that the delay time Tc , That is, the information amount Cm can be increased.
A high-speed buffer can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram of a first embodiment of the present invention.

FIG. 2 is a mounting image diagram of the first embodiment of the present invention.

FIG. 3 is a schematic circuit diagram of a second embodiment of the present invention.

FIG. 4 is a mounting image diagram of a second embodiment of the present invention.

FIG. 5 is a schematic circuit diagram of a third embodiment of the present invention.

FIG. 6 is a schematic circuit diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Superconducting stripline 2,22 Crossbar switch body 3,23,14,34 First input terminal 4,24,15,35 First output terminal 5,25 Second input terminal 6,26 Second Output terminals 7, 27, 16, 36 Control signal terminals 10, 30 Multi-chip module 11, 31 Superconducting delay line chip 12, 32 Crossbar switch chip 13, 33 Superconducting wiring 28, 37 Voltage terminal 41 Crosspoint switch 42 Input Terminal group 43 Output terminal group 51 Address filter 52 Crossbar switch with delay line buffer

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 12/28 H01L 39/22 ZAA H04Q 3/52 101

Claims (3)

(57) [Claims] A first input terminal connected to the first input terminal and a second input terminal connected to the first input terminal;
And a control signal terminal, and the first input terminal or
Represents the cell input to the second input terminal and the control signal terminal
Cross operation or bar operation according to the control signal input to the slave
To the first output terminal or the second output terminal
A clock-operated crossbar switch body for outputting, the second input terminal of the crossbar switch body and a
The crossbar is connected between the second output terminal and the second output terminal.
A cell output from the second output terminal of the switch body
The delayed have a superconducting delay line input to the input terminal of the second said crossbar switch body, said crossbar
The switch body includes a cell input to the first input terminal.
Is controlled to perform the bar operation by the control signal.
Output to the first output terminal when the
When it is controlled to operate, it goes to the second output terminal.
And outputting the cell input to the second input terminal to the
Controlled to perform the cross operation by a control signal
Output to the first output terminal when the bar operates
The crossbar switch outputs to the second output terminal when controlled as described above . 2. The crossbar switch body and the superconductor
The delay line is an m × n arranged in a two-dimensional matrix.
(M and n are each an integer of 2 or more) cross points
Switches, and each of the above-mentioned m × n
N of the loss point switches arranged horizontally
N of the above cross point switches respectively
The first input terminal of the crossbar switch body
Is added to the header information of the cell input from the common input terminal.
Therefore, the n address filters that determine the traveling direction
Each of the m crosses connected in the vertical direction
M number of the cross-bars constituting a point switch
The first output terminals of the switch body are commonly connected.
Crossbar switch according to claim 1, wherein the that. Wherein said superconducting delay line, which is connected between the first input terminal and the first output terminal of the crossbar switch body, Josephson propagation speed is controlled by a voltage applied from the voltage terminal The crossbar switch according to claim 1, wherein the crossbar switch is a transmission line.