JP2993431B2 - Hysteresis comparator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a hysteresis comparator, and more particularly, to a hysteresis comparator having a function of varying a hysteresis width.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional hysteresis comparator. The hysteresis comparator shown in FIG. 6 includes a differential circuit including a current source I ₁₀₁ and PNP transistors Q ₁₀₁ and Q ₁₀₂ , and NPN transistors Q ₁₀₃ , Q ₁₀₄ ,
Two current mirror loads composed of Q ₁₀₅ and Q ₁₀₆ are connected. In FIG. 6, () indicates the emitter area ratio of the transistor.

Next, the operation of the conventional hysteresis comparator will be described. Two input terminals 1 of the differential amplifier circuit
The voltage difference between the 02,103, whereas one of the two current mirror load current (current mirror transistor Q ₁₀₃ and Q _104, or current mirror transistors Q ₁₀₅ and Q _106,) flows, is stabilized.

For example, the potential V of one input terminal 103
If the potential V _IN101 the other input terminal 102 than _IN102 is sufficiently low, one transistor Q ₁₀₁ is turned on, the other transistor Q ₁₀₂ turned off, current flows through the transistor Q ₁₀₅ and Q _{10 6} of current mirror load .

The potential V of the other input terminal 102 is
_IN101 is increased, V _IN102 = exceed V _IN101, in (the cut-switched point output state) near the point of FIG. 7, the same current is respectively transistor to the emitter area ratio of the transistor Q ₁₀₅ and Q ₁₀₆ of the current mirror load Q ₁₀₅ , Q
Flows to the collector of _106, the collector current ratio of the transistor Q _101, Q ₁₀₂ becomes equal to the collector current ratio of the transistor Q ₁₀₅ and Q _106.

At this time, the difference V _BE (Q ₁₀₂ −Q ₁₀₁ ) between the base-emitter voltages of the transistors Q ₁₀₁ and Q ₁₀₂ is Becomes However,

(Equation 1) It is. Where K is Boltzmann's constant, q is the amount of charge, T
Is the absolute temperature.

Therefore, the value of the point at which the output state switches is V _IN102 + V _T lnN ₂ .

Conversely, the potential V of one input terminal 103
From when the potential V _IN101 the other input terminal 102 than _IN102 is sufficiently high, the value of the point of switching the state of the output becomes V _IN102 -V _T lnN _1. In the above, ln indicates a natural logarithm.

As described above, in the conventional hysteresis comparator, the hysteresis width (the value of,) is
Since the determined by the emitter area ratio of the transistor Q ₁₀₃ and Q _104, Q ₁₀₅ and Q _106, when assembled an IC on the semiconductor chip, it is impossible to change the hysteresis width.
FIG. 8 shows a hysteresis comparator disclosed in JP-A-4-4606.

The hysteresis comparator shown in FIG.
The first and second input terminals are controlled by controlling the emitter currents of NPN transistors Q ₂₀₁ and Q ₂₀₂ connected to the first and second input terminals 202 and 203 in the form of emitter followers by the transistors Q ₂₀₃ and Q _204. 202, 2
That is, a constant offset voltage (hysteresis width) is generated during the period 03.

However, this hysteresis comparator also reduces the offset voltage (hysteresis width) between the input terminals 202 and 203 by the current ratio (I ₂₀₁ and I ₂₂₁ ) depending on the area ratio between the transistors Q ₂₂₁ and Q ₂₂₃ or the transistors Q ₂₂₂ and Q _224.
Since the current ratio is determined by the current ratio of ₂₀₂ , the hysteresis width cannot be changed when the IC is mounted on a semiconductor chip as in the conventional example shown in FIG.

[0012]

However, the S / N
In the case of a signal having a constant ratio, the input dynamic range cannot be widened and cannot be applied to a light receiving unit of a laser beam printer. In the case of a signal having a constant S / N ratio, if the input level increases, the noise level also increases. Therefore, if the hysteresis width is constant, the noise level exceeds the hysteresis width.
Causes malfunction.

The reason is that, since the hysteresis width is determined by the emitter area ratio of the transistor, the hysteresis width cannot be varied when the semiconductor chip is incorporated in an IC.

An object of the present invention is to provide a hysteresis comparator capable of changing a hysteresis width.

[0015]

In order to achieve the above object, a hysteresis comparator according to the present invention is a hysteresis comparator having a differential circuit, a current mirror load, and offset voltage control means. Has two transistors forming a differential pair, inputs an input signal to the bases of the two transistors, and outputs an output signal proportional to the difference between the collector and the collector. The offset voltage control means is connected between the collectors of the transistors forming the differential circuit and outputs a voltage amplified by a gain, and the offset voltage control means is connected between the emitters of the transistors forming the differential circuit. An offset between two input terminals provided at the base of a transistor comprising a variable resistor and forming the differential circuit; Pressure, at least the emitter
A resistor connected between the resistor and the current mirror load
Based on the preset emitter area ratio of the transistor
Connected between the emitters
The resistance is variable .

The hysteresis comparator according to the present invention
Are the differential circuit, the current mirror load, and the offset.
A hysteresis comparator having voltage control means.
Therefore, the differential circuit is composed of two transistors forming a differential pair.
Input signal to the base of two transistors
Output signal proportional to the difference between the collector and collector.
And the current mirror load is
Connected between the collectors of the transistors forming the driving circuit,
From a set of transistors that output a voltage multiplied by a gain
And the offset voltage control means includes: a second differential circuit;
A current limiter, wherein the second differential circuit comprises a differential pair.
And a resistor, and the differential circuit
The current limiter is connected in parallel to the
Having two transistors in a differential pair, wherein the second difference
The current ratio of the driving circuit is adjusted, and the differential circuit is adjusted.
Two input terminals provided at the base of the transistor
The offset voltage between the differential pair of the current limiter is
The current ratio is adjusted by changing the voltage between the terminals of the transistor.
It is designed to be adjusted and controlled.

[0017]

[0018]

The offset voltage between the two input terminals of the differential circuit is controlled to adjust the hysteresis width. Therefore, the dynamic range of the input signal can be widened.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIG. 1 is a circuit diagram showing a hysteresis comparator according to Embodiment 1 of the present invention.

In FIG. 1, the hysteresis comparator according to the present invention has a differential circuit, a current mirror load, and offset voltage control means as a basic configuration.

In the first embodiment shown in FIG. 1, the offset voltage control means is a variable resistor.

As shown in FIG. 1, the differential circuit has two transistors Q ₁ and Q ₂ forming a differential pair, and a current source I _1a, and inputs the bases of the _two transistors Q ₁ and Q _2. A signal is input, and an output terminal proportional to the difference is output between the collector and the collector. Here, although PNP transistors are used as the transistors Q ₁ and Q ₂ forming a differential pair, NPN transistors may be used.

[0024] Current mirror load is connected between the collectors of the transistors forming a differential circuit, and outputs the amplified voltage to the gain times, the transistors Q _3,
It has Q ₄ , Q ₅ , and Q ₆ . Here, although NPN transistors are used as the transistors Q ₃ , Q ₄ , Q ₅ , and Q ₆ , PNP transistors may be used.

The specific connection relationship will be described.
_1a is connected to the first power supply terminal 1. The base of the PNP transistor Q ₁ is connected to the first input terminal 2, a collector is connected to the collector and base of the collector and the NPN transistor Q ₆ of the NPN transistor Q _3.

The base of the PNP transistor Q ₂ is connected to the second input terminal 3, the collector is connected to the collector and base of the collector and the NPN transistor Q ₄ of NPN transistor Q _5.

The emitters of the NPN transistors Q ₃ , Q ₄ , Q ₅ , Q ₆ forming a current mirror load are:
It is connected to the second power supply terminal 4.

Further emitter of the PNP transistor Q ₁ is connected to a current source I _1a via a resistor R _1a, the emitter of the PNP transistor Q ₂ is connected to a current source I ₁ through the resistor R _2a.

[0029] between the emitters of the PNP transistors Q ₁ and Q ₂ is connected a variable resistor R _3a as an offset voltage control means.

The output terminal 6 is connected to a PNP transistor Q
Is connected to the _first collector, the output terminal 5 is connected to the collector of the PNP transistor Q ₂ of the collector and NPN transistors Q _4, Q _5.

The characteristic of the hysteresis comparator described above, the variable resistor R _3a is placed between two of the PNP transistors Q _1, Q ₂ emitter forming a differential pair, and adjusting the resistance value of the variable resistor R _3a, PNP transistor a voltage drop occurs between the emitter and the current source I ₁ of Q _1, PNP transistor Q ₂
Control the voltage drop that occurs between the current emitter and the current source I ₁ ,
An object is to control an offset voltage between the first and second input terminals 2 and 3 to vary a hysteresis width.

In FIG. 1, () indicates the emitter area ratio of the transistor, and N ₁ , N ₂ > 1
In a relationship.

Next, the operation of the first embodiment of the present invention will be described in detail with reference to FIG. Path (A) is when the input voltage V _{IN1 at} the first input terminal 2 changes from a low voltage value to a high voltage value, and path (B) is when the input voltage V _{IN1 at} the first input terminal 2 is high. This is when changing from a voltage value to a low voltage value.

I) Operation in path (A) In the region where the input voltage V _IN1 is lower than the potential at the point B in FIG.
The NPN transistors Q ₃ and Q ₄ are turned off, and a current flows through the current mirror formed by the NPN transistors Q ₅ and Q ₆ . In this case, NPN transistor Q ₅ is saturated.

The potential of the input voltage V _IN1 rises, and A
The potential near the point, the NPN transistor Q ₅ is rendered active, the ratio of the collector current of the NPN transistor Q ₅ and Q ₆ are, N _2: the 1. Then, they are connected to respective collectors of NPN transistors Q ₅ and Q ₆ . PNP
The collector current ratio of the transistors Q ₁ and Q ₂ is 1: N ₂ .

At this time, the difference V _BE (Q ₂ −Q ₁ ) between the base-emitter voltages of the PNP transistors Q ₁ and Q ₂ is Becomes

Furthermore the voltage difference V _{R1 · R3} between the emitter and the current source I _1a of the PNP transistor Q _1, the voltage difference V _{R2 · R3} between the emitter and the current source I _1a of the PNP transistor Q ₂ is,

(Equation 2) Becomes Here, I ₁ is the current value of the current source I _1a , R ₁ is the resistance value of the resistor R _1a , R ₂ is the resistance value of the resistor R _2a , R ₃ is the resistance value of the variable resistor R _3a , and N ₂ is the transistor Q ₅ is the emitter area ratio of the Q _6. Further, there is a relationship of R = R ₁ = R ₂ .

Therefore, the potential at point A in FIG.

(Equation 3) Becomes ln indicates a natural logarithm.

Then, the potential of the input voltage V _IN1 becomes A
When the point further rises, the NPN transistors Q ₅ and Q ₆
Is turned off, current flows into the NPN transistors Q ₃ and Q ₄ , and the output V _OUT1 changes from a low level to a high level (H).
switch to level).

Ii) Operation in the path (B) In a region where the input voltage V _IN1 is higher than the potential at the point A in FIG.
The NPN transistors Q ₅ and Q ₆ are turned off, and a current flows through the NPN transistors Q ₃ and Q ₄ .

The potential of the input voltage V _IN1 falls, and the potential of the input
The potential near the point, the ratio and the ratio of the PNP transistor Q _1, Q ₂ of the collector current of the NPN transistor Q ₃ and Q ₄ are equal, N _1: a 1. Where N ₁ is N
An emitter area ratio of the PN transistors Q ₃ and Q _4.

At this time, the difference V _BE (Q ₂ −Q ₁ ) between the base-emitter voltages of the PNP transistors Q ₁ and Q ₂ is Becomes ln indicates a natural logarithm.

[0043] Furthermore a voltage difference V _{R2 · R3} between the emitter and the current source emitter voltage difference V _{R1 · R3} and PNP transistor Q ₂ between I _1a and the current source I _1a of the PNP transistor Q ₁ is,

(Equation 4) Becomes

Therefore, the potential at point B in FIG.

(Equation 5) Becomes

Then, the potential of the input voltage V _IN1 is changed to B in FIG.
When it further falls below the point, the NPN transistors Q ₃ and Q ₄
Is turned off, a current flows into the NPN transistors Q ₅ and Q ₆ , and the output voltage V _OUT1 switches from a high (High) level to a low (Low) level.

As described above, from the equations (1) and (2), the hysteresis width (potential at points A and B) is a function of the resistance value R ₃ of the variable resistor R _3a , and the resistance value R ₃ Can be controlled by varying.

As a method of adjusting the resistance value R ₃ of the variable resistor R _3a , a method of equivalently making a variable resistor using a transistor, a terminal is provided between a and b in FIG. Optimal variable resistor R _3a according to the range
There is a way to attach externally.

(Embodiment 2) FIG. 3 is a circuit diagram showing Embodiment 2 of the present invention.

In the second embodiment shown in FIG. 3, the variable resistor R _{3a of the} first embodiment is equivalently realized by using an active element, and controls the voltages of the input terminals 7 and 8. Thus, the hysteresis width can be changed.

The equivalent circuit of the variable resistor R _3a forms a differential circuit with PNP transistors Q ₇ and Q ₈ and resistors R ₄ and R _{5. The} differential circuit is composed of the PNP transistors Q ₁ and Q ₂ and the resistor R _1. ,
PN which is connected in parallel to a differential circuit constituted by R ₂ and forms a differential pair for controlling current values I _a and I _b of the respective differential circuits
It has P transistors Q ₉ and Q ₁₀ .

PNP transistors Q ₉ and Q forming a differential pair
Each input terminal voltage of ₁₀ and V _{con t1,} V _cont2,
When the voltage across its terminals and V _c, the V _c -V _cont1 -V _cont2.

Further, the relational expression between I _a , I _b and V _c is:

(Equation 6) Next, the V _c, it is possible to control the I _a, I _b.

Where R _a = R ₁ = R ₂ , R _b = R ₄ = R ₅ ,
Set the circuit constants such that R _a <R _b, varying the voltage V _c, I _a, the current ratio is changed in the I _b, the transistor Q _{1 0} of the collector potential V _X and the transistor Q ₉ Since the collector potential V _Y changes, the offset voltage (hysteresis width) between the input terminals 2 and 3 can be changed.

According to the second embodiment, the input / output characteristics are as shown in FIG. Figure in A "-A 'between, B'-B" hysteresis width between can be controlled by V _c, the same effect as a variable resistor R3a embodiment 1 can be obtained.

FIG. 5 is a block diagram showing a case where the hysteresis comparator according to the second embodiment is applied to a light receiving section of a laser beam printer.

The photodiode 11 receives the optical signal of the laser diode 10 and outputs a current signal. The preamplifier 12 which receives the current signal converts the current signal into a voltage signal, and outputs a hysteresis comparator 14 and a hysteresis width control. An electric signal is output to the circuit 13.

The hysteresis width control circuit 13 controls the voltage difference between the input terminals 7 and 8 of the hysteresis comparator 14 according to the magnitude of the input signal, and outputs the hysteresis width of the hysteresis comparator 14 to the input terminals 2 and 3. Optimized for Hysteresis comparator 14
Compares the levels of the signals input to the input terminals 2 and 3 and outputs the signals to the output terminals 5 and 6.

According to the circuit shown in FIG. 5, the optimum hysteresis width can be automatically set with respect to the laser input level.
Even for a signal having a constant / N ratio, the noise at the input level does not exceed the hysteresis width and does not malfunction, so that the dynamics of the laser input level can be widened.

[0059]

As described above, according to the present invention, since the hysteresis width can be varied, the dynamic range of the input signal can be widened.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a hysteresis comparator according to a first embodiment of the present invention.

FIG. 2 is an input / output characteristic diagram of the hysteresis comparator of FIG.

FIG. 3 is a circuit diagram illustrating a hysteresis comparator according to a second embodiment of the present invention.

4 is an input / output characteristic diagram of the hysteresis comparator of FIG.

FIG. 5 is a block diagram showing a stress circuit of the hysteresis comparator of FIG. 3;

FIG. 6 is a circuit diagram showing a conventional hysteresis comparator.

FIG. 7 is an input / output characteristic diagram of the hysteresis comparator of FIG. 6;

FIG. 8 is a circuit diagram showing a conventional hysteresis comparator.

9 is an input / output characteristic diagram of the hysteresis comparator of FIG.

[Explanation of symbols]

_{Q 1 ~Q 10, Q 101 ~Q} 106, Q 201 ~Q 204, Q 221 ~Q
_228, transistor R _1a to R _5a resistor R _203a to R _205a resistor I _1a current source 1 the first power supply terminal 2 first input terminal 3 and the second input terminal 4 and the second power supply terminals 5 and 6 an output terminal 7, 8 Input terminal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 19/00-19/32 H03K 5/08-5/12 H03F 3/45

Claims (2)

(57) [Claims] 1. A hysteresis comparator having a differential circuit, a current mirror load, and an offset voltage control means, wherein the differential circuit has two transistors forming a differential pair,
An input signal is input to the bases of the two transistors, and an output signal proportional to the difference is output between the collector and the collector. A current mirror load is connected between the collectors of the transistors forming the differential circuit. The offset voltage control means comprises a variable resistor connected between the emitters of the transistors forming the differential circuit, and includes a base for the transistors forming the differential circuit. The offset voltage between the two input terminals provided at least is connected between the emitters at least.
Of the transistor forming the current mirror load
Determined based on a predetermined emitter area ratio
Wherein the resistance connected between the emitters is variable.
Hysteresis comparator, characterized in that. 2. A differential circuit, a current mirror load, and an
Hysteresis comparator having offset voltage control means
The differential circuit has two transistors forming a differential pair,
An input signal is input to the bases of two transistors,
Outputs an output signal proportional to the difference between the collector
The current mirror load is a transistor which forms the differential circuit.
Connected between the collectors of the
The offset voltage control means includes a second differential circuit and a current control circuit.
And the second differential circuit includes two transistors forming a differential pair.
And a resistor connected in parallel to the differential circuit.
And the current limiter includes two transistors forming a differential pair.
For adjusting the current ratio of the second differential circuit.
Provided at the base of the transistor forming the differential circuit.
The offset voltage between the two input terminals is determined by the current limiter.
The voltage between the terminals of the transistors of the differential pair
A hysteresis comparator wherein the current ratio is adjusted and controlled .