JP2993701B2 - Solid-state imaging device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a solid-state imaging device.

[Conventional technology]

Conventionally, there has been no solid-state imaging device provided with a circuit that serially performs two different processes on a signal output from a photoelectric conversion element on the same element having a photoelectric conversion element that photoelectrically converts incident light.

[Problems to be solved by the invention]

For this reason, when performing two different processes on the signal output from the photoelectric conversion element, the signal is taken out of the imaging element and then the processing is performed, which requires a long reading time.

The present invention has been made in view of the above circumstances,
It is an object of the present invention to provide a solid-state imaging device capable of realizing high-speed reading.

[Means for solving the problem]

In order to solve the above problems, the present invention provides, on the same element, a photoelectric conversion unit that photoelectrically converts incident light, and a signal extraction control unit that controls extraction of a signal generated by photoelectric conversion from the photoelectric conversion unit. A first signal processing unit for processing a signal extracted by the signal extraction control unit; a storage unit for temporarily storing a signal processed by the first signal processing unit; and a signal stored in the storage unit A second signal processing unit that performs processing different from the first signal processing unit on the extracted signal, and a signal processed by the second signal processing unit can be output outside the element. And a driving means for synchronizing and outputting a first control signal for controlling the driving of the signal extraction control means and a second control signal for controlling the driving of the accumulating means. A solid-state imaging device according to claim.

[Action]

In the present invention, since the above means are formed on the same element, a signal obtained by performing two different processes on the signal output from the photoelectric conversion element is output outside the solid-state imaging element. .

〔Example〕

 Hereinafter, examples of the present invention will be described.

This embodiment is an example in which the present invention is applied to a solid-state imaging device having a frame interline transfer structure or a frame transfer structure. FIG. 1 is a conceptual diagram of the embodiment.

The solid-state imaging device 1 of the present embodiment sequentially reads out the charges accumulated in the light receiving unit 2 in which charges corresponding to the irradiation light amount are accumulated, and reads out the accumulated charges with different exposure times. And a signal processing unit 4 that outputs a value obtained by slicing a fixed pattern noise when the light receiving unit 2 is saturated when a slice level for cutting off excess charge is set in advance and the signal processing unit An accumulator 5 for sequentially storing the outputs of the accumulator 4, an adder 6 for adding the electric charges read out from the accumulator 5 at each exposure time, a horizontal shift register 7 to which the sum of the adder 6 is input, The output buffer 8 that outputs the electric charge transferred by the horizontal shift register 7 as a video signal is a main component.

FIG. 2 is a diagram showing a specific configuration of the embodiment. A plurality of photosensors 11 arranged on a matrix, a light receiving unit transfer gate 12 provided to each of these photosensors 11 and to which a drive pulse for reading is applied, and a photosensor 11 arranged in a vertical direction. The light receiving section 2 is composed of a plurality of first vertical shift registers 13 provided along the individual transfer gates 12 and transferring the charge read from the photo sensor 11.

One end of each vertical shift register 13 is connected to a signal processing circuit 15 via a light receiving section output buffer 14 composed of a floating diffusion amplifier.
The output side of each signal processing circuit 15 is a second vertical shift register
16 is connected to one end. Second vertical shift register
Reference numeral 16 denotes a plurality of registers for temporarily storing the charge read out from each photosensor 11 for each pixel. Each register is connected to an adder shift register 18 via a storage transfer gate 17. The adder shift register 18
The second vertical shift register 16 has a function of sequentially adding charges read out from each of the registers a plurality of times. One end of each adder shift register 18 is connected to a horizontal shift register 19, and the charges transferred by the horizontal shift register 19 are output from an output buffer 20.

The light receiving unit output buffer 14 has the configuration shown in FIG. A voltage is applied to each of the horizontal shift register electrodes 21 to transfer the read charge from the electrode 21a located on the input side to the electrode 21c on the output side, and transfer the charge to the floating diffusion FD via the output gate OG. Lead. The potential of the floating diffusion FD is reset to the same potential as that of the sweeping drain DD by a reset pulse applied to the reset gate RG. The cycle of the reset pulse is synchronized with the charge transfer cycle. The charge guided to the floating diffusion FD is output to the signal processing circuit 15 via the output buffer 23.

The signal processing circuit 15 has the configuration shown in FIG. The output of the light receiving unit output buffer 14 is applied to the input terminal 24 of the signal processing circuit 15. The input terminal 24 is connected via a clamp capacitor C to one base of a slice transistor 25 which connects the collector and the emitter of the two transistors. To the other base of the slice transistor 25, a slice-level voltage serving as a threshold when slicing excess charges is applied.
A constant voltage Vcc is applied to the collectors connected to each other. The potential appearing at the emitter of the slice transistor 25 is output to the second vertical shift register 16.
Note that the signal processing circuit 15 also sets a clamp level. Therefore, the base of the clamp transistor 26 is
A feed-through clamp pulse shown in FIG. 2B is applied, a clamp level voltage is applied to the emitter, and the collector is connected to the base of the slice transistor 25.

The adder shift register 18 has a capacity sufficient to accumulate charges sequentially read out at different exposure times, the area thereof is set larger than that of the second vertical shift register 16, and the applied voltage Is also set to a large value.
Further, in order to increase the capacity of the adder shift register 18, the impurity concentration of the silicon substrate forming the adder shift register 18 is increased.

Next, the operation of the present embodiment thus configured will be described.

The electric charges accumulated in each photosensor 11 are sequentially read out to the first vertical shift register 13 by a read pulse applied to each light receiving unit transfer gate 12, transferred by the first vertical shift register 13, and output to the light receiving unit output buffer.
Enter in 14. The charges input to the light receiving unit output buffer 14 are output in synchronization with the charge transfer cycle and sequentially input to the signal processing circuit 15. As shown in FIGS. 5 (a) and 5 (b), a feed-through clamp pulse (b) is applied to the base of the clamp transistor 26 in accordance with the feed-through period of the input signal. The feedthrough level is clamped to the clamp level set by the clamp transistor 26. Such clamping is performed every time a feed-through level appears. The signal thus clamped is a slice transistor
After being sliced at the slice level by 25, it is input to the second vertical shift register 16.

All charges from the light receiving section are transferred to the second vertical shift register 16
Then, a drive pulse is applied to the storage section transfer gate 17, and the electric charge of the second vertical shift register 16 is transferred to the addition section shift register 18.

Here, in the present embodiment, the storage unit transfer gate 17
Then, the driving pulse shown in FIG. 6 is applied. In FIG. 6, t ₀ indicates an exposure start time, and φ _{1 to} φ ₅ indicate drive pulses for transferring the electric charge of the second vertical shift register 16 to the adder shift register 18. . As a result, the charge sequentially accumulated for each pixel in the second vertical shift register 16 is read by the pulse phi ₁ to [phi] _5,
Five images having different exposure times are transferred to each register of the adder shift register 18 for each pixel (photo sensor), and are added there. Then, after read out a plurality of images by applying a pulse phi ₁ to [phi] _5, to transfer the charge from the adding unit shift register 18 with a period of t ₀ to the horizontal shift register 19, via the output buffer 20 Transfer charges outside the device.
The transfer of the electric charge to the horizontal shift register 19 is performed by the adder shift register 18. The charge transferred by the horizontal shift register 19 is output as a video signal via the output buffer 20.

The photoelectric conversion characteristics obtained by such an operation will be described with reference to FIG. Incidentally, in the figure shows a photoelectric conversion characteristic that takes place between the time t ₁ of time t _5.
f ₁ ~f ₅ is a photoelectric conversion characteristics corresponding to t ₁ ~t ₅ each exposure time. Therefore, charges obtained in t ₁ ~t ₅ each exposure time is added by the addition unit shift register 18 for each pixel is converted into the photoelectric conversion characteristics such as F _0. The F ₀ characteristic may be a logarithmic waveform or a square root waveform.

Until now, the addition was performed by changing the exposure time.
The adding operation may be performed with the exposure time kept constant. That is, by performing addition without changing the exposure time, cumulative addition is performed, and random noise can be reduced, and as a result, the dynamic range can be expanded. For example, by adding four times, Wide dynamic range. When this driving method is used, the effect of the wide dynamic range is small, but the photoelectric conversion characteristics become linear, and there is an advantage that the processing circuit after output of the solid-state imaging device 1 is simplified.

As described above, according to the present embodiment, the charges read out from the plurality of photosensors 11 are input to the signal processing circuit 15, where the clamp level is set, and the excess charges are reduced by the slice transistor 25 at the slack level. Since the excess charge included in the charge read by slicing is cut, even if fixed charge noise is included in the charge read from each photosensor 11, the noise component can be cut. .

In addition, since the noise component is cut in this way and a plurality of charges obtained by changing the exposure time are added for each pixel by the adding unit shift register 18, the dynamic range can be expanded. it can.

As a result, it is possible to obtain a video signal that does not include a noise component and has an expanded dynamic range, obtains an extremely accurate image without being affected by the luminance of the subject, and further obtains a normal TV rate. It is also possible to obtain an image with an expanded dynamic range.

Further, an adder shift register provided inside the element
Since a plurality of images are added in step 18, the reading time can be greatly reduced as compared with a case where a plurality of images are taken out of the element and then added.

 Next, a modification of the above embodiment will be described.

In the above embodiment, the example in which the floating diffusion amplifier is used as the light receiving unit output buffer 14 has been described. However, the light receiving unit output buffer 14 may be formed of one potential well.

FIG. 8 shows the configuration of the light-receiving unit output buffer 14 and the corresponding signal processing circuit 15 when the light-receiving unit output buffer 14 is formed of one potential well. In this modification, between the light-receiving unit output buffer 14 and the signal processing circuit 15,
A floating drain 30 is provided, and a sweeping drain 32 is connected to the floating drain 30 via a sweeping transfer gate 31. FIG. 9 shows the eighth
FIG. 3 is a sectional view taken along line AA shown in FIG.
3 shows the state of the potential. Incidentally, to produce an element to be constant depth P _TG potential well for each column.

With this configuration, the density of the slice circuit for slicing the excess charge can be increased,
The size of the element can be reduced.

Further, as another modified example, a floating gate amplifier can be used for the light receiving unit output buffer 14.

Since the floating gate amplifier has excellent DC voltage stability and low noise, the clamp circuit of the signal processing circuit 15 can be omitted.

Therefore, the signal processing circuit 15 can be composed of only the slice circuit 40 as shown in FIG. That is, the electric charge applied to the transfer electrode 33 in the light-receiving unit output buffer 14 is transferred from the transfer electrodes 33a to 33c and guided to the floating gate 34. A DC bias voltage is applied to the electrode 35 of the floating gate 34. The electrode 35 is connected to a slice circuit 40 of the signal processing circuit.

The slice circuit 40 includes three field effect transistors 41, 4
The transistors 41 and 42 have their sources and drains connected to each other, the gate of one transistor 41 is connected to the electrode 35, and the gate of the other transistor 42 is applied with a slice-level voltage. A power supply is connected to the drains of the transistors 41 and 42 which are connected to each other, and a source side is connected to the output terminal 44 and to another transistor 43 forming a constant current source.

Although a bipolar transistor can be used instead of the field effect transistor, the use of the field effect transistor is advantageous in simplifying the manufacturing process since the CCD itself uses the field effect.

In the above description, the case where the slice level is constant is taken as an example. However, the slice level may be changed according to the exposure time, and by doing so, the degree of freedom of the characteristic F ₀ shown in FIG. Can be increased. Therefore, when simplifying the drive circuit, fix the slice level,
It is desirable that the slice level is variable when it is desired to increase the degree of freedom in characteristics F _0.

〔The invention's effect〕

As described above in detail, according to the present invention, it is possible to provide a solid-state imaging device capable of realizing high-speed reading.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of the embodiment, FIG. 2 is a configuration diagram of a solid-state imaging device according to the embodiment, FIG. 3 is a configuration diagram of a light receiving unit output buffer, FIG. 4 is a configuration diagram of a signal processing circuit, and FIG. FIG. 6 is a diagram for explaining the operation of the signal processing circuit, FIG. 6 is a diagram showing a driving pulse applied to the storage section transfer gate, FIG. 7 is a diagram showing photoelectric conversion characteristics according to each exposure time, and FIG. FIG. 9 is a diagram showing a modification of the internal output buffer, and FIG. 9 is a diagram showing AA shown in FIG.
FIG. 10 is a sectional view taken along a line, and FIG. 10 is a view showing another modification. 1 ... solid-state imaging device, 2 ... light receiving unit, 3 ... driving unit, 4
…… Signal processing section, 5… Storage section, 6… Addition section, 7,19…
… Horizontal shift register, 8,20 …… output buffer, 11 ……
Photo sensor, 12 ... Transfer gate, 13 ... First
Vertical shift register, 14 ... Receiver output buffer, 15
... A signal processing circuit, 16... A second vertical shift register,
17: accumulation part transfer gate, 18: addition part shift register.

Claims (1)

(57) [Claims] 1. A photoelectric conversion unit for photoelectrically converting incident light on the same element, a signal extraction control unit for controlling extraction of a signal generated by photoelectric conversion from the photoelectric conversion unit, and a signal extraction control unit First signal processing means for processing the signal extracted by the above, storage means for temporarily storing the signal processed by the first signal processing means, and the signal stored in the storage means to be extracted and extracted A second signal processing unit that performs different processing on the signal from the first signal processing unit; an output unit configured to output a signal processed by the second signal processing unit to outside the element; A solid-state imaging device comprising: a first control signal for controlling the driving of a signal extraction control unit; and a driving unit for outputting a second control signal for controlling the driving of the storage unit in synchronization with the first control signal. Child.