JP2997221B2 - A / D conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D conversion circuit, and more particularly, to an AC-coupled A / D conversion circuit for performing successive comparison using an inverter which receives an input voltage signal via a capacitor as a comparator. The present invention relates to an A / D conversion circuit which can reduce a determination error due to droop of a sampled voltage, achieve higher accuracy, and perform high-speed conversion.

[0002]

2. Description of the Related Art One of the A / D conversion circuits is an AC-coupling type A / D conversion circuit using a CMOS inverter having an input capacitor as a comparator. Used with sample and hold circuits. An A / D conversion value is obtained by comparing the sample voltage held by the sample hold circuit with a reference voltage that is sequentially set. FIG. 3 shows an example of the A / D conversion circuit 8, which is input to the input terminal 7 by turning on the switch SW1 of the sample and hold circuit 1 by a sample signal, and the sampled and held input voltage signal Vs is It is once held in the capacitor C1. The held voltage Vs is supplied to an AC-coupled comparator 3 using an inverter via an A / D conversion switching circuit 2.

The switching circuit 2 receives the switching signal S, switches between the reference voltage VR and the sample voltage Vs of the sample and hold circuit 1 in response to the switching signal S, and inputs the switching to the comparator 3. The switching circuit 2 first receives signals from the controller 4 as shown in FIG.
Upon receiving the switching signal S shown in (a), it switches to the sample voltage Vs side at the rise. At this time, at the same time, the controller 4 first switches the switch circuit SW of the comparator 3.
The switching signal S is added to 2 to turn it on. As a result, the voltage Vs of the sample and hold circuit 1 is
This capacitor is charged in addition to the AC coupling capacitor C2.
As a result, the threshold voltage of the inverter VTH = Vcc /
2, the capacitor C2 is connected to the sample voltage Vs-
Charged at a voltage of Vcc / 2 (however, sample voltage Vs
> Vcc / 2) . The voltage Vcc is a power supply voltage for the CMOS inverter of the comparator 3.

Next, the switching signal S from the controller 4 falls, and at this falling timing, the switch circuit SW2 of the comparator 3 is turned off. In this state, the switching circuit 2 is switched to the D / A conversion circuit 5 side. As a result, the comparator 3 receives the comparison reference voltage VR from the D / A conversion circuit 5 via the switching circuit 2, and enters the comparison judgment while the switching signal S is at the LOW level (hereinafter "L"). The inverter generates a HIGH-level (hereinafter, “H”) output when the sample voltage Vs exceeds the comparison reference voltage VR, and generates an “L” output otherwise.

[0005] The output result of the comparator 3 is received by the controller 4, and when the judgment result is “1” (= “H”), the digital signal set in the register 6 sent to the D / A conversion circuit 5 is set. Increment the value by +1. Next, the switching signal S rises again to "H", and the next judgment is started. Hereinafter, the same operation is repeated. In this operation, the output result of the comparator 3 is “0” (=
"L"), and during the period when the switching signal S is "L", when the determination result becomes "L", the controller 4 outputs the digital value of the register 6 as an A / D conversion value. I do. When the sample voltage Vs <Vcc / 2
, The determination result is reversed and sent to the D / A conversion circuit 5.
Decrement the digital value set in register 6
And make it smaller.

[0006]

In this type of A / D conversion circuit, it is necessary to secure sufficient time for receiving the sample voltage Vs and charging the capacitor C2 in order to perform more accurate A / D conversion. . Therefore, the switching signal S is set to “H”.
The period T1 becomes longer, and it is necessary to secure the processing time of the "L" period because of the determination process. Therefore, the switching signal S in FIG. 4A is usually a pulse having a duty ratio of about 50%. Therefore, there is a certain limit in increasing the frequency of the switching signal S. Such a pulse is repeated until the output result of the comparator 3 becomes "0".

However, in response to the result of the determination, D /
FIG. 4 shows the relationship between the A conversion and the rising timing.
As shown in (b), when the ringing phenomenon occurs,
It takes time for it to stabilize. Since the ringing phenomenon R is at most about several tens of percent from the rise of the switching signal S, in such a case, the determination is made without the sample voltage Vs being stabilized. As a result, there is a problem that D / A conversion values are not stabilized and accurate A / D conversion is not performed. In addition, D / A Contact Keru to conversion A of this kind
An A / D conversion circuit using a C-coupled inverter is usually
Since a sample-hold circuit and an A / D conversion circuit are required, one A / D conversion value is obtained by successive approximation processing instead of parallel detection processing. Therefore, there is a problem that it takes time to obtain an A / D conversion result (a determination result by the controller).

In addition, when such successive comparison is performed, a determination error occurs due to a droop (decrease) of the voltage of the capacitor for holding the voltage of the sample and hold circuit, which is a problem. In order to avoid this, it is conceivable to increase the circuit scale and provide a plurality of AC-coupled A / D conversion circuits to perform parallel detection processing. When the parallel detection processing is performed in relation to the capacity of the AC coupling capacitor, which is usually several tens to several hundreds of pico than several pico,
There is a problem that the input voltage changes. The present invention solves such a problem of the prior art, and provides an A / D conversion circuit which has a small determination error due to droop of a sampled voltage, has higher accuracy, and can perform high-speed conversion. The purpose is to do.

[0009]

A feature of the A / D conversion circuit of the present invention for achieving the above object is that a threshold voltage VTH is used as an inverter corresponding to the number n of A / D conversion bits. Vcc / 2 for voltage Vcc
Are connected in parallel, the sampled voltages are simultaneously received by the n inverters, and the comparison reference voltage VR of the most significant bit of the A / D conversion bit number n is Vcc / 2.
The comparison reference voltage VR at which the inverter corresponding to the next lower-order bit sequentially performs the comparison and determination of the next lower-order bit with respect to the voltage sampled as D / A based on the data of the determination result of the upper-order bit By conversion circuit
And the comparison reference voltage V
The determination criterion based on R is limited to a range of 1/2 at a time, and the determination up to the least significant bit is performed.
/ D conversion value.

[0010]

DETAILED DESCRIPTION OF THE INVENTION Thus, in response to the sampled voltage value on held in the inverter input capacitance at a time, half a criterion in each successive comparison times Dzutsuhan
As being enclosed limitation, follow sets the VR + Vcc / 2 ⁿ or VR-Vcc / 2 ⁿ as comparison reference voltage VR of the next lower bit with respect to the specific reference voltage VR, by repeating the comparison determination, It is not necessary to input the voltage from the capacitor of the sample-and-hold circuit each time the determination is made. This eliminates a determination error due to droop of the sample voltage. In addition, since the sample-and-hold circuit does not need to generate a switching signal corresponding to one bit in order to charge the capacitor for each bit comparison, the conventional time of the charging time of the sample voltage for the input capacitor times the number of conversion bits is almost equal. Since one bit is required, the entire A / D conversion time is reduced.

[0011]

FIG. 1 is a block diagram of an embodiment to which an A / D conversion circuit according to the present invention is applied. FIG. 2 is an explanatory diagram of the waveform of the switching signal. Note that the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted. 10 is A /
This is a D conversion circuit, and does not include a sample and hold circuit in FIG. And the number of bits A / D conversion n
Corresponding to the comparators 3a to 3n in which n comparators 3 of the CMOS inverter in FIG.
3n. That is, each of the comparators 3a to 3n corresponds to the comparator 3. In FIG. 1, n =
8 shows a circuit in the case of 8 bits.

Further, the A / D conversion circuit 10 includes a switching circuit 11, a selection circuit 12, a latch circuit 13, and a controller 14. In this embodiment, as shown in FIG. 2, the switching signal S has one pulse, and its waveform is different from that of FIG. That is, the period of the pulse width T2 of "H" of the switching signal S during which the capacitor C2 receives the sample voltage Vs is longer than the pulse width T1 of FIG. 4, and the pulse width T2 is T2> T1. Further, the controller 14 outputs a switching signal S (see FIG. 2A)
In addition, a selection signal SEL (see FIG. 2B) and a latch signal Ls (see FIG. 2C) are generated to start the determination. In this example, the n comparators 3a to 3n are arranged in the order of 3a to 3n from the most significant bit to the least significant bit of the digital value to be A / D converted.

The switching circuit 11 comprises two-input one-output switching circuits 11a to 11n. Each of these switching circuits corresponds to the switching circuit 2 shown in FIG. 3, except for the switching circuits 11b to 11b except for the switching circuit 11a. 11n has an intermediate position that is not connected to any input terminal. This is different from the switching circuit 2 in this point. The outputs of the switching circuits 11a to 11n are connected to the inputs for charging the capacitor C2 of the comparators 3a to 3n, respectively. The selection circuit 12 includes n switch circuits 12a to 12n that receive respective outputs of the comparators 3a to 3n. The latch circuit 13 includes the switch circuits 12 a to 12 a corresponding to the least significant bit to the most significant bit.
The flip-flops in the upper to lower bit positions corresponding to each output of 12n are composed of n flip-flops connected to the corresponding bit outputs.

The selection circuit 12 and the latch circuit 13 receive the control signal SEL from the controller 14 and select their respective switch circuits or flip-flops sequentially from the most significant bit to the least significant bit. Further, the controller 14 receives the output n bits of the flip-flop of the latch circuit 13 in parallel, determines the contents thereof,
Data (digital value) corresponding to the next lower bit comparison reference voltage VR is output to the register 6 according to the determination result. This setting data will be described later.

The controller 14 corresponds to the controller 5. In this embodiment, each of the comparators 3a to 3n is switched while switching between the switching circuit 11 and the selection circuit 12.
Are sequentially determined bit by bit from the most significant bit to the least significant bit, and the determination result is latched.
Is controlled by latching in the flip-flop at the corresponding bit position. In addition to the switching signal S in FIG. 2A, a selection signal SEL (FIG. 2B) for that is switched by the switching circuit 11 and the selection circuit. 12 is sent. The switching circuit 11 and the selection circuit 12 receive the switching signal S and the selection signal SEL, switch the internal switch circuit from the most significant bit to the lower bit in order according to the selection signal SEL, and switch only one of them. The switching circuit 11 is connected to the comparison reference voltage VR,
The selection circuit 12 turns on only one of them.

Hereinafter, the overall operation will be described focusing on the operation of the controller 14. The controller 4 first outputs the switching signal S shown in FIG.
In addition to the 3n switch circuits SW2, these are simultaneously turned on.
Set to N. At this time, the controller 4 also applies the switching signal S to the switching circuit 11 at the same time. The switching circuit 11 first receives one switching signal S, sets all of the switching circuits 11a, 11b,..., 11n to the side receiving the sample voltage signal Vs at the rise of the switching signal S, and is input. The sample voltage Vs is simultaneously applied directly to each AC coupling capacitor C2 to charge them.

As a result, the capacitors C2 of the comparators 3a to 3n simultaneously output the sample voltage Vs
Is charged. The signal of the sampled voltage at this time is held by the entire stray capacitance inserted in parallel, but the capacitance at this time is much smaller than that of the sample and hold capacitor C1 in FIG. Next, the switching signal S from the controller 14 falls, and the comparators 3a to 3a correspond to the falling timing.
The n-th switch circuit SW2 is turned off. Then, the switching circuits 11b to 11n are set to intermediate positions where no input is received. In response to the rise of the selection signal SEL shown in FIG.
Switching to the / A conversion circuit 5 side (connection state shown) , the selection circuit 12 also receives the first selection signal SEL shown in FIG. 2A and turns on the switch circuit 12a.

By the switching of the switching circuit 11a, the comparator 3a enters the comparison judgment while the switching signal S is "L" when the switching circuit 11a receives the comparison reference voltage VR from the D / A conversion circuit 5. In addition, data for generating an analog voltage of Vcc / 2 from the controller 14 is set in the register 6 in accordance with the rising timing of the first switching signal S in the register 6. That is, it is first determined whether the sample voltage Vs is higher or lower than Vcc / 2. When the sample voltage Vs is higher than Vcc / 2, the result of determination set in the flip-flop is "1". The determination result set in the loop becomes “0”.

Therefore, the determination result of the most significant bit is obtained during the "L" period of the switching signal S, which is latched by the latch circuit 13 at the rise of the latch signal Ls. Note that each flip-flop of the latch circuit 13 has its value reset at the rise of the switching signal S. Controller 14
The latch signal L shown in FIG. 2C is synchronized with the timing when the determination is completed during the period when the switching signal S is "L".
s is added to the latch circuit 13, and at the rising edge, the output result of the comparator 3a is latched in the highest-order flip-flop of the latch circuit 13. At the falling edge of the latch signal Ls, the controller 14 takes in the output from the latch circuit 13.

When the determination result is "1" based on the obtained determination result of the most significant bit, the controller 14
Assuming that the sample voltage signal Vs is a voltage higher than Vcc / 2, the current comparison reference voltage V
VR = VR + Vcc / 4 (= Vcc / 2 + Vcc /
The data value which becomes the voltage of 4) is obtained as the comparison reference voltage VR of the next lower bit, and is set in the register 6. On the other hand, when the obtained most significant bit determination result is “0”, it is determined that the sample voltage signal Vs is lower than Vcc / 2, and then the current comparison reference voltage VR of the D / A conversion circuit 5 is output.
VR = VR−Vcc / 4 (= Vcc / 2−Vcc / 4)
Is obtained as the comparison reference voltage VR of the next lower bit and set in the register 6.

Then, the next selection signal SEL shown in FIG.
The next switching circuit 11b is moved from the intermediate position to D by the rise of
The comparator 3b switches to the / A conversion circuit 5 and receives the newly set comparison reference voltage VR to make the comparator 3b determine the next lower bit. At this time, the selection circuit 12 also receives the next selection signal SEL shown in FIG. 2A, turns off the switch circuit 12a, and turns on the switch circuit 12b at the bit position corresponding to the next determination. Comparator 3
The determination result of b is latched by the next lower bit flip-flop of the latch circuit 13 at the rise of the latch signal Ls, as described above. The controller 14 receives the determination result, and when the determination result is “1”, sets the data value which becomes VR = VR + Vcc / 8 with respect to the current comparison reference voltage VR to the comparison reference voltage of the next lower bit. It is obtained as VR and set in the register 6. On the other hand, when the obtained judgment result is “0”, the sampled voltage signal Vs is Vcc
Assuming that the voltage is lower than / 2, next, with respect to the current comparison reference voltage VR of the D / A conversion circuit 5, VR = VR-Vcc /
The data value which becomes the voltage of 8 is obtained as the comparison reference voltage VR of the next lower bit, and is set in the register 6.

In this manner, the controller 14 moves to the next bit position, repeats the same processing, and sequentially changes the current comparison reference voltage VR in accordance with the determination results of "1" and "0". Te VR = VR + Vcc / 2 ⁿ or VR = VR
−Vcc / 2 ⁿ The comparison reference voltage VR of the lower bit next to ⁿ (where n is a numerical value that is incremented to n = n + 1 each time the most significant bit is set to n = 1 and the determination is made toward the lower bit) is stored in the register 6. By setting the D / A conversion circuit 5 to generate the reference voltage VR of the next lower bit, the sample voltage Vs is updated by n + 1 each time the determination is made, and the A / D conversion is performed.
N is updated by the number of conversion bits n.

As a result , the next highest bit (n = 1)
G (n = 2), the comparison reference value VR is as described above.
Calculation of ± Vcc / 4 for the highest comparison reference value VR
And VR = VR ± Vcc / 4 (ie, when n = 2,
VR = VR ± Vcc / 2 ² ), and the next bit
(N = 3) is the next highest comparison base
An operation of ± Vcc / 8 is performed on the reference value VR, and VR = VR ±
Vcc / 8 (that is, VR = VR ± Vcc when n = 3)
/ 2 ³⁾ calculated as, by limiting the 1/2 increments range criteria in each successive comparison times, go drove to follow the comparison value to the sample voltage at Vcc / 2 ⁿ increments. In this manner, the sample voltage Vs approaches the sample voltage Vs, and finally, the A / D converted value of the sample voltage Vs is converted into the least significant 1 bit determined by Vcc / 2 ⁿ corresponding to the number n of A / D conversion bits. The whole A / D converted value is obtained in the latch circuit 13 with the resolution. The controller 14 makes n comparison decisions,
When the last least significant bit is determined, the data of the latch circuit 13 is received as an A / D conversion value and output serially or in parallel from the output terminal 14a to the outside.

Considering the A / D conversion in this case, first, in this embodiment, since there is no sample and hold circuit, it is not necessary to sequentially input the voltage from the capacitor C1.
In addition, since the input capacitor C2 of each inverter receives the sample voltage Vs at a time, there is almost no determination error due to droop of the sample voltage Vs. Further, the period of the pulse width of the switching signal S is longer than the pulse width T1 of FIG.
Since the pulse width T2 satisfies T2> T1, even if the ringing phenomenon R becomes about several tens%, it is hardly affected by the ringing phenomenon R. In particular, the pulse width T2 is changed to the conventional pulse width T
70% to 80% for 1 (= 50% of the conventional cycle)
By setting to about, you can eliminate the ringing phenomenon,
The inverter can start the judgment at the timing when the sample voltage Vs is stabilized. Thereby, a more accurate A / D conversion value can be obtained.

The "H" period of the switching signal S corresponding to one bit for charging the capacitor C2 from the sample-and-hold circuit for each one-bit comparison shown in FIG. Since no conversion bit is provided, when the number of conversion bits is the same, the entire A / D conversion time is reduced as shown in FIG.
It is shortened as compared with (a). As a result, high-speed A / D
Conversion becomes possible.

As described above, the controller 14 of the embodiment is simply described as a black box. However, this is because the timing control signal is fixed.
It can be easily configured by a logic array, a gate array, or the like, or can be realized by program processing by providing a CPU, an MPU, and a memory. Also, the inverter used as the comparator has a threshold voltage VTH substantially equal to Vcc / 2 of the power supply voltage Vcc of the inverter.
Is not limited to a CMOS inverter. Furthermore, in the embodiment, the sample-and-hold circuit is not provided. However, even if the sample-and-hold circuit is provided, the switching process only needs to receive the sample-and-hold voltage once, so that the A / D conversion process can be speeded up. In addition, a determination error due to droop of the sample and hold voltage can be prevented. Therefore, in the present invention, it does not matter whether a sample hold circuit is provided.

[0027]

As described above, according to the present invention, the voltage value sampled at a time is received and held in the input capacitor of the inverter, and the comparison is repeated.
And follow-up setting to limit the judgment criterion by 1/2 ,
By repeating the comparison and determination, it is not necessary to input the voltage from the capacitor of the sample and hold circuit every time the determination is made. This eliminates a determination error due to droop of the sample voltage. In addition, since the sample-and-hold circuit does not need to generate a switching signal corresponding to one bit in order to charge the capacitor for each bit comparison, the conventional time of the charging time of the sample voltage for the input capacitor times the number of conversion bits is almost equal. Since one bit is required, the entire A / D conversion time is reduced. As a result, it is possible to realize an A / D conversion circuit that has a small determination error due to droop of the sampled voltage, has higher accuracy, and can perform high-speed conversion.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment to which an A / D conversion circuit of the present invention is applied.

FIG. 2 is an explanatory diagram of a waveform of the switching signal in FIG.

FIG. 3 is a block diagram of a conventional A / D conversion circuit.

FIG. 4 is an explanatory diagram of a waveform of a switching signal in FIG. 3;

[Explanation of symbols]

1. Sample hold circuit 2. Switching circuit 3, 3a,
3b, 3n: comparator, 4, 14: controller,
5: D / A conversion circuit, 6: register, 10: A / D conversion circuit, 11, 11b, 11n: switching circuit, 12: selection circuit, 12a, 12b, 12n: switching circuit, 13: latch circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-273651 (JP, A) JP-A-5-335955 (JP, A) JP-A-8-162955 (JP, A) JP-A 64-64 19829 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 1/38 H03M 1/14

Claims (3)

(57) [Claims] 1. A successive approximation using an inverter which receives an input voltage signal via a capacitor as a comparator
In the C-coupled A / D conversion circuit, n inverters having a threshold voltage of Vcc / 2 with respect to the power supply voltage Vcc of the inverter are provided in parallel with the inverter corresponding to the number of A / D conversion bits n, The sampled voltages are simultaneously received by the n inverters, and the comparison reference voltage VR of the most significant bit of the A / D conversion bit number n is set to Vcc / 2.
Said sequential from sampled the most significant bit for the voltage as, based on the comparison reference voltage VR which the inverter corresponding to the next lower bit is then compared to the next lower bit data of the upper bits of the determination results D /
Each time the comparison is made by the A-conversion circuit and the number of comparisons is repeated, the judgment criterion based on the comparison reference voltage VR is limited to a range of づ, and the judgment is made up to the least significant bit. An A / D conversion circuit obtained as an A / D conversion value. 2. A method for performing successive comparison using an inverter which receives an input voltage signal via a capacitor as a comparator.
In the C-coupled A / D conversion circuit, n inverters having a threshold voltage of Vcc / 2 with respect to the power supply voltage Vcc of the inverter are provided in parallel with the inverter corresponding to the number of A / D conversion bits n, The sampled voltages are simultaneously received by the n inverters, and the comparison reference voltage VR of the most significant bit of the A / D conversion bit number n is set to Vcc / 2.
The comparison of the most significant bit is performed by the inverter corresponding to the most significant bit with respect to the sampled voltage, and the most significant bit is set to n = 1, and n = n + 1 is set for each lower bit. Based on the data of the determination result , the D / A conversion circuit sequentially converts the comparison reference voltage VR of the next lower bit into VR = VR + Vcc /
The comparison reference voltage VR of the next lower bit is generated as 2 ⁿ or VR = VR−Vcc / 2 ⁿ , and the inverter corresponding to the next lower bit performs the comparison judgment of the next lower bit to perform comparison. 1 each time
An A / D conversion circuit that obtains a determination result up to the least significant bit by limiting the range by / 2, and obtains n bits of the obtained determination result as an A / D conversion value. 3. The semiconductor device according to claim 1, further comprising an n-bit latch circuit, wherein said inverter is a CMOS inverter, and said judgment result of said n bits corresponding to said least significant bit to said least significant bit is sequentially determined by n of said latch circuit. 3. The A / D conversion circuit according to claim 2, wherein the signal is output at a bit position corresponding to the bit.