JP2997352B2 - FSK modulated wave demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for demodulating an FSK-modulated wave, and more particularly to a circuit for demodulating an FSK-modulated wave using a one-chip microcomputer and having improved discrimination of a frequency shift.
In the drawings, the same reference numerals indicate the same or corresponding parts.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a conventional FSK modulation wave demodulation circuit. This demodulation circuit is an application of a digital PLL circuit, and the phase comparator 1, the selection gate circuit 2, and the frequency divider 3 in FIG. 1 correspond to the PLL circuit. That is, an FSK modulated wave input from a communication line (not shown) is compared with the 0 level to be binarized, and is supplied to the phase comparator 1 as an FSK modulated wave input (modulated pulse) 31 of a square wave pulse. On the other hand, the output frequency f1 of the oscillator 6 or the output frequency f2 of the oscillator 7 is selected via the selection gate circuit 2 as described later, and is given to the frequency divider 3. In the phase comparator 1, the received FS
The phase comparison between the K-modulated wave input 31 and the output frequency-divided frequency of the frequency divider 3 is performed, and a selection signal 1a for selecting the oscillation frequency f1 or f2 that minimizes the phase shift is output. The selection signal 1a causes the selection gate circuit 2 to select the oscillator output f1 or f2 as described above. The selection signal output 1a is passed through the low-pass filter 4, and further subjected to waveform shaping via a waveform shaping circuit 5 to obtain an FSK demodulated output (also referred to as reception data) RD.

FIG. 5 shows another example of a conventional demodulation circuit. This demodulation circuit is an application of a delay circuit 8 that delays an input signal by a predetermined time, such as a one-shot multivibrator, and includes an FSK modulation wave input 31 and
EX of the input 31 with the delay output 8a by the delay circuit 8
An OR condition (exclusive OR) is obtained via the EXOR gate 9, and the output 9a is passed through the low-pass filter 4,
Further, waveform shaping is performed via the waveform shaping circuit 5, and FS
This is to obtain a K demodulation output RD.

[0004]

However, the conventional demodulation circuit has the following problems. (1) When the transmission speed is high (for example, 1200 BPS: 1
700 Hz), the number of carriers is small for one bit of data (eg, 1200 BPS, 1700 Hz ± 400 Hz)
1.083 waves at a band of 1300 Hz).
For slow return応速degree by the demodulation circuit by the PLL circuit of the digital, it is difficult to improve the strain tolerance and the like. (2) When the frequency shift is small and in a high frequency band (for example, 200
(BPS: 2800 Hz ± 100 Hz) indicates a small mark-space difference (2900 Hz:
2700 Hz = 54%: 45%), the circuit of FIG. 5 has poor data discrimination and relatively large distortion. (3) in the reception wave input Oite the specification range of frequencies (e.g., the lock range in the digital PLL circuit of FIG. 4 (i.e. range PLL circuit to the input wave can follow)
In the case of an outside input or an input outside the delay time range in the circuit of FIG. 5), the demodulation operation becomes unstable in the conventional demodulation circuit, and accurate demodulation output cannot be guaranteed. Therefore, an object of the present invention is to provide a demodulation circuit of an FSK modulated wave that can solve such a problem.

[0005]

According to the present invention, there is provided a means for sequentially outputting a differential pulse at each zero crossing point of an FSK modulated wave input from a communication line (comparator 14, differential circuit 15, etc.). , And the zero cross point
H and L are sequentially selected according to the differential pulse sequentially output every time.
Output the first square wave and differentiate
Means for sequentially measuring the time width between pulses (pulse width measurement counter 161, reception pulse output counter 163, etc.)
When, a means (such as a conversion table 162) that calculates and outputs a delay width increases and decreases in a predetermined relationship depending on the deviation between the measured half-period time width and the center frequency for each said time width, said first square A second square wave signal (such as a reception delay output 34) is output in which the rising and falling points alternately appearing in the wave signal are each delayed by the delay width obtained from the time width related to the point. means (receiving such delayed pulse output counter 164), and means (such as EXOR gates 9) for obtaining the EXOR conditions between the first square wave signal and the second square wave signal, said first square wave signal And the second square
E output from the means for obtaining the EXOR condition with the wave signal
It is assumed that the XOR output (such as 35) is smoothed, binarized, and the final demodulated data (such as RD) is output.

[0006]

The time width between the rising and falling points alternately appearing during the input of the FSK modulated square wave is sequentially measured, and a predetermined time is determined according to the difference (frequency shift) between the half cycle of the center frequency and the measured time width. And a square wave obtained by delaying the rising point and the falling point by the delay width corresponding to each of the rising and falling points, with reference to a conversion table for each time width. The signal obtained under the EXOR condition with the square wave before the delay is smoothed and binarized to obtain demodulated data.

[0007]

FIG. 1 is a block diagram showing a configuration of an FSK modulated wave demodulation circuit as an embodiment of the present invention, FIG. 2 is an explanatory diagram of a waveform delay operation of the one-chip CPU 16 of FIG. 1, and FIG. FIG. Next, the configuration and operation of FIG. 1 will be described with reference to FIGS. FSK of the waveform shown in FIG.
The modulated wave 30 is input from a communication line (not shown) to the isolation transformer 11 and is electrically insulated.
F) The signal is separated from the unnecessary band signal via 12 and then amplified by the amplifier (AMP) 13 and input to the comparator 14. The comparator 14 compares the input modulated wave 30 with the 0 level (that is, detects the zero cross point).
It is binarized and outputs a square wave modulated pulse 31 having the waveform shown in FIG. The modulated pulse signal 31 is supplied to a differentiating circuit 15 to be differentiated.
A differential output (pulse) 32 of the waveform shown in FIG.
16 is input.

The one-chip CPU 16 is a main component of the present invention, and includes therein a pulse width measurement counter 161 and pulse width data which represent the main internal processing of the CPU 16 equivalently in the form of hardware. A conversion table 162 for converting into delay width data, a reception pulse output counter 163, and a reception delay pulse output counter 164 are provided. Here, the pulse width measurement counter 161 measures each pulse width of the differential output 32 and temporarily transfers it to a data file (not shown). And this transferred data is then sent to the conversion table 162 and a received pulse output counter 1 6 3. Therefore, the reception pulse output counter 163 outputs the reception output 33 having the waveform shown in FIG. The reception output 33 has the same waveform as the modulation pulse 31, but has a waveform with a delay corresponding to the processing time after the output of the modulation pulse 31. On the other hand, the conversion table 162 receives pulse width measurement data from the counter 161, obtains delay width data for delaying the rising point and the falling point of the reception output 33 with predetermined conversion characteristics, and transfers the data to a data file (not shown). I do. This transfer data is then transmitted to the reception delay pulse output counter 164.
Sent to As a result, the counter 164 outputs the reception delay output 34 having the waveform shown in FIG.

Next, the conversion contents of the conversion table 162 will be described with reference to FIG. FIG. 3A is a waveform diagram showing the relationship between the reception output 33 and the reception delay output 34. In FIG.
T1 and T2 are pulse width data measured by the counter 161. Here, T1 is the transmission speed of the FSK modulation signal.
Pulse width data corresponding to the center frequency fc determined by the degree , T0 corresponds to a frequency (fc + Δf) accompanied by a change of + Δf, and T2 corresponds to a frequency (fc−Δf) accompanied by a change of −Δf. Pulse width data. That is, T0 = 1/2 (fc + Δf) T1 = 1/2 · fc T2 = 1/2 (fc−Δf) where Δf: frequency shift.

The conversion table 162 includes delay width data TD0, TD for each of the rising and falling edges of the reception output 33.
D1 and TD2 are output in accordance with the pulse width data T0, T1 and T2 corresponding to the respective edges. Here, there is a relationship of TD0 = (T0 / 2) + ΔTD0 TD1 = (T1 / 2) + ΔTD1 TD2 = (T2 / 2) + ΔTD2, and each delay width data TD0, TD1, TD2
FIG. 2 shows T0 / 2, T1 / 2, and T2 / 2 as 1/2 of the corresponding pulse width data, respectively.
Delay addition values ΔTD0, Δ given by the conversion characteristics of (B)
This is a value obtained by adding TD1 (= 0) and ΔTD2. That is, in this example, the delay addition value ΔTD1 = 0 for the pulse width T1 of the center frequency fc, and the negative delay addition value ΔTD0 is given for the pulse width T0 of the frequency (fc + Δf), and the frequency (fc− A positive delay addition value ΔTD2 is given to the pulse width T2 of Δf).

The reception output 33 and the reception delay output 34 output from the one-chip CPU 16 are EXO
The exclusive OR is calculated by the R gate 9, and the EXOR output 35 shown in the waveform of FIG. This EXOR output 35 is a low-pass filter (LP
F) The signal is smoothed by 4 to become an LPF output 36 having the waveform shown in FIG.
Is shaped into digital received data RD by a waveform shaping circuit 5 comprising a comparator for comparing the output of the comparator with the 0 level and a driver for amplifying the output of the comparator.

[0012]

According to the present invention, a differential pulse is sequentially generated at each zero cross point of the FSK modulated wave 30 input from the communication line.
Output means (comparator 14, differentiation circuit 15, etc.)
And the differential pulse sequentially output at each of the zero cross points
H and L are sequentially selected according to the first square wave signal.
Signal (received output 33) and the differential pulse
Means for sequentially measuring time width (pulse width measurement counter 16
1, a reception pulse output counter 163), and a conversion table 162 that calculates and outputs a delay width that increases or decreases in a predetermined relationship according to a deviation between the measured time width and a half cycle of the center frequency for each time width. A second square wave signal (reception delay output) in which the rising and falling points alternately appearing in the first square wave signal 33 are each delayed by the delay width obtained from the time width related to the point. 34), and an EXOR gate 9 for obtaining an EXOR condition of the first square wave signal 33 and the second square wave signal 34. The EXOR gate 9 outputs the EXOR condition . The EXOR output 35 is smoothed via the LPF 4 and then binarized via the waveform shaping circuit 5 to output the final demodulated data RD.

The following effects can be obtained. (1) As for the reaction speed of the demodulation circuit, it is possible to determine the frequency shift with one wave, and thus the above-mentioned problem (1) is solved. (2) By adjusting the conversion data table, the pulse width of the demodulated pulse signal in the mark space can be set arbitrarily, so that the discrimination of data is improved and the above-mentioned problem (2) is solved. (3) By preparing the wavelength data of the received wave at a frequency outside the range in the conversion data table, the stability of the demodulation operation at this input can be secured, and the above-mentioned problem (3) is solved. (4) The number of components in the demodulation circuit was reduced by using a one-chip microcomputer, and the circuit was further simplified.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a configuration as an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a waveform delay operation of the one-chip CPU of FIG. 1;

FIG. 3 is a waveform diagram of each part in FIG. 1;

FIG. 4 is a diagram showing an example of a configuration of a main part of a conventional FSK modulation wave demodulation circuit.

FIG. 5 is a diagram showing another example.

[Explanation of symbols]

Reference Signs List 4 low-pass filter (LPF) 5 waveform shaping circuit 9 EXOR gate 11 insulating transformer 12 band-pass filter (BPF) 13 amplifier (AMP) 14 comparator 15 differentiating circuit 16 one-chip CPU 30 line modulation wave 31 modulation pulse 32 differential output 33 reception Output 34 Reception delay output 35 EXOR output 36 LPF output RD Reception data 161 Pulse width measurement counter 162 Pulse width data → delay width data / conversion table 163 Reception pulse output counter 164 Reception delay pulse output counter T0 Pulse width data T1 Pulse width data T2 Pulse width data TD0 Delay width data TD1 Delay width data TD2 Delay width data ΔTD0 Delay addition value ΔTD1 Delay addition value ΔTD2 Delay addition value fc Center frequency Δ fc Frequency shift

Claims (1)

(57) [Claims] A means for sequentially outputting a differentiated pulse at each zero cross point of an FSK modulated wave input from a communication line, and responding to a differentiated pulse sequentially output at each zero cross point.
Output the first square wave by selecting H and L sequentially
Means for sequentially measuring the time width between differential pulses
When the delay width increases and decreases in a predetermined relationship depending on the deviation between the measured half-period time width and the center frequency and means for calculating output every said time width alternately in said first square wave signal Means for outputting a second square wave signal obtained by delaying a rising point and a falling point that appear by the delay width obtained from the time width relating to the point, respectively, and the first square wave signal and the second square wave signal. EXOR with square wave signal
And means for determining the condition, the first square wave signal and the EXOR conditions of the second square-wave signals
An FSK modulated wave demodulation circuit, which smoothes an EXOR output output from a means for obtaining a condition, binarizes the EXOR output, and outputs final demodulated data.