JP2999567B2 - Method for manufacturing semiconductor element and article used for its implementation - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and a device used for carrying out the method. The present invention relates to a production method which is less liable to occur, and a product used for implementing the method.

[0002]

2. Description of the Related Art Semiconductor devices are indispensable for today's industrial development. For this reason, various manufacturing methods for obtaining a semiconductor element having desired characteristics have been studied.

[0003] For example, a document (IEEE GaAs IC Symposium) related to the applicant of the present application.
(1989) p. 117) describes a method for manufacturing a high electron mobility transistor (hereinafter, referred to as “HEMT”). FIG. 8 is a schematic cross-sectional view of the HEMT provided for this description.

According to this document, first, semi-insulating GaAs is used.
A GaAs buffer layer 13, an AlGaAs buffer layer 15, and a Si-doped n ⁺ AlGaAs carrier supply layer 1 are formed on the s substrate 11 by MBE (molecular beam epitaxy).
7, a non-doped AlGaAs layer 19, a GaAs channel layer 21, a Si-doped n-GaAs layer 23, and a Si-doped n ⁺ GaAs layer 25 are sequentially formed.

[0005] Next, oxygen is ion-implanted into a portion of the laminate thus formed other than a portion to be an active region of the HEMT to form an inter-element isolation region (not shown).

Next, an ohmic electrode 27 is formed on a predetermined portion of the n ⁺ GaAs layer 25 by a known method, and thereafter, a part of the n ⁺ GaAs layer 25 and a part of the n-GaAs layer 23 are formed on the surface of the n ⁺ GaAs layer. A predetermined depth is removed from the recess 29 to form a recess 29. Further, a gate electrode 31 is formed in the recess 29 by a lithography technique and a lift-off technique. HEM by controlling the depth of the recess 29
The threshold voltage for turning T on and off can be determined.

Next, although not described in the above-mentioned literature, a multilayer wiring technique is used. For example, an input terminal is connected to the gate electrode 29, a ground terminal is connected to one ohmic electrode 27, and a ground terminal is connected to the other ohmic electrode 27. These terminals are formed such that the power supply terminal is connected to the output terminal to one of the ohmic electrodes, and the HEMT is obtained.

In order to improve the operation speed of a logic circuit formed using the HEMT formed as described above, HE
It is effective to reduce the gate length of the MT. Therefore, the above H
In EMT, the gate length was reduced to 0.25 μm.

[0009]

However, according to the conventional manufacturing method, the semi-finished product of the semiconductor device in which the input terminal, the output terminal, the power supply terminal and the ground terminal have been formed, is manufactured in a state where these terminals are not connected to each other. Sent to the process. This is because each terminal usually needs to be electrically independent in order to operate the semiconductor element. For this reason, if electric charges are accumulated in the input terminal, the output terminal, and / or the power supply terminal for some reason in a later process (static electricity is generated), the electric charges are discharged between the terminals through the active region of the semiconductor element. There has been a problem that the semiconductor element may be destroyed by the electric charge. In particular, when charge is accumulated for some reason in a terminal (for example, an input terminal) connected to the gate electrode, the charge flows to the ground terminal through the gate electrode and the active region. There has been a problem that the semiconductor element is destroyed during manufacture, in combination with the reduced breakdown voltage of the electrostatic breakdown due to the reduced area.

The electrostatic breakdown of the HEMT is caused not only by the charge at the terminal connected to the gate electrode but also by the charge accumulated at other terminals. This is because the area of the active region and the ohmic electrode is reduced due to the principle of the proportional reduction rule with the reduction of the gate length, and the breakdown voltage of these is reduced.

Further, the above-mentioned electrostatic breakdown is caused by the above-mentioned HEM.
Since it can occur not only in the manufacturing process of T but also in the manufacturing process of other various semiconductor elements, improvement is desired.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device which is less likely to cause electrostatic breakdown in a process of manufacturing the semiconductor device, and to use the method for implementing the method. It is to provide a suitable thing.

[0013]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which is used to manufacture a semiconductor device such as a field effect transistor. A predetermined plurality of terminals including one or more terminals each having one end connected thereto and electrically independent of each other, such as an input terminal, an output terminal, a power supply terminal, a ground terminal, and the like. The semiconductor device is manufactured in a state where the terminals are connected to each other during the manufacturing of the semiconductor device.

In practicing the present invention, the predetermined terminals are connected to each other by (A) connecting the other end of each of the predetermined terminals to a position separated from the active region of the semiconductor base. Forming a conductive connection region,
A plurality of normally-on type switch portions for dividing the connection region into a plurality of portions corresponding to the predetermined number of terminals are formed in the connection region, and thereafter, the divided portions of the connection region are formed; This is characterized in that the above-mentioned predetermined terminals are formed over each of the active regions.

(B) Alternatively, a connection region having conductivity for connecting the other end of each of the above-mentioned predetermined terminals to a semiconductor base and a part of which is connected to the above-mentioned active region is formed. And forming the predetermined terminal so that the other end of the predetermined terminal is connected to the connection region. After the formation of the semiconductor element, a disconnection process between the active region and the wiring region is performed. In addition, a process for dividing the wiring area so that the predetermined terminals are electrically independent is performed.

The second invention of this application, which is used for carrying out the method of the first invention, comprises a semiconductor base, an active region for the semiconductor device, and various terminals connected to the semiconductor device. A connection region to which a part of the connection region is connected and a connection region having conductivity, and a plurality of connection regions for dividing the connection region into a plurality of regions corresponding to at least the various numbers of terminals. A plurality of normally-on type switch units.

[0017]

According to the first aspect of the present invention, a semi-finished product on which predetermined terminals such as an input terminal, an output terminal, a power supply terminal and a ground terminal have been formed is obtained in a state where these terminals are directly connected to the ground terminal. , Followed by a subsequent manufacturing process. Therefore,
Even if electric charges are accumulated in the terminals in some later process for some reason, the electric charges flow directly to the ground terminal without passing through the active region.

A conductive connection region for connecting the other end of each of predetermined terminals such as an input terminal, an output terminal, a power supply terminal and a ground terminal is formed at a position separated from the active region under the semiconductor base, and A plurality of normally-on type switch portions for dividing the connection region into a plurality of portions corresponding to the predetermined number of terminals are formed in the connection region, and thereafter, for each of the divided portions of the connection region, According to the configuration in which the above-mentioned predetermined terminal is formed over the above-mentioned active area, since the switch section that divides the connection area is a normally-on type, the divided portions of the connection area are usually electrically connected to each other. It has been done. For this reason, when the other end of the predetermined terminal is connected to this connection area, these terminals are normally connected to each other. Further, when the semiconductor element is normally operated after the manufacture of the semiconductor element is completed, the switch section is operated. As a result, the divided portions of the connection region are electrically separated, and the various terminals are electrically independent.

An input terminal, an output terminal,
A conductive connection region for connecting the other end of each of the predetermined terminals such as a power supply terminal and a ground terminal, a part of which forms a connection region connected to the active region, and the predetermined terminal Is formed by forming the predetermined terminal so that the other end of the semiconductor device is connected to the connection region. After forming the semiconductor element, the active region is separated from the wiring region, and the wiring region is formed. According to the configuration for performing the process of dividing the above-described predetermined terminals so that the predetermined terminals are electrically independent, the respective terminals can be connected to each other during the manufacturing process, and the respective terminals are electrically independent after the product is manufactured. .

According to the second aspect of the present invention,
After the various terminals are formed, these terminals are connected to each other unless the normally-on switch unit is operated, so that the method of the first invention can be easily implemented. Needless to say, the semiconductor element can be used only by operating the normally-on type switch section.

[0021]

Embodiments of the present invention will be described below with reference to the accompanying drawings. The embodiment of the second invention will be described together with the first embodiment of the first invention. Further, the drawings used in the description schematically show the dimensions, shapes, and arrangement relations of the components so that the present invention can be understood. The following embodiment is an example in which the present invention is applied to the manufacture of a field effect transistor (FET) having a recess gate.

<First Embodiment> First, a first embodiment of the first invention will be described. 2 (A) and (B), FIG.
(A) and (B) and FIG. 1 are manufacturing process diagrams for explanation thereof. Each of the figures is a plan view of the element in the manufacturing process as viewed from above the semiconductor base main surface.

First, a semi-insulating GaAs substrate (not shown)
For example, an n-GaAs layer (not shown) for a channel layer having a predetermined impurity concentration and an n ⁺ GaAs layer for mainly reducing ohmic contact resistance are sequentially formed by MBE to form a semiconductor substrate of the embodiment. Get 41.

Next, after the active region formation region and the connection region formation region of the semiconductor base 41 are respectively covered with a suitable mask material (not shown), the semiconductor base 4 is formed.
1 is ion-implanted with oxygen. Thereby, the semiconductor base 4
1, active areas 43a, 43b and active areas 43a, 4
A connection region 45 having a planar shape surrounding the area 3b in a substantially “R” shape, and an element isolation region 47 for electrically isolating them.
(FIG. 2A). As described above, the connection region 45 according to the present invention can be easily obtained by using a part of the n ⁺ GaAs layer formed for reducing the ohmic contact resistance, which is advantageous in the process. In this embodiment, two active regions 43a, 4a
3b, and one FET is formed thereon. However, this is exemplary. It should be understood that the number of active areas can be varied by design.

Next, an ohmic electrode 49 for the FET is connected to an ohmic electrode formation region (source / drain formation region) of each of the active regions 43a and 43b. Ohmic electrodes 51 for these terminals are formed on the portions by a known method (FIG. 2B).

Next, a gate electrode recess (not shown) is formed in a region where the gate electrode is to be formed in the active regions 43a and 43b.
Further, a recess (not shown) for forming a switch portion is formed in a portion of the connection region 45 between the portion where each of the ohmic electrodes 51 is formed, and the corresponding region of the semiconductor base is etched by a predetermined amount. ,Form. Here, the respective predetermined amounts include both cases where they are the same or different. Next, a metal film capable of forming a Schottky junction with the semiconductor base is formed in these recesses. By this. FET
Gate electrode 53 and switch portions 55a to 55d are obtained (FIG. 3A). By controlling the depth of the recess, F
The threshold voltage of the ET and the switch unit can be controlled. In this embodiment, the FET and the switch units 55a to 55a
The etching amount at the time of forming the recess was controlled so that 5d operates in the depletion mode (normally-on type). When the formation of the switch parts 55a to 55d is completed,
The connection area 45 is formed by the switches 55a to 55b.
It is divided into four parts 45a to 45d (FIG. 3)
(A)). However, since each of the switch sections 55a to 55d is a normally-on type, a normal state (switch section 55
No voltage is applied to the Schottky electrodes a to 55d)
Then, these four portions 45a to 45d are in an electrically conductive state.

Next, as shown in FIG. 3B, an interlayer insulating film 57 is formed on the sample by a known method, and further, contact holes 59 are formed in predetermined portions of the interlayer insulating film 57, respectively. . Here, the predetermined location is the one shown in FIG.
The gate electrode 53 and the ohmic electrode 49 shown in FIG.
Reference numeral 51 denotes an interlayer insulating film portion corresponding to a portion of each of the switch portions 55a to 55d to which input terminals and the like are to be connected.

Next, in the case of this embodiment, as shown in FIG. 1, a part 45b of the connection area (switch parts 55a and 55b
FE between the drain region and the connection region portion sandwiched between
The power supply terminal 61 for T, the output terminal 63 for FET between the connection region 45c, 45a and the source region, the terminal 63 also serves as a ground terminal, the portion 45d of the connection region and the gate electrode. An input terminal 65 for the FET is formed between the switching unit 53 and the wiring 53, and a wiring 67 for connecting the switching terminals 55a to 55d is formed by a known wiring forming technique. As a result, the power supply terminal 61, the ground / output terminal 63, and the input terminal 65 each have one end connected to the active regions 43a and 43b of the FET and the other end divided by the switch portions 55a to 55d of the connection region 45. 45a-45
d and connected.

Thereafter, although not shown, a passivation film is formed, and portions of the passivation film corresponding to the power supply terminal 61, the ground / output terminal 63, the input terminal 65, and the pad portion of each switch connection wiring 67. Then, a hole is formed for wire bonding to obtain an FET.

In the FET manufactured as described above, since the switch portions 55a to 55d are of the depletion type, all portions 45a to 45d of the connection region 45 are connected when no voltage is applied to the switch connection wires 67. Becomes
Therefore, the power terminal 61, the ground / output terminal 63, and the input terminal 65 are connected to each other. For this reason, even if charges are accumulated in each terminal in a later step, the charges flow directly to the ground terminal. Therefore, destruction of the active region and the gate electrode due to static electricity is less likely to occur than before. On the other hand, when a negative voltage is applied to each switch connection wiring 67, no current flows in a portion of the connection region 45 where each switch is provided at a certain voltage (threshold voltage). Since 45a to 45d are electrically independent, a power supply terminal 61,
The grounding / output terminal 63 and the input terminal 65 are also electrically independent from each other, so that the FET can operate normally.

Also, a semiconductor base 41 has a connection region 45 to which active regions 43a and 43b for semiconductor elements and a part of each of various terminals 61, 63 and 65 connected to the semiconductor element are connected. And a connection region 45 having conductivity. The connection region 45 is provided with a plurality of regions 45 a to 4 corresponding to at least various types of terminals.
A wafer including a plurality of normally-on type switch portions 55a to 55d for dividing into 5d (FIG. 3A)
reference. According to the second aspect of the present invention, it can be seen that various terminals can be easily connected in a later step, and the semiconductor element can be put into a use state only by operating a normally-on type switch section. .

In the above-described embodiment, the active region 43a, 43b and the connection region 45 are separated from each other by the element isolation region 4.
7, a method of electrically separating in advance was used (see FIG. 2A). However, as shown in FIG.
The active regions 43a and 43b and the connection region 45 are connected in advance, and normally-on type switch portions 55x and 55y are formed at the connection portions as shown in FIG. 4B. The active area and the connection area may be divided by 55x and 55y. Switch part 5
5x and 55y may be manufactured at the same time when the switch parts 55a to 55d are manufactured. With the miniaturization of the semiconductor element, the active region is also miniaturized and the electrostatic breakdown of the active region is easily caused. However, if the structure as described with reference to FIG. 4 is used, the area of the active region becomes the connection region during the manufacturing process. Therefore, an advantage can be expected that electrostatic breakdown is less likely to occur since the area becomes larger by the connection.

In the above-described embodiment, the switch sections 55a to 55y for dividing the connection area 45 are of a normally-on type. However, even if these switch units are normally-off type (enhancement type), the same effect as in the embodiment can be obtained in principle. However, in the case where the switch section is constituted by a normally-off type, after forming the various terminals, it is necessary to carry out the post-process work in a state where a voltage is applied to the various terminal connection wirings 67 (see FIG. 1). Disadvantageous.

<Second Embodiment> Next, a second embodiment of the first invention will be described. The main difference between the second embodiment and the first embodiment is that the switch units 55a to 55y are not used. 5 (A) and 5 (B), FIGS. 6 (A) and 6 (B), and FIGS. 7 (A) and 7 (B) are process diagrams for explanation thereof. Each drawing is shown by a plan view at a position similar to that of the first embodiment.

First, a semiconductor underlayer 41 is formed in the same procedure as in the first embodiment, and active regions 43a and 43b, a connection region 45, and an element isolation region 47 are formed on the semiconductor underlayer 41. However, in this example, the active areas 43a, 43
3b and the connection region 45 are partially connected (the portion indicated by S in FIG. 5A) (FIG. 5A). This is to make it difficult for electrostatic breakdown of the active region to occur as in the modification of the first embodiment (see FIG. 4). Of course, as in the first embodiment, the active regions 43a and 43b and the connection region 45 may be completely separated (see FIG. 2A).

Next, an ohmic electrode 49 for the FET is formed in each of the active regions 43a and 43b in the region where the ohmic electrode is to be formed (the region where the source / drain is to be formed). Ohmic electrodes 51 for these terminals are formed on the portions to be connected in the same procedure as in the first embodiment (FIG. 5B).

Next, in the second embodiment, the active area 43
Gate electrode recesses (not shown) are formed only in the gate electrode formation regions a and 43b. The depth of the recess may be determined depending on whether the FET is a depression type or an enhancement type. Next, a metal film capable of forming a Schottky junction with the semiconductor base is formed in the gate recess. Thus, a gate electrode 53 of the FET is obtained (FIG. 6A).

Next, as in the first embodiment, the interlayer insulating film 57 is formed.
Are formed, and contact holes 59 are formed at predetermined positions of the interlayer insulating film 57 (FIG. 6).
(B)).

Next, an FET power supply terminal 61, an FET output terminal (this terminal also serves as a ground terminal) 63, F
The ET input terminals 65 are formed in the same manner as in the first embodiment. Each of these terminals 61, 63, 65 is connected to connection region 4
5 (FIG. 7A).

Next, although not shown, a passivation film is formed, and a hole for wire bonding is formed in a portion of the passivation film corresponding to the pad portion of the power supply terminal 61, the ground / output terminal 63, and the input terminal 65. Do.

Next, the terminals 61, 63, and 65 remain connected by the connection region 45.
Since it cannot be used as ET, the active regions 43a, 43b
And the connection region 45 (FIG. 5A).
And the terminals 61, 6 of the connection region 45.
In this embodiment, oxygen is ion-implanted into portions other than the portions to which the connection regions 3 and 65 are connected, and the active regions 43a and 43b are electrically separated from the connection region 45.
1, 63, 65 are made electrically independent. Thereby, an FET is obtained.

In the above, the embodiments of the first and second inventions of the present application have been described. However, these inventions are not limited to the above-described embodiments, and the following modifications can be added. .

In each of the above-described embodiments, the planar shape of the connection region 45 has a substantially "square" shape surrounding the active region.
However, the planar shape is not limited to this, and can be any shape according to the design of the semiconductor element.

In the above embodiment, the GaAs-FET
Is an example in which the method of the present invention is applied to the formation of a semiconductor device. However, it is clear that the manufacturing method of the present invention can be widely used for manufacturing semiconductor devices other than GaAs-FETs.

The structure of the connection area 45 and the switch section 5
The configurations of 5a to 55y are not limited to those of the embodiment, but may be other configurations as long as similar effects can be obtained.

[0046]

As is clear from the above description, according to the first invention of this application, a semi-finished product having predetermined terminals such as an input terminal, an output terminal, a power supply terminal, and a ground terminal is formed. Terminal is directly connected to the ground terminal,
Since the electric charge is sent to the subsequent manufacturing process, even if electric charge is accumulated in the terminal for some reason in the subsequent process, the electric charge flows directly to the ground terminal without passing through the active region. For this reason,
Electrostatic breakdown of the gate electrode and the active region is less likely to occur than in a case where each terminal is not directly connected.

The other end of each of predetermined terminals such as an input terminal, an output terminal, a power supply terminal, and a ground terminal is connected by a connection region, and the connection region is connected to a normally-on type for each portion to which the predetermined terminal is connected. In the case of the configuration divided by the switch unit, the predetermined terminals are usually connected to each other via the connection area, and are electrically independent by operating the switch unit. Therefore, when the semiconductor element is not operating, the semiconductor element can always be protected from static electricity.

According to the second invention of this application,
After the formation of various terminals, these terminals are connected to each other unless a normally-on switch is operated. After the semiconductor element is formed, the element can be operated normally by applying a voltage to each switch section. Thus, the method of the first invention can be easily implemented.

[Brief description of the drawings]

FIG. 1 is a diagram provided for explanation of a first invention and a second invention.

FIGS. 2A and 2B are process diagrams for explaining a first embodiment of the first invention.

FIGS. 3A and 3B are process drawings following FIG. 2 for explaining the first embodiment of the first invention; FIGS.

FIGS. 4A and 4B are explanatory views of a modified example of the first embodiment of the first invention.

FIGS. 5A and 5B are process diagrams for explaining a second embodiment of the first invention.

FIGS. 6A and 6B are process diagrams following FIG. 5 for describing a second embodiment of the first invention.

FIGS. 7A and 7B are process diagrams following FIG. 6 for describing a second embodiment of the first invention.

FIG. 8 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

41: Semiconductor base 43a, 43b: Active area 45: Connection area for connecting various terminals 45a to 45d: Part of connection area 47: Inter-element isolation area 49: Ohmic electrode 53: Gate electrode 55a to 55d: Connection area 61: Power supply terminal 63: Output terminal (also used as ground terminal) 65: Input terminal 67: Wiring for connection of each switch

──────────────────────────────────────────────────の Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/778 29/812 (56) References JP-A-2-280321 (JP, A) JP-A-2-118515 (JP, A) JP-A-4-122056 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/095 H01L 21/338 H01L 21/822 H01L 23/60 H01L 27/04 H01L 29/778 H01L 29/812

Claims (2)

(57) [Claims] 1. A plurality of predetermined terminals including a ground terminal, selected from various terminals having one end connected to an active region of a semiconductor element and being electrically independent of each other. A method of manufacturing a semiconductor device, wherein the semiconductor device is manufactured while the semiconductor device is connected to each other during the manufacturing of the semiconductor device, wherein the semiconductor device is a field-effect transistor, and the various terminals are input terminals of the field-effect transistor. , An output terminal, a power supply terminal, and a ground terminal. 2. The semiconductor device according to claim 1, further comprising an active region for the semiconductor element and a conductive connection area to which a part of each of various terminals connected to the semiconductor element is connected. Comprising, in the connection region, a plurality of normally-on type switch portions for dividing the connection region into a plurality of regions corresponding to at least the various terminal numbers, wherein the semiconductor element is a field-effect transistor; 3. The method according to claim 1, wherein the various terminals are an input terminal, an output terminal, a power supply terminal, and a ground terminal of the field effect transistor.