JP3000779B2 - Information collection method of processor execution status - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for collecting information for software debugging in an information processing apparatus. In an information processing apparatus, it is necessary to debug the software at any time in order to check whether software to be used is compatible with the apparatus. As a method of debugging the software, there is a method of tracing the running address of a program. In particular, it is useful for debugging if a device actually operated has this function.

However, in recent years, when the prefetching of instructions is performed due to the advance of the architecture of the information processing apparatus, it becomes difficult to correspond the instruction fetch (acquisition) address appearing on the memory path to the execution address of the processor.
Further, in a processing device in which a cache memory (a partial copy of the main memory) is integrated in one chip due to advances in semiconductor technology, accesses hitting the built-in cache memory do not appear to the outside. Is almost impossible.

[0003] There is also a method of generating information by software by generating a debug trap every time one instruction is executed or each time a branch instruction is executed. However, there is no method for collecting information in real time in an actual operation state. It has become necessary to trace the running address of the program.

[0004]

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional information collecting method in an execution state of an information processing apparatus. In the figure, 21 is a processor (CPU), 22 is a main storage device (M
M) and 23 are input / output control devices (IOC), 24 is a trace control device, 25 is an address bus, 26 is a data bus, and 27 is a control signal line. A disk device (H
D), magnetic tape (MT), console (keyboard,
Input / output device such as a display) is connected.

Various control signals are sent from the processor 21 to a main storage device 22 and an input / output control device 23 via a control signal line 27, and an address signal is sent to the main storage device 22 via an address bus 25.
The data signal is sent to the input / output control device 23 and the trace memory 24, and a data bus is used to send and receive data signals to and from these devices. The trace control unit 24 is composed of a RAM and a control unit, receives all address signals and data signals from the processor 21, traces the received contents, and can take out the received contents by control signals.

The CPU 21 sends an address command to be executed to the MM 22, and data representing the command is output from the MM 22.
The data output from the MM 22 is fetched by the CPU 21 to execute an instruction for an input / output device or a memory or an instruction for an operation. These instruction addresses and data are transmitted and received via the address bus 25 and the data bus 26.
The trace memory 24 can monitor these buses and trace (accumulate) address instructions and data.

[0007]

However, if prefetching of an instruction from the CPU is performed, it becomes difficult to correspond the instruction fetch address and the execution address appearing on the memory bus.
Also, a CPU in which cache memory is integrated in one chip
In this case, since the access hitting the internal cache does not appear to the outside, it is impossible to trace the running address. Therefore, there is no method for collecting information in real time in an actual operation state.

An object of the present invention is to develop a means for real-time information collection of an actual operation state in a system in which execution state information cannot be collected by monitoring a bus due to prefetching of an instruction or a built-in cache memory. Aim.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 1 is a first processor for a normal mode, 2 is a main storage device, 3 is an input / output control device, 8 is a second processor for a trace mode, 4 is a trace memory, 5 is an address bus, and 6 is an address bus. The data bus 7 indicates a control signal line. The first processor 1 for the normal mode and the second processor 8 for the trace mode are one-chip integrated circuits having the same configuration, and are processing devices that perform the same internal operation.

The first processor 1 is set to the normal mode and performs data processing. The second processor 8 is set to the trace mode, and the internal operation is the same as that of the first processor 1 and outputs execution address information instead of an output signal such as a control signal. The execution address information is stored in the trace memory 4. The contents of the trace memory 4 are read from the first processor 1 or from a dedicated console or the like by means not shown.

[0011]

A normal mode and a trace mode are provided for setting a processor, and the mode is set externally by, for example, the potential of a terminal. In trace mode,
The processor performs the same data processing as in the normal mode based on the input signal, and switches the output terminal used for external control or the like in the normal mode for outputting the address being executed and the latch timing. The input / output terminal is in a high impedance state in the output mode.

A signal line connected to the input terminal and the input / output terminal of the processor 1 in the normal mode is connected to the input terminal and the input / output terminal of the processor 8 in the trace mode. Processor 1
Are arranged in parallel, and the processor 1 in the normal mode outputs the result of the data processing, and at the same time, the processor 8 in the trace mode outputs the execution address. Collection becomes possible.

[0013] It is assumed that the processor is configured to eliminate internal indeterminate elements that affect the operation by resetting.

[0014]

2 and 3 show an embodiment of a block diagram of a processor according to the present invention. The embodiment (part 1) of FIG. 2 shows a case where a trace memory is connected to the outside, and the other embodiment (part 2) of FIG. 3 shows a case where a trace memory is built-in. In the figure, 11 is a processor (CPU), 12 is an instruction control unit (IU), 13 is an instruction execution unit (EU), 14 is a memory access control unit (SU), and 15 is a bus access control unit (B
U) and 16 indicate a cache memory (CM), and 17 indicates a trace memory (TM).

In the embodiment of FIG. 2 (part 1), the bus access control unit 15 has a selector (SEL), and the selector selects a normal mode or a trace mode by a mode switching signal. Memory access control unit in normal mode
14 is selected, and in the case of the trace mode, the internal information i from the program counter (PC) of the instruction control unit 12 is selected, and the control signal is connected to an external trace memory to send the latch timing. Together with the execution address.

The instruction execution unit 13 comprises an operation unit (AU) and a register set (R).
Command, and the memory access control unit 14
The instruction from the instruction execution unit 13 accesses the cache memory 16 and the bus access control unit 15 accesses the main memory via the bus. Therefore, the execution address is the same in both the normal mode and the trace mode.

In another embodiment (part 2) of FIG. 3, the trace memory 17 is built in the processor 11, and the internal information i from the program counter (PC) of the instruction control unit 12 is always stored. By controlling the bus access control unit 15 with the output instruction signal DUMP, the internal information stored in the trace memory 17 can be output. The output instruction can be given by software. Note that the portion within the dotted line can be mounted with a piggyback (double chip mounted).

[0018]

According to the present invention, a means for collecting information on an actual operation state in real time can be obtained for a system in which execution state information cannot be collected by monitoring a bus, due to an instruction prefetch for instruction prefetching and a built-in cache memory. .

[Brief description of the drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention.

FIG. 2 is a block diagram of an embodiment (part 1);

FIG. 3 is a block diagram of an embodiment (part 2);

FIG. 4 is a block diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 First processor 2, 22 Main storage device 3, 23 I / O controller 4, 24, 17 Trace memory 5, 25 Address bus 6, 26 Data bus 7, 27 Control signal line 8 Second processor 11, 21 Processor 12 Instruction control unit 13 Instruction execution unit 14 Memory access control unit 15 Bus access control unit 16 Cache memory

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hisamitsu Yanahira 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Co., Ltd. 56) References JP-A-3-129440 (JP, A) JP-A-2-310738 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 11/28 310 G06F 11 / 34

Claims (2)

(57) [Claims] A first processor for a normal mode (1)
And between the main storage device (2) and the input / output control device (3)
In an information processing apparatus which performs an information processing operation by being connected to an address bus (5), a data bus (6) and a control signal line (7), one chip having the same configuration as the first processor (1) for the normal mode And a trace memory (4) connected to the second processor (8) for performing the same internal operation in the integrated circuit of the first processor (1). ) Is set to the normal mode to perform data processing, the second processor (8) is set to the trace mode, and the internal operation of the second processor (8) is the same as that of the first processor (1). A method for collecting execution state information of a processor, comprising outputting execution address information instead of an output signal such as a control signal, and storing the execution address information in a trace memory (4). 2. In the information processing apparatus, a trace memory (4) connected to the second processor (8) is provided in a chip of the second processor (8). A method for collecting information on the execution state of a processor, wherein an instruction to output information stored in the processor is issued by an external control signal.