JP3000926B2 - Switch configuration method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a switch configuration method, and more particularly to a switch configuration method using a bit slice configuration.

[0002]

2. Description of the Related Art Japanese Patent Laid-Open No.
There is an invention of a space division switch described in JP-A-8891. The invention described in the above publication aims to easily increase the switch capacity even when high-speed data is input, and to provide a unit switch having a switch size of n × n. A method for realizing a large-sized switch by connecting a plurality of switches in a matrix is shown. For example, it is shown that when a number of n × n switches are connected in a matrix in a row direction and b in a column direction, a (a × n) × (b × n) switch can be formed. .

Although not related to the invention described in the above publication, a general technique for handling high-speed signals is to parallel develop high-speed signals to a speed at which a device (such as an LSI) can process the signals. There is technology. Further, when the number of parallel expansions is large and the number of input / output terminals of the device is insufficient, or when the processing circuit scale is larger than the device scale, there is a technique of performing processing by a plurality of devices by a bit slice configuration.

FIG. 16 is a block diagram showing an N × N switch having a bit slice configuration in a conventional example.

The configuration shown in FIG. 16 will be described. The input signal # 1 is an m-bit parallel signal and is input to S110.
The first set of k-bit signals is input from S111 to the input port 1 of the first unit switch 101, and the second set of k-bit signals is input from S112 to the input port 1 of the second unit switch 102. And so on,
The k-bit signal of the last (m / k) group is input to the input port 1 of the (m / k) -th unit switch 103 from S113. Similarly, the input signal # 2 is input to S120, and is input to the input ports 2 of the unit switches 101 to 103 from S121 to S123 in order of k bits. Similarly, the input signal #N is also input to S130, and the unit switch 10 is sequentially switched from S131 to S133 in k bit order.
It is input to input ports N of 1 to 103.

The connection of the output ports of the unit switches is symmetrical to the connection of the input ports, and the output signal # 1 is a signal S140 obtained by collecting the signals S141 to S143 output from the output ports 1 of the unit switches 101 to 103. Becomes
The output signal # 2 is a signal S150 obtained by collecting the signals S151 to S153 output from the output ports 2 of the unit switches 101 to 103. Similarly, the output signal #N becomes a signal S160 obtained by collecting the signals S161 to S163 output from the output ports N of the unit switches 101 to 103.

In the configuration shown in FIG. 16, each input / output signal of m bits parallel is connected to the input / output port of each unit switch for each k bits.
A plurality of bit sets are not connected to one unit switch. That is, a k-bit signal is sent from the input signal # 1 to the input port of the unit switch 101 at S11.
Input only from 1. Therefore, in the configuration shown in FIG. 16, for example, when used as a 2 × 2 switch, the number of unit switches remains unchanged at (m / k).
Of the N input / output ports of each unit switch, only the input / output ports 1 and 2 are used, and the other input / output ports are unused.

Next, the operation of FIG. 16 will be described. When outputting the data of the input signal # 1 to the output signal # 2, S1
10 is bit sliced and input to each of the unit switches 101 to 103 as signals of S111 to S113.
S110 has “2” indicating the output destination as switch control information indicating the output destination. Based on this switch control information, the unit switches 101 to 103 connect the input port 1 and the output port 2 with each other. , And S111 is S
151 is output to S152, and S112 is output to S152.
113 is output to S153. Therefore, the data of the input signal # 1 input from S110 is output from S150 to become the output signal # 2. The same processing is performed in the unit switches 101 to 103 even when the input / output signal is another signal.

FIG. 17 is a block diagram showing a configuration example of an output buffer type switch used in the ATM communication system in a conventional example, and shows a circuit of a unit switch constituting an 8 × 8 switch.

The configuration of FIG. 17 will be described. The input / output of the cell multiplexing circuit 709 is 8 inputs and 1 output with a 2-bit width. The input signals # 1 to # 8 are 2-bit parallel signals, and are input from S711 to S718 to the input ports 1 to 8 of the cell multiplexing circuit 709, respectively. The output signal S720 of the cell multiplexing circuit 709 is wired in the form of a bus S721, and the bus S721 and the cell buffers 701 to 708
They are connected using 2-bit parallel signals S731 to S738, respectively. 2 from the cell buffers 701 to 708
Bit parallel signals S741 to S748 are output, respectively, and become output signals # 1 to # 8.

Next, the operation of FIG. 17 will be described. Each of the eight input signals # 1 to # 8 has a 2-bit width, and
The signal 718 is input to the cell multiplexing circuit 709, and the cell multiplexing circuit 709 multiplexes the cells and outputs the result as S720. The output signal S720 of the cell multiplexing circuit 709 is transferred to a bus S721.
And the output signal of the bus S721 is transmitted to the cell buffer 7 by two-bit parallel signals S731 to S739.
01 to 708, respectively. Cell buffer 701
The control unit (not shown) for controlling writing and reading of 〜 to 708 gives write permission to the corresponding output destination cell buffer in accordance with the switch control information of each input data, thereby achieving expected output. Signal # 1
To # 8.

[0012]

In the above prior art,
It has been shown that the switch size can be increased by connecting a plurality of unit switches in a matrix, but a method of using the unit switches as switches smaller than the switch size is not shown. There is a problem.

To put it simply, the unit switch is 8 × 8
In this case, it is possible to use only a part of the input / output ports and use it as a small-scale switch of 2 × 2, 4 × 4, or the like. However, in this case, the cost of these small switches is the same as 8 × 8 switches.

Further, if the number of unit switches is small and the number of switches is large, the cost can be improved when the switches are used as small-scale switches. In this case, there is a problem that the cost increases.

For example, when the number of cross points is compared between the 2 × 2 switch and the 8 × 8 switch, the number is 4 for the 2 × 2 switch and 64 for the 8 × 8 switch. For this reason, the number of cross points of the 2 × 2 switch is 1/16 as compared with the case of the 8 × 8 switch, but the manufacturing cost is not 1/16 but a larger value. Therefore, if 16 2 × 2 unit switches are used, 8 ×
Although eight switches can be configured, the cost is higher than when the unit switches are 8 × 8.

An object of the present invention is to solve the above problems and to provide a switch configuration method capable of reducing the cost when the unit switch is applied to a small-scale switch.

[0017]

In order to achieve the above object, according to a switch configuration method of the present invention, an N × N switch is composed of a plurality of unit switches by a bit slice configuration.
When a switch smaller than × N is configured, the number of unit switches used is reduced and a plurality of physical input ports are treated as one logical input port.

For example, when an N × N unit switch is composed of four unit switches, (N / 2) ×
When configuring the (N / 2) switch, two unit switches are used to group N input / output ports by two, and used as a switch having (N / 2) logical ports.

The details are as follows.

(1) N (N: an integer satisfying N ≧ 2) input signals are each subjected to m (m: an integer satisfying m ≧ 2) bit parallel expansion, and the m-bit parallel expanded input signal is Are divided into (m / k) groups of k (k: an integer that satisfies k ≧ 2 and a divisor of m) bits, and the k-bit parallel signal is processed as a set of input / output signals (m / k). k) unit switch circuits have (m /
k) The signals of k bits divided into k groups are input and processed in parallel, and the signals of k bits are output from the (m / k) unit switch circuits.
In the case of an N × N switch having a bit slice configuration having N output sides and a switch size of N × N, (m / k) unit switch circuits are used and a
(A: an integer satisfying 1 ≦ a ≦ N).
(B: an integer satisfying 1 ≦ b ≦ m / k) The k-bit signal of the group is input to the a-th logical input port of the b-th unit switch circuit, and the switch size is set to (N /
s) × (N / s) (s: an integer satisfying s ≧ 2 and a divisor of N), the unit switch circuit is set to (m /
(S × k)) signals, and the c (c: an integer satisfying 1 ≦ c ≦ N / s) th signal is (s × (d−1) + t) (d:
Integer satisfying 1 ≦ d ≦ m / (s × k), t: 1 ≦ t ≦ s
The k-bit signal of the (th integer satisfying −1) th group is input to the tth logical input port of the dth unit switch circuit.

(2) At this time, when the switch size is (N /
s) × (N / s), the unit switch circuit having N input / output ports performs grouping of N input / output ports by s and (N / s) A logical input / output port is provided, and each input / output signal of the logical input / output port can operate as a switch circuit having a (k × s) bit width.

(3) The switch size is (N / s)
× (N / s), e (e: 1 ≦ e ≦ N / s
An e-th input signal in order to output a signal input from the (th integer that satisfies) th logical input port to the f-th (integer that satisfies f: 1 ≦ f ≦ N / s) th logical output port Is connected to the s physical output ports from which the f-th output signal is output in a one-to-one manner, so that s physical input ports of the unit switch circuit to which
The switch control information indicating the output destination of the e-th input signal attached to the e-th input signal is converted in advance, and the unit switch circuit is attached to the input signal input from each of the physical input ports. It can operate as an N × N switch that distributes the input signal according to the switch control information to be performed.

In this way, when a switch smaller than N × N is configured, it can be realized in a scale corresponding to the switch size, and the number of unit switches can be reduced. Costs can be reduced.

[0024]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

[1] Description of Configuration First, the configuration of an embodiment of the present invention will be described.

FIG. 1 is a block diagram showing a switch configuration to which the switch configuration method of the present invention is applied. As shown in FIG. 1, an N × N bit width per port is k bits.
An (N / s) × (N / s) switch is configured by using (m / (s × k)) unit switches 1, 2, and 3.

The input signal # 1 is an m-bit parallel signal and is input to S10. The first set of k-bit signals is input from S11 to the input port 1 of the first unit switch 1, and the second set of k-bit signals is S12.
Is input to the input port 2 of the unit switch 1. Similarly, the s-th set of k-bit signals is input to the input port s of the unit switch 1 from S13. The next (s +
1) The k-bit signal of the set is input from S14 to the input port 1 of the second unit switch 2, and the (s + 2) -th set of k-bit signals is input from S15 to the input port 2 of the unit switch 2. . Similarly, the 2s-th set of k-bit signals is input to the input port s of the unit switch 2 from S16. In the same manner, input in the same order, and enter the last (m
/ K) The k-bit signal of the set is converted from S19 to (m / (s ×
k)) is input to the input port s of the unit switch 3.

The input signal # 2 is also an m-bit parallel signal and is input to S20. The first set of k-bit signals is input from S21 to the input port (s + 1) of the unit switch 1, and the second set of k-bit signals is S2.
2 is input to the input port (s + 2) of the unit switch 1. Similarly, the s-th set of k-bit signals is S2
3 is input to the input port 2s of the unit switch 1.
The k-bit signal of the next (s + 1) -th set is input from S24 to the input port (s + 1) of the unit switch 2, and (s +
2) The k-bit signal of the set is changed from S25 to the unit switch 2
Is input to the input port (s + 2). Similarly, the 2s-th k-bit signal is input to the input port 2s of the unit switch 2 from S26. Thereafter, the signals are sequentially input in the same manner, and the k-bit signal of the last (m / k) group is input from S29 to the input port 2s of the (m / (s × k))-th unit switch 3.

Similarly, from the input signal # 3 to the input signal # (N / s-1), they are sequentially input to the input ports of the (m / (s × k)) unit switches 1 to 3.

Finally, the input signal # (N / s) is input from S30. The first set of k-bit signals is input from S31 to the input port (N-s + 1) of the unit switch 1, and
The second set of k-bit signals is input from S32 to the input port (Ns + 2) of the unit switch 1. Similarly, the s-th set of k-bit signals is input to the input port N of the unit switch 1 from S33. The next (s + 1) -th set of k-bit signals is input from S34 to the input port (N-s + 1) of the unit switch 2, and the (s + 2) -th set of k-bit signals is input from S35 to the input port (N-s) of the unit switch 2. N
−s + 2). Similarly, the 2s-th set of k-bit signals is input to the input port N of the unit switch 2 from S36. Thereafter, the signals are sequentially input in the same manner, and the k-bit signal of the last (m / k) group is input to the input port N of the unit switch 3 from S39.

The connection on the output side of the unit switches 1 to 3 is symmetrical to the connection on the input side, and the output signal # 1 is the signal S41 output from each output port 1 to s of the unit switch 1 to 3. ~ S49 are collected into a signal S40. The output signal # 2 is a signal S51 to S59 output from each of the output ports (s + 1) to 2s of the unit switches 1 to 3.
Is obtained as a signal S50. The output signal # (N / s) is applied to each output port (N−s +
1) A signal S60 obtained by collecting the signals S61 to S69 output from N.

If s = 1 in the configuration of FIG. 1, the configuration is the same as that of FIG. 16 described in the background art.

The configuration shown in FIG. 1 is the same as the conventional configuration shown in FIG. 16 in that m-bit parallel input / output signals are connected to the input / output port of the unit switch in units of k bits. Is one input / output signal k
The difference is that a plurality of sets of bits are connected to one unit switch.

[2] Description of Operation Next, the operation of the embodiment of the present invention will be described.

FIG. 2 is a block diagram showing a case where the N × N switch shown in FIG. 16 is applied to the (N / s) × (N / s) switch shown in FIG.

First, referring to FIG. 2, an (N / s) × (N / s) switch similar to that of FIG. 1 was constructed using the conventional N × N unit switch shown in FIG. 16 as it is. The problem in the case will be described. A case where the input signal # 1 is output as the output signal # 2 as in the case of FIG. 16 described above will be described.

The data D510 input to S510 has "2" as switch control information indicating an output destination, and the unit switch 501 performs processing based on this switch control information as in the conventional case. However, as it is, D510 is bit sliced into D511 to D51.
3 also has the same switch control information “2”, so that all the data D511 to D513 input to the input ports 1 to s of the unit switch 501 are output to the output port 2.

The output port expected at this time is D51
1 is an output port (s + 1), D512 is an output port (s + 2), and D513 is an output port 2s.

Next, the operation of the present invention will be described with reference to FIG. As in the case of FIG. 2 described above, the input signal # 1
Is output to the output signal # 2. In the bit slice processing, all the unit switches perform the same operation, and thus only the operation of the unit switch 1 will be described here.

The input / output ports of the unit switch 1 shown in FIG. 1 are grouped by s. That is, the physical I / O ports 1 to s are logically treated as the I / O port 1, the physical I / O ports (s + 1) to 2s are logically treated as the I / O port 2, and so on. N
−s + 1) to N are provided in the unit switch 1 so that they can be logically handled as input / output ports (N / s).

In this case, there are s physical output ports ((s + 1) to 2s) for the switch control information (for example, “2”) indicating one output destination. Therefore, the physical input ports (p × s + q) ) (P, q: 0 ≦ p ≦ N / s−)
1,1 ≦ q ≦ s).
Physical output port (r × s + q) (0 ≦ r ≦ N / s−1,
(r is a value specified by the switch control information). In addition, the value of s is recognized by an external setting for each unit switch (for example, setting by a DC signal in hardware, downloading of a setting value from firmware).

With such a mechanism, when the switch control information is "2", the unit switch 1
Connects input port 1 and output port (s + 1),
The input port 2 is connected to the output port (s + 2), and the input port s is connected to the output port 2s. As a result, the bit-sliced signals S11 to S13 become S1
1 is output to S51, S12 is output to S52, and S
13 will be output to S53. Similar processing is performed for other combinations of input / output signals.

FIG. 3 is a block diagram showing a method for converting switch control information according to an embodiment of the present invention.

FIG. 4 is an example of a conversion table of the switch control information conversion unit in FIG. FIG. 4A shows a conversion table of the switch control information conversion unit 602, and FIG.
4 shows a conversion table of the switch control information conversion unit 603, and FIG. 4C shows a conversion table of the switch control information conversion unit 604.

By using FIG. 3 and FIG. 4 to convert the switch control information of the input signal in advance (N /
A mechanism for operating as an (s) × (N / s) switch will be described. Since all unit switches perform the same operation,
Here, only the operation of the unit switch 601 is controlled by the input signal #
1 will be described as an output signal # 2.

Input signal # 1 is input to S610. S
Data D610 on 610 has "2" as switch control information. As S610 is bit-sliced into S611 to S613, data D610 is also bit-sliced into data D611 to D613.
Data D611 to D613 are the same as data D610.
It has switch control information “2”.

The data D 611 is input to the switch control information conversion unit 602, and is output as data D 614 in which the switch control information is converted from “2” to “s + 1”, and is input to the input port 1 of the unit switch 601.
The data D612 is input to the switch control information conversion unit 603, is output as data D615 in which the switch control information is converted from "2" to "s + 2", and is input to the input port 2 of the unit switch 601. Similarly,
The data D613 is input to the switch control information conversion unit 604, and is output as data D616 in which the switch control information is converted from “2” to “2s”.
01 is input to the input port s.

As described above, the switch control information of the bit-sliced data D611 to D613 is pre-converted before being input to the unit switch 601.
Data D614 to D616 input from 02 to 604
May be directly output to the output port indicated by the switch control information. Thus, data can be output to a desired output signal # 2. Here, the contents of the conversion tables of the switch control information conversion units 602 to 604 are all different.

When input signal # 2 is input, switch control information converters 605 to 607 perform the same operation.

FIG. 4A shows the input port (p × s + 1) (p: 0) of the unit switch 601 for other input signals.
≤p≤N / s-1), which is a conversion table of the switch control information conversion units (602, 605, ‥‥) used in FIG. 4 (b), which is used in the input port (p × s + 2). Switch control information converter (603, 606,.
‥), and FIG. 4C shows the conversion table of the switch control information conversion units (604, 607, ‥‥) used in the input port (p × s + s).

[0051]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

[1] Description of Configuration FIGS. 5 to 7 show configurations when specific values are used for the configuration of FIG. FIG. 5 is a block diagram of a case where an 8 × 8 switch is configured using FIG. 1, and shows a case where N = 8, s = 1, m = 8, and k = 2 in FIG. FIG. 6 is a block diagram in the case of configuring a 4 × 4 switch using FIG. 1. In FIG. 1, N = 8, s = 2,
The case where m = 8 and k = 2 is shown. FIG. 7 shows FIG.
FIG. 2 is a block diagram in the case of configuring a 2 × 2 switch by using N = 8, s = 4, m = 8, and k = 2 in FIG. Hereinafter, each figure will be described in order.

The configuration shown in FIG. 5 will be described. In FIG. 5, the unit switches 201 to 204 are 8 × 8 switches each having a processing bit width of 2 bits per physical port.

The connection on the input side will be described. The input signal # 1 is an 8-bit parallel signal and is input to S210.
S210 is bit-sliced two bits at a time and S211
To S214, each of which is a unit switch 201 to 2
04 is input to the physical input port 1. At this time, S2
11 is input to the physical input port 1 of the unit switch 201, and S212 is the physical input port 1 of the unit switch 202.
S213 is input to the physical input port 1 of the unit switch 203, and S214 is input to the physical input port 1 of the unit switch 204.

The input signal # 2 is input to S220 and is bit-sliced every two bits, resulting in S221 to S224. S221 to S224 correspond to the unit switch 20 respectively.
1 to 204 are input to the physical input ports 2. S221
Is input to the unit switch 201, S222 is input to the unit switch 202, and S223 is the unit switch 203.
S224 is input to the unit switch 204.

In the same manner, the input signal # 3 is changed to S230
And is bit-sliced two bits at a time,
1 to S234. Steps S231 to S234 are input to the physical input ports 3 of the unit switches 201 to 204, respectively. The input signal # 4 is input to S240 and is bit-sliced by two bits, resulting in S241 to S244.
S241 to S244 correspond to the unit switches 201 to 201, respectively.
204 is input to the physical input port 4. Input signal # 5
Is input to S250 and is bit-sliced by two bits, resulting in S251 to S254. S251 to S254
Are input to the physical input ports 5 of the unit switches 201 to 204, respectively. The input signal # 6 is input to S260 and bit-sliced by two bits, and S261 to S2
64. Steps S261 to S264 are input to the physical input ports 6 of the unit switches 201 to 204, respectively.
The input signal # 7 is input to S270, and is bit-sliced every two bits, resulting in S271 to S274. S271
Steps S274 to S274 are input to the physical input ports 7 of the unit switches 201 to 204, respectively. Input signal # 8 is S28
0, and is bit-sliced two bits at a time.
81 to S284. Steps S281 to S284 are input to the physical input ports 8 of the unit switches 201 to 204, respectively.

The connection on the output side will be described. Unit switch 2
S216 output from the physical output port 1 of the unit switch 202 and S216 output from the physical output port 1 of the unit switch 202.
217, a signal S2 obtained by combining S218 output from the physical output port 1 of the unit switch 203 and S219 output from the physical output port 1 of the unit switch 204.
15 is output as the output signal # 1.

Similarly, S226 to S226 output from the physical output port 2 of each of the unit switches 201 to 204
229 are output as output signal # 2. A signal S235 in which S236 to S239 output from the respective physical output ports 3 of the unit switches 201 to 204 are combined is output as an output signal # 3. A signal S245 in which S246 to S249 output from the respective physical output ports 4 of the unit switches 201 to 204 are combined is output as an output signal # 4. Physical output port 5 of each of unit switches 201 to 204
S2 that summarizes S256 to S259 output from
55 is output as output signal # 5. A signal S265 that summarizes S266 to S269 output from the physical output port 6 of each of the unit switches 201 to 204 is
Output as output signal # 6. Unit switches 201 to
S output from each physical output port 7 of S204
A signal S275 obtained by combining 276 to S279 is output as an output signal # 7. S286 to S286 output from each physical output port 8 of the unit switches 201 to 204
A signal S285 that summarizes S289 is output as the output signal # 8.

The configuration of FIG. 6 will be described. In FIG. 6, the unit switches 301 and 302 are 8 × 8 switches each having a processing bit width of 2 bits per physical port.

The connection on the input side will be described. The input signal # 1 is an 8-bit parallel signal and is input to S310.
S310 is bit-sliced two bits at a time and S311
~ S314, and two sets of unit switches 301, 30
2 is input. At this time, S311 is the unit switch 3
S312 is input to the physical input port 2 of the unit switch 301. S31
3 is input to the physical input port 1 of the unit switch 302, and S314 is the physical input port 2 of the unit switch 302.
Is input to

Similarly, the input signal # 2 is changed to S320
, And is bit-sliced two bits at a time,
1 to S324. S321 to S324 are each two sets,
It is input to the unit switches 301 and 302. At this time,
S321 and S322 are input to the physical input ports 3 and 4 of the unit switch 301, respectively. S323, S32
4 are input to the physical input ports 3 and 4 of the unit switch 302, respectively.

The input signal # 3 is input to S330 and is bit-sliced by two bits, resulting in S331 to S334. Steps S331 to S334 are performed in units of the unit switch 30 by two sets.
1,302. S331 and S332 are input to the physical input ports 5 and 6 of the unit switch 301, respectively. Steps S333 and S334 are input to the physical input ports 5 and 6 of the unit switch 302, respectively.

The input signal # 4 is input to S340 and is bit-sliced by two bits, resulting in S341 to S344. Steps S341 to S344 are performed in units of the unit switch 30 by two sets.
1,302. S341 and S342 are input to the physical input ports 7 and 8 of the unit switch 301, respectively. Steps S343 and S344 are input to the physical input ports 7 and 8 of the unit switch 302, respectively.

The connection on the output side will be described. Unit switch 3
S351 output from the physical output port 1 of the unit switch 301 and S351 output from the physical output port 2 of the unit switch 301.
352, a signal S3 obtained by combining S353 output from the physical output port 1 of the unit switch 302 and S354 output from the physical output port 2 of the unit switch 302.
50 are output as output signal # 1.

In the same manner, S361 and S361 respectively output from the physical output ports 3 and 4 of the unit switch 301
S362, the physical output port 3 of the unit switch 302,
A signal S360 in which S363 and S364 respectively output from No. 4 are output is output as an output signal # 2.
S371 and S372 output from the physical output ports 5 and 6 of the unit switch 301, respectively, and the unit switch 30
S3 output from the physical output ports 5 and 6
A signal S370 obtained by combining 73 and S374 is output as the output signal # 3. S381 and S38 output from the physical output ports 7 and 8 of the unit switch 301, respectively.
2 and the signal S380 in which S383 and S384 outputted from the physical output ports 7 and 8 of the unit switch 302 are outputted as the output signal # 4.

The configuration of FIG. 7 will be described. In FIG. 7, the unit switch 401 is an 8 × 8 switch in which the processing bit width per physical port is 2 bits.

The connection on the input side will be described. The input signal # 1 is an 8-bit parallel signal and is input to S410.
S410 is bit-sliced two bits at a time and S411
To 414, all of which are input to the unit switch 401. At this time, S411 is input to the physical input port 1, S412 is input to the physical input port 2, and S41 is input.
3 is input to the physical input port 3, and S414 is input to the physical input port 4.

Similarly, the input signal # 2 is input to S420 and bit-sliced two bits at a time.
This will be S424. Steps S421 to S424 are all input to the unit switch 401. S421 is the physical input port 5
S422 is input to the physical input port 6,
S423 is input to the physical input port 7, and S424 is input to the physical input port 8.

The connection on the output side will be described. Unit switch 4
S431 output from the physical output port 1 of the unit switch 401 and S431 output from the physical output port 2 of the unit switch 401.
432, S433 output from the physical output port 3 of the unit switch 401, and S434 output from the physical output port 4 of the unit switch 401.
30 is output as output signal # 1.

Similarly, S441 output from the physical output port 5 of the unit switch 401, S442 output from the physical output port 6, S443 output from the physical output port 7, and output from the physical output port 8 A signal S440 obtained by summing up S444 obtained above is output as an output signal # 2.

FIG. 8 is a block diagram showing a main signal system of a switch configuration method according to an embodiment of the present invention. A circuit is added to the output buffer type ATM switch described with reference to FIG. Is realized. FIG.
Are added to the selection circuits 811 to 818,
The cell multiplexing circuits 822 and 823.

The input signals # 1 to # 8 are 2-bit parallel signals, respectively, and are input to S811 to S818.

The input / output of the cell multiplexing circuit 821 has eight inputs and one output with a 2-bit width. Cell multiplexing circuit 821
S811 is input to the input port 1 of the
, S812 is input to input port 3, S814 is input to input port 4, S815 is input to input port 5, and S815 is input to input port 6.
816 is input, S817 is input to the input port 7, and S818 is input to the input port 8. The output signal S841 of the cell multiplexing circuit 821 is wired in the form of a bus S844, and the bus S844 and the input A of the selection circuits 811 to 818 are connected to two-bit parallel signals S851 to S8, respectively.
58.

The input / output of the cell multiplexing circuit 822 is 4 inputs and 1 output having a 4-bit width. Cell multiplexing circuit 822
S811 and S812 are input to the input port 1 of the device, S815 and S814 are input to the input port 2, S815 and S816 are input to the input port 3, and S817 and S818 are input to the input port 4. The output signal S842 of the cell multiplexing circuit 822 is wired in the form of a bus S845, and the bus S845 and the input B of the selection circuits 811 to 818 are connected using 4-bit parallel signals S861 to S864. At this time, S861 is input to the selection circuits 811 and 812 on a 2-bit basis, S862 is input to the selection circuits 813 and 814 on a 2-bit basis, S863 is input to the selection circuits 815 and 816 on a 2-bit basis, and S864 is 2
The data is input to the selection circuits 817 and 818 bit by bit.

The cell multiplexing circuit 823 has two inputs and one output with an 8-bit width. Cell multiplexing circuit 823
S811 to S814 are input to the input port 1, and S815 to S818 are input to the input port 2. The output signal S843 of the cell multiplexing circuit 823 is wired in the form of a bus S846, and the bus S846 and the input C of the selection circuits 811 to 818 are connected using 8-bit parallel signals S871 and S872. At this time, S871 is input to the selection circuits 811 to 814 two bits at a time, and S872 is input to the selection circuits 815 to 818 two bits at a time.

The 2-bit parallel output signals S881 to S888 selected by the selection circuits 811 to 818 are input to the cell buffers 801 to 808, respectively. From the cell buffers 801 to 808, a 2-bit parallel signal S
891 to S898 and output signals # 1 to # 8
It becomes 8.

[2] Description of Operation Next, the operation of the embodiment of the present invention will be described in detail with reference to the drawings.

As described above in the description of the configuration, FIG.
FIG. 4 is a block diagram in the case of configuring eight switches. Since the unit switches 201 to 204 all perform the same operation, only the operation of the unit switch 201 will be described here.

When the unit switch 201 outputs the input signal # 1 input to the physical input port 1 from S210, the unit switch 201 according to the switch control information of the input signal # 1
When the signal is output as the output signal # 1 from S215, it is output to the physical output port 1. Similarly, when the output signal # 2 is output from S225, the signal is output to the physical output port 2, when the output signal # 3 is output from S235, the signal is output to the physical output port 3, and the output signal # 4 is output from S245. Is output to the physical output port 4 when output is performed, and is output to the physical output port 5 when output as the output signal # 5 from S255, and the output signal # 6 is output from S265.
Output to the physical output port 6 and output as S
In the case where the output signal # 7 is output as the output signal # 7, the signal is output to the physical output port 7, and when the output signal # 8 is output from the step S285, the signal is output to the physical output port 8. The same applies to other input signals # 2 to # 8.

This operation is the same whether the conventional 8 × 8 switch or the 8 × 8 switch of the present invention is used.

FIG. 6 is a block diagram of a 4 × 4 switch configured using 8 × 8 unit switches. Since the unit switches 301 and 302 perform the same operation, only the operation expected of the unit switch 301 will be described here.

When outputting the input signal # 1 input to the physical input ports 1 and 2 from S310, the unit switch 301 outputs the output signal # 1 from S350 according to the switch control information of the input signal # 1. The signal S311 input to the physical input port 1 is output as the signal S351 from the physical output port 1, the signal S312 input to the physical input port 2 is output as the signal S352 from the physical output port 2, and the signals S351 and S352 are Is output as an output signal # 1. Similarly, when the signal is output as the output signal # 2 from S360, the signal S311 is output as the signal S361 from the physical output port 3, the signal S312 is output as the signal S362 from the physical output port 4, and the signals S361 and S361 are output.
362 is output as an output signal # 2. When the signal S311 is output from S370 as the output signal # 3, the signal S311 is output from the physical output port 5 to the signal S3.
71, the signal S312 is output from the physical output port 6 as the signal S372, and the signals S371 and S372 are output.
Is output as an output signal # 3. When the signal S311 is output from S380 as the output signal # 4, the signal S311 is output from the physical output port 7 to the signal S381.
, The signal S312 is output from the physical output port 8 as the signal S382, and the signal S380 obtained by combining the signals S381 and S382 is output as the output signal # 4.

When the input signal # 2 input to the physical input ports 3 and 4 from S320 is output from S350,
The signal S321 input to the physical input port 3 is converted to a signal S35
The signal S3 output as 1 and input to the physical input port 4
22 is output as a signal S352, and signals S351 and S3 are output.
52 is output as an output signal # 1. Similarly, when outputting from S360,
The signal S321 is output as the signal S361, and the signal S32
2 is output as a signal S362, and signals S361 and S36 are output.
2 is output as an output signal # 2. When outputting from S370, the signal S321 is output as the signal S371, and the signal S322 is output as the signal S37.
2 and outputs a signal S370 that combines the signals S371 and S372 as an output signal # 3. S380
, The signal S321 is output as the signal S381, the signal S322 is output as the signal S382, and the signal S380 obtained by combining the signals S381 and S382 is output.
As an output signal # 4.

When the input signal # 3 input to the physical input ports 5 and 6 from S330 is output from S350,
The signal S331 input to the physical input port 5 is converted to a signal S35
The signal S3 output as 1 and input to the physical input port 6
32 is output as a signal S352, and signals S351 and S3 are output.
52 is output as an output signal # 1. Similarly, when outputting from S360,
The signal S331 is output as the signal S361, and the signal S33 is output.
2 is output as a signal S362, and signals S361 and S36 are output.
2 is output as an output signal # 2. When outputting from S370, the signal S331 is output as the signal S371, and the signal S332 is output as the signal S37.
2 and outputs a signal S370 that combines the signals S371 and S372 as an output signal # 3. S380
, The signal S331 is output as the signal S381, the signal S332 is output as the signal S382, and the signal S380 obtained by combining the signals S381 and S382 is output.
As an output signal # 4.

When the input signal # 4 input to the physical input ports 7 and 8 from S340 is output from S350,
The signal S341 input to the physical input port 7 is converted to a signal S35
The signal S3 output as 1 and input to the physical input port 8
42 is output as a signal S352, and signals S351 and S3 are output.
52 is output as an output signal # 1. Similarly, when outputting from S360,
The signal S341 is output as the signal S361, and the signal S34 is output.
2 is output as a signal S362, and signals S361 and S36 are output.
2 is output as an output signal # 2. When outputting from S370, the signal S341 is output as the signal S371, and the signal S342 is output as the signal S37.
2 and outputs a signal S370 that combines the signals S371 and S372 as an output signal # 3. S380
, The signal S341 is output as the signal S381, the signal S342 is output as the signal S382, and the signal S380 obtained by combining the signals S381 and S382 is output.
As an output signal # 4.

FIG. 7 is a block diagram of a 2 × 2 switch configured using 8 × 8 unit switches. The expected operation of the unit switch 401 will be described.

When outputting the input signal # 1 input to the physical input ports 1 to 4 from S410, the unit switch 401 outputs the output signal # 1 from S430 according to the switch control information of the input signal # 1. The signal S411 input to the physical input port 1 is output from the physical output port 1 as a signal S431, the signal S412 input to the physical input port 2 is output from the physical output port 2 as a signal S432, and is output to the physical input port 3. The input signal S413 is output from the physical output port 3 as a signal S433, and the signal S414 input to the physical input port 4 is output.
Is output from the physical output port 4 as a signal S434, and a signal S430 obtained by combining the signals S431 to S434 is output as an output signal # 1. Similarly, when outputting from S440 as the output signal # 2, the signal S411 is output from the physical output port 5 as the signal S441, and the signal S412 is output.
Is output from the physical output port 6 as a signal S442, the signal S413 is output from the physical output port 7 as a signal S443, and the signal S414 is output from the physical output port 8 as a signal S4.
44, and outputs a signal S440 obtained by combining the signals S441 to S444 as an output signal # 2.

When the input signal # 2 input to the physical input ports 5 to 8 from S420 is output from S430,
The signal S421 input to the physical input port 5 is converted to a signal S43.
The signal S4 output as 1 and input to the physical input port 6
22 is output as a signal S432, the signal S423 input to the physical input port 7 is output as a signal S433, and the signal S424 input to the physical input port 8 is output as a signal S434.
, And a signal S4 obtained by combining the signals S431 to S434.
30 is output as the output signal # 1. Similarly, S440
, The signal S421 is output as the signal S441, the signal S422 is output as the signal S442, the signal S423 is output as the signal S443, and the signal S421 is output.
424 is output as a signal S444, and the signals S441 to S441 are output.
A signal S440 obtained by summing 444 is output as an output signal # 2.

FIG. 9 is a block diagram showing a case where the conventional 8 × 8 switch is applied to the 4 × 4 switch shown in FIG.

Referring to FIG. 9, the operation when the output is not performed as expected when the conventional 4 × 4 switch shown in FIG. 6 is constructed using the conventional unit switch for the 8 × 8 switch as it is. explain.

The switch control information indicating the output destination of the data D1210 of the input signal # 1 is "2", and the switch control information of D1211, D1212 of the data obtained by bit-slicing the 8-bit data D1210 by 2 bits is also "2". 2 ". The switch control information of the data D1220 indicating the output destination of the input signal # 2 is "4".
The switch control information of D1221 and D1222 of the data obtained by bit-slicing the bit data D1220 by 2 bits is also “4”. The switch control information of the data D1230 indicating the output destination of the input signal # 3 is "3",
The switch control information of D1231 and D1232 of the data obtained by bit-slicing the 8-bit data D1230 by 2 bits is also “3”. The switch control information of the data D1240 indicating the output destination of the input signal # 4 is "1", and D1241 and D124 of the data obtained by bit-slicing the 8-bit data D1240 by two bits at a time.
The switch control information of No. 2 is also “1”.

Here, D1211, D1212 and D122 are connected to the physical input ports 1 to 8 of the unit switch 1201.
1, D1222, D1231, D1232, D124
When the unit switch 1201 operates in accordance with the switch control information of these data when D1 and D1242 are sequentially input, D1211 and D1212 are output to the physical output port 2 of the unit switch, and D1221 and D121 are output.
22 is output to the physical output port 4, and D1231, D1
232 is output to the physical output port 3, and D1241, D124
1242 will be output to the physical output port 1,
This is different from the expected behavior.

As a method for solving this, as shown in FIGS. 5 to 7, a plurality of physical input / output ports of the unit switch are put together to form a logical input / output port according to the size of the switch to be applied. .

That is, when an 8 × 8 switch is configured as shown in FIG. 5, each physical input / output port is handled independently as in the conventional case.

When a 4 × 4 switch is configured as shown in FIG. 6, the physical input / output ports of the unit switch are handled as follows. The physical input ports 1 and 2 are collectively referred to as a logical input port 1, and the physical output ports 1 and 2 are collectively referred to as a logical output port 1. The physical input ports 3 and 4 are collectively referred to as a logical input port 2, and the physical output ports 3 and 4 are collectively referred to as a logical output port 2. Physical input port 5,
6 are collectively referred to as a logical input port 3, and the physical output ports 5 and 6 are collectively referred to as a logical output port 3. The physical input ports 7, 8 are collectively referred to as a logical input port 4, and the physical output ports 7, 8 are collectively referred to as a logical output port 4.

Further, when a 2 × 2 switch is configured as shown in FIG. 7, the physical input / output ports of the unit switch are handled as follows. The physical input ports 1 to 4 are collectively referred to as a logical input port 1, and the physical output ports 1 to 4 are collectively referred to as a logical output port 1. The physical input ports 5 to 8 are collectively referred to as a logical input port 2, and the physical output ports 5 to 8 are collectively referred to as a logical output port 2.

FIG. 8 shows an example of a switch configuration method of the present invention realized by adding a circuit to the output buffer type ATM switch of FIG. 17 in the prior art, as described above in the description of the configuration. The basic operation of FIG. 8 is the same as that of the conventional ATM switch shown in FIG.
Reference numeral 818 selects a signal to be output according to an external setting. Here, external means a DC signal from hardware,
Refers to firmware, etc.

First, the case where FIG. 8 operates as an 8 × 8 switch will be described. In this case, the selection circuits 811 to 81
Reference numeral 8 outputs a signal input from the input A according to an external setting.

In the 8 × 8 switch, the input signal # 1 is changed to S8
11 is directly input to the logical input port 1 of the cell multiplexing circuit 821. Similarly, input signals # 2 to # 8 are respectively converted from S812 to S818 to cell multiplexing circuit 82.
1 is input to each of the logical input ports 2 to 8.

The outputs of the cell buffers 801 to 808 are set as logical output ports 1 to 8, respectively, and the signals S891 to S898 output from the cell buffers 801 to 808 are output.
As output signals # 1 to # 8.

The cell multiplexing circuit 821 multiplexes the signals S811 to S818 input to the logical input ports 1 to 8 and outputs the result. The signal S output from the cell multiplexing circuit 821
841 is wired in the form of a bus S844, and the output signal of the bus S844 is input to the input A of the selection circuits 811 to 818 by 2 bits at S851 to S858, respectively.
The selection circuits 811 to 818 select the selection signal S that selects the input A.
881 to S888 are output, and each is output to the cell buffer 8.
01 to 808.

Thus, the cell buffers 801-8
A signal (the output signal S841 of the cell multiplexing circuit 821) having the same content is input to all of the bits 08, but only the cell buffer to which the write permission is given from the control unit (not shown) can write the input signal. Here, the control unit has a function of controlling writing and reading of the cell buffers 801 to 808 according to the switch control information of the input signals # 1 to # 8.

Therefore, when the output destination of the cell of the input signal # 1 input to the logical input port 1 from S811 is the output signal # 2 output from the logical output port 2, only the cell buffer 802 has Write permission is given from the control unit.

Next, a case where FIG. 8 operates as a 4 × 4 switch will be described. The selection circuits 811 to 818 output a signal input from the input B according to an external setting.

In the 4 × 4 switch, the input signal # 1 is changed to S8
The 2-bit signal input from S11 and the input signal # 2 are converted to S8
12 and the 4-bit signal S
821, a logical input port 1 of the cell multiplexing circuit 822
To enter. Similarly, input signals # 3 and # 4 of 2 bits are input to the logical input port 2 of the cell multiplexing circuit 822 as 4-bit signals S822. input signal#
5 and # 6 are input to the logical input port 3 as S823. The input signals # 7 and # 8 are input to the logical input port 4 as S824.

The outputs of the cell buffers 801 and 802 are set to the logical output port 1 and
2 are output signals # 891 and # 892 from output signal #
1 and # 2. Similarly, the cell buffer 8
03, 804 as the logical output port 2, the signals S893, S89 output from the cell buffers 803, 804
894 are output as output signals # 3 and # 4. The outputs of the cell buffers 805 and 806 are used as the logical output port 3
Signal S89 output from cell buffers 805 and 806
5, S896 are output as output signals # 5 and # 6. The outputs of the cell buffers 807 and 808 are set as the logical output port 4, and the signals S897 and S898 output from the cell buffers 807 and 808 are output as output signals # 7 and # 8.

The cell multiplexing circuit 822 multiplexes the signals S821 to S824 input to the logical input ports 1 to 4 and outputs the signals. The signal S output from the cell multiplexing circuit 822
842 is wired in the form of a bus S845, and the output signal of the bus S845 is input to the input B of the selection circuits 811 to 818 by two bits at S861 to S864, each having 4 bits. At this time, S861 is switched to the selection circuits 811 and 8
12, S862 is input to the selection circuits 813, 814, and S863 is input to the selection circuits 815, 816, and S
864 is input to the selection circuits 817 and 818. The selection circuits 811 to 818 select the input B and select signals S881 to S881.
S888 is output, and each of the cell buffers 801-8 is output.
08.

Therefore, when the output destination of the cells of the input signals # 1 and # 2 input to the logical input port 1 from S811 and S812 is the output signal # 2 output from the logical output port 2, the cell buffer 803 , 804 only from the control unit.

Next, the case where FIG. 8 operates as a 2 × 2 switch will be described. The selection circuits 811 to 818 output signals input from the input C according to external settings.

In the 2 × 2 switch, the input signal # 1 is supplied to S8
The 2-bit signal input from S11 and the input signal # 2 are converted to S8
The 2-bit signal input from # 12 and the input signal # 3 are converted to S8
13 and the input signal # 4 in S8
14 and an 8-bit signal S
As 831, it is input to the logical input port 1 of the cell multiplexing circuit 823. Similarly, the input signals # 5 to # 8 are sent to S815
To each of the 2-bit signals input from S818
The bit signal S832 is input to the logical input port 2 of the cell multiplexing circuit 823.

The outputs of the cell buffers 801 to 804 are set as the logical output port 1 and the cell buffers 801 to 80
4 are output signals # 891 to S894.
Output as 1 to # 4. Similarly, the cell buffer 805
808 as the logical output port 2, the signals S895 to S89 output from the cell buffers 805 to 808
8 are output as output signals # 5 to # 8.

The cell multiplexing circuit 823 multiplexes the signals S831 and S832 input to the logical input ports 1 and 2 and outputs the result. The signal S output from the cell multiplexing circuit 823
843 is wired in the form of a bus S846, and the output signal of the bus S846 is input to the input B of the selection circuits 811 to 818 in two bits by S871 and S872, each having 8 bits. At this time, S871 is switched to the selection circuits 811 to 811.
14, and S872 is input to the selection circuits 815 to 818. The selection circuits 811 to 818 output selection signals S881 to S888 for selecting the input B, and input them to the cell buffers 801 to 808, respectively.

Therefore, when the output destination of the cells of the input signals # 1 to # 4 input to the logical input port 1 from S811 to S814 is the output signal # 2 output from the logical output port 2, the cell buffer 805 Write permission is given from the control unit only to .about.808.

FIG. 10 is a block diagram showing a selection circuit of a switch configuration method according to an embodiment of the present invention.

The operation of converting the write enable signal output from the control unit shown in FIG. 8 according to the switch control information according to the switch size will be described with reference to FIG.

Write enable signal S911 for cell buffer
S918 to S918 are signals generated according to the switch control information of the data input to the switch, and are converted by the selection circuits 901 to 908 according to the switch size to become new write enable signals S921 to S928. Each of S928 controls the writing of the eight cell buffers S931 to S938. The selection circuits 901 to 908 select the input A when the switch size is 8 × 8, select the input B when the switch size is 4 × 4, and select the input B when the switch size is 2 × 2. Select C. The switch size is specified by setting from a hardware strap or firmware.

In the case of the 8 × 8 switch, if the output destination of the cell of the input signal is the logical output port 1, write permission is issued to the original write permission signal S911, and S91
The write enable signal S921 is output from the selection circuit 901 in which 1 is input to the input A. Write enable signal S9
Since 21 is input to the cell buffer 931, S891 shown in FIG. 8 is output as the output signal # 1.

When the output destination of the cell of the input signal is the logical output port 2, the write permission is issued to the original write enable signal S912, and the write enable signal is sent from the selection circuit 902 to which the input A is input to the input A. S922 is output. Since the write enable signal S922 is input to the cell buffer 932, S892 shown in FIG.
Is output as

When the output destination of the cell of the input signal is the logical output port 3, the write permission is issued to the original write enable signal S913, and the write enable signal is sent from the selection circuit 903 to which the input A is input to the input A. S923 is output. Since the write enable signal S923 is input to the cell buffer 933, S893 shown in FIG.
Is output as

When the output destination of the cell of the input signal is the logical output port 4, the write permission is issued to the original write enable signal S914, and the write enable signal is sent from the selection circuit 904 to which the input A is input to the input A. S924 is output. Since the write enable signal S924 is input to the cell buffer 934, S894 shown in FIG.
Is output as

When the output destination of the cell of the input signal is the logical output port 5, the write permission is issued to the original write enable signal S915, and the write enable signal is output from the selection circuit 905 to which the input A is inputted to the input A. S925 is output. Since the write enable signal S925 is input to the cell buffer 935, S895 shown in FIG.
Is output as

When the output destination of the cell of the input signal is the logical output port 6, the write permission is issued to the original write enable signal S916, and the write enable signal is sent from the selection circuit 906 to which the input A is input to the input A. S926 is output. Since the write enable signal S926 is input to the cell buffer 936, S896 shown in FIG.
Is output as

When the output destination of the cell of the input signal is the logical output port 7, the write permission is issued to the original write enable signal S917, and the write enable signal is output from the selection circuit 907 to which the input A is inputted to the input A. S927 is output. Since the write enable signal S927 is input to the cell buffer 937, S897 shown in FIG.
Is output as

When the output destination of the cell of the input signal is the logical output port 8, the write permission is issued to the original write enable signal S918, and the write enable signal is sent from the selection circuit 908 to which the input A is inputted to the input A. S928 is output. Since the write enable signal S928 is input to the cell buffer 938, S898 shown in FIG.
Is output as

In the case of the 4 × 4 switch, if the output destination of the cell of the input signal is the logical output port 1, write permission is issued to the original write permission signal S911, and S91
The write enable signals S921 and S922 are output from the selection circuits 901 and 902 in which 1 is input to the input B. The write enable signals S921 and S922 are transmitted to the cell buffer 93.
1, 932, so that S891 shown in FIG.
S892 is output as the output signal # 1.

If the output destination of the cell of the input signal is the logical output port 2, the write permission is issued to the original write enable signal S912, and S912 is written from the selection circuits 903 and 904 to which the input B is input. Permission signal S92
3, S924 is output. Write enable signal S923,
Since S924 is input to the cell buffers 933 and 934, S893 and S894 shown in FIG. 8 are output as the output signal # 2.

When the output destination of the cell of the input signal is the logical output port 3, the write permission is issued to the original write enable signal S913, and S913 is written from the selection circuits 905 and 906 to which the input B is input. Permission signal S92
5, S926 is output. Write enable signal S925,
Since S926 is input to the cell buffers 935 and 936, S895 and S896 shown in FIG. 8 are output as the output signal # 3.

When the output destination of the cell of the input signal is the logical output port 4, a write permission is issued to the original write enable signal S914, and S914 is written from the selection circuits 907 and 908 to which the input B is input. Permission signal S92
7, S928 is output. The write enable signal S927,
Since S928 is input to the cell buffers 937 and 938, S897 and S898 shown in FIG. 8 are output as the output signal # 4.

In the case of the 2 × 2 switch, if the output destination of the cell of the input signal is the logical output port 1, write permission is issued to the original write permission signal S911, and S91
The write enable signals S921 to S924 are output from the selection circuits 901 to 904 in which 1 is input to the input C. The write enable signals S921 to S924 are transmitted to the cell buffer 93.
1 to 934, so that S891 to S891 shown in FIG.
S894 is output as the output signal # 1.

When the output destination of the cell of the input signal is the logical output port 2, the write permission is issued to the original write enable signal S912, and S912 is written from the selection circuits 905 to 908 input to the input C. Permission signal S925
To S928. Write enable signal S925-S
Since 928 is input to the cell buffers 935 to 938, S895 to S898 shown in FIG. 8 are output as the output signal # 2.

FIG. 11 is a block diagram showing a method for converting switch control information in one embodiment of the present invention. FIG.
In FIG. 1, only one unit switch is shown because a plurality of unit switches all perform the same operation in the bit slice configuration.

FIG. 12 is an example of a conversion table of the switch control information conversion unit in FIG. FIG. 12A shows switch control information conversion units 1001, 1003, 1005, 1
007 shows the conversion table of the physical input ports 1, 3,
This is a conversion table used in 5 and 7. FIG. 12 (b)
Are switch control information conversion units 1002, 1004, 100
6, 1008, is a conversion table used by the physical input ports 2, 4, 6, and 8.

However, when operating as an 8 × 8 switch, the switch control information conversion units 1001 to 1008
Becomes unnecessary.

A case in which the switch control information is converted to operate as a 4 × 4 switch will be described with reference to FIGS. 11 and 12.

In FIG. 11, input signals # 1 to # 4
Are input from logical input ports 1 to 4 (not shown), respectively, and output signals # 1 to # 4 are output to logical output ports 1 to 4 (not shown), respectively.

The switch control information converters 1001 to 1008 shown in FIG. 11 refer to the respective conversion tables shown in FIG. 12 to read the data D1 of the input signals # 1 to # 4.
The switch control information of each of 010, D1020, D1030, and D1040 is replaced with new switch control information.

The unit switch 1009 is a circuit similar to a unit switch constituting a conventional 8 × 8 switch, and data D1013, D1014, D102 input to each of the physical input ports 1 to 8 of the unit switch 1009.
3, D1024, D1033, D1034, D104
3. Determine the physical output port of the input data according to the newly replaced switch control information of D1044.

If the output destination of data D1010 of input signal # 1 is output signal # 2, D1010 is bit-sliced and D1011 is input to switch control information conversion section 1001, and D1012 is input to switch control information conversion section 1001. It is input to the conversion unit 1002. The switch control information conversion unit 1001 changes the input switch control information of D1011 from “2” to “3” in accordance with the conversion table shown in FIG. 12A and outputs it as D1013. In the switch control information conversion unit 1002, according to the conversion table shown in FIG.
The input switch control information of D1012 is changed from “2” to “4” and output as D1014.

In the unit switch 1009, the switch control information of the D1013 input from the physical input port 1 is “3”, so that it is output from the physical output port 3 and the switch control information of the D1014 input from the physical input port 2 is Since it is “4”, it is output from the physical output port 4. In this way, D1010 is output to the physical output ports 3 and 4 of the unit switch, so that it is output to the logical output port 2 as an output signal # 2.

When the output destination of the data D1020 of the input signal # 2 is the output signal # 4, the D1020 is bit sliced, and D1021 is input to the switch control information conversion unit 1003, and D1022 is input to the switch control information conversion unit 1003. Input to the conversion unit 1004. The switch control information conversion unit 1003 changes the input switch control information of D1021 from “4” to “7” according to the conversion table shown in FIG. 12A, and outputs it as D1023. In the switch control information conversion unit 1004, according to the conversion table shown in FIG.
The input switch control information of D1022 is changed from “4” to “8” and output as D1024.

In the unit switch 1009, the switch control information of D1023 input from the physical input port 3 is “7”, so that it is output from the physical output port 7, and the switch control information of D1024 input from the physical input port 4 is Since it is “8”, it is output from the physical output port 8. In this way, D1020 is output to the physical output ports 7 and 8 of the unit switch, so that it is output to the logical output port 4 as an output signal # 4.

When the output destination of the data D1030 of the input signal # 3 is the output signal # 3, D1030 is bit-sliced, and D1031 is input to the switch control information conversion unit 1005, and D1032 is input to the switch control information conversion unit 1005. The data is input to the conversion unit 1006. The switch control information conversion unit 1005 changes the input switch control information of D1031 from “3” to “5” according to the conversion table shown in FIG. 12A, and outputs it as D1033. In the switch control information conversion unit 1006, according to the conversion table shown in FIG.
The input switch control information of D1032 is changed from “3” to “6” and output as D1034.

In the unit switch 1009, the switch control information of the D1033 input from the physical input port 5 is “5”, so that it is output from the physical output port 5 and the switch control information of the D1034 input from the physical input port 6 is Since it is “6”, it is output from the physical output port 6. In this way, D1030 is output to the physical output ports 5 and 6 of the unit switch, so that it is output to the logical output port 4 as an output signal # 3.

If the output destination of data D1040 of input signal # 4 is output signal # 1, D1040 is bit-sliced, and D1041 is input to switch control information conversion section 1007, and D1042 is input to switch control information. The data is input to the conversion unit 1008. The switch control information conversion unit 1007 changes the input switch control information of D1041 from “1” to “1” according to the conversion table shown in FIG. 12A, and outputs it as D1043. In the switch control information conversion unit 1008, according to the conversion table shown in FIG.
The input switch control information of D1042 is changed from “1” to “2” and output as D1044.

In the unit switch 1009, the switch control information of D1043 input from the physical input port 7 is “1”, so that it is output from the physical output port 1 and the switch control information of D1044 input from the physical input port 8 is Since it is “2”, it is output from the physical output port 2. In this way, D1040 is output to the physical output ports 1 and 2 of the unit switch, so that it is output to the logical output port 4 as the output signal # 1.

In FIG. 12, the case of operating as a 4 × 4 switch has been described. However, in the case of a 2 × 2 switch, as shown in FIG. 13, it is necessary to cope only by changing the conversion table of the switch control information conversion unit. Can be.

FIG. 13 is an example of a conversion table of the switch control information conversion unit in FIG. FIG. 13A shows a conversion table of the switch control information conversion units 1001 and 1005, and is a conversion table used in the physical input ports 1 and 5. FIG. 13B shows the switch control information converter 10.
02, 1006 are conversion tables used by the physical input ports 2, 6. FIG. 13 (c)
Indicates a conversion table of the switch control information conversion units 1003 and 1007, and is a conversion table used by the physical input ports 3 and 7. FIG. 13D shows a conversion table of the switch control information conversion units 1004 and 1008, which is a conversion table used by the physical input ports 4 and 8.

FIGS. 14 and 15 are block diagrams showing a conversion circuit of the switch control information conversion unit in FIG.
FIG. 14A shows switch control information converters 1001 and 10.
FIG. 14B shows the conversion circuits of the switch control information conversion units 1002 and 1006, and FIG.
15A shows a conversion circuit of the switch control information conversion units 1003 and 1007, and FIG. 15B shows a conversion circuit of the switch control information conversion units 1004 and 1008.

Referring to FIGS. 14 and 15, switch control information conversion units 1001 to 1008 shown in FIG.
A method of converting switch control information using a conversion circuit without using a conversion table will be described.

In the above description, the values of the switch control information are set to "1" to "8", and correspond to the physical output port numbers of the unit switches.

In the method described with reference to FIGS. 14 and 15, the values of the switch control information are set to “0” to “7”, and
"0" corresponds to the physical output port 1, "1" corresponds to the physical output port 2, "2" corresponds to the physical output port 3, "3" corresponds to the physical output port 4, "4""
Correspond to the physical output port 5, "5" corresponds to the physical output port 6, "6" corresponds to the physical output port 7, and "7" corresponds to the physical output port 8.

The switch control information conversion unit handles these pieces of switch control information in binary numbers.

The conversion circuits 1111 to 11 shown in FIGS.
13,1121 to 1123,1131 to 1133,11
41 to 1143 select input A when operating as an 8 × 8 switch, select input B when operating as a 4 × 4 switch, and input C when operating as a 2 × 2 switch. select.

Switch control information S1111 to S111
3, S1121 to S1123, S1131 to S113
3, S1141 to S1143 are data held by the signal input to the switch control information conversion unit shown in FIG. 11, and S1111, S1121, and S113
1, S1141 is MSB, S1113, S1123, S
1133 and S1143 are LSB. “0” and “1” in the figure indicate fixed values input to the conversion circuit.

In the case of operating as an 8 × 8 switch, since all the conversion circuits select the input A, the switch control information included in the data input to the switch control information conversion units 1001 to 1008 is output without conversion. .

When operating as a 4 × 4 switch,
This will be described with reference to FIG. Here, the switch control information of each input data described in FIG. 11 is replaced with a value obtained by subtracting 1 from each.

In FIG. 11, input signals # 1 to # 4
Are input from logical input ports 1 to 4 (not shown), respectively, and output signals # 1 to # 4 are output to logical output ports 1 to 4 (not shown), respectively.

Each of the switch control information conversion units 1001 to 1008 shown in FIG. 11 uses the conversion circuits shown in FIGS. 14 and 15 to convert the data D of the input signals # 1 to # 4.
The switch control information of each of 1010, D1020, D1030, and D1040 is replaced with new switch control information.

Input signal # input from logical input port 1
One data D1010 is bit sliced, and D1011 of the data is input to the switch control information conversion unit 1001 and D1012 is input to the switch control information conversion unit 1002. In the switch control information conversion unit 1001,
<001>, which represents the switch control information “1” of D1011 in binary, is input to the conversion circuit of FIG.
0>. Since this is switch control information “2”, it is output as D1013. The switch control information conversion unit 1002 inputs <001>, which represents the switch control information “1” of D1012 in binary, to the conversion circuit of FIG. 14B and converts it into <011>. Since this is switch control information “3”, it is output as D1014.

In the unit switch 1009, the switch control information of the D1013 input from the physical input port 1 is “2”, so that it is output from the physical output port 3 and the switch control information of the D1014 input from the physical input port 2 is Since it is “3”, it is output from the physical output port 4. In this way, the D input from the logical input port 1
Since 1010 is output to the physical output ports 3 and 4 of the unit switch, it is output to the logical output port 2 as an output signal # 2.

Input signal # input from logical input port 2
The second data D1020 is bit sliced, and D1021 of the data is input to the switch control information conversion unit 1003, and D1022 is input to the switch control information conversion unit 1004. In the switch control information conversion unit 1003,
<011> expressing the switch control information “3” of D1021 in binary notation is input to the conversion circuit of FIG.
0>. Since this is switch control information “6”, it is output as D1023. The switch control information conversion unit 1004 inputs <011>, which represents the switch control information “3” of D1022 in binary, to the conversion circuit of FIG. 15B and converts it into <111>. Since this is switch control information “7”, it is output as D1024.

In the unit switch 1009, the switch control information of D1023 input from the physical input port 3 is “6”, so that it is output from the physical output port 7 and the switch control information of D1024 input from the physical input port 4 is Since it is “7”, it is output from the physical output port 8. In this way, the D input from the logical input port 2
Since 1020 is output to the physical output ports 7 and 8 of the unit switch, it is output to the logical output port 4 as an output signal # 4.

Input signal # input from logical input port 3
The data D1030 of No. 3 is bit sliced, of which D1031 is input to the switch control information conversion unit 1005 and D1032 is input to the switch control information conversion unit 1006. In the switch control information conversion unit 1005,
<010> expressing the switch control information “2” of D1031 in binary notation is input to the conversion circuit of FIG.
0>. Since this is the switch control information “4”, it is output as D1033. The switch control information conversion unit 1006 inputs <010>, which represents the switch control information “2” of D1032 in binary, to the conversion circuit in FIG. 14B and converts it into <101>. Since this is switch control information “5”, it is output as D1034.

In the unit switch 1009, the switch control information of D1033 input from the physical input port 5 is “4”, so that it is output from the physical output port 5 and the switch control information of D1034 input from the physical input port 6 is Since it is “5”, it is output from the physical output port 6. In this way, the D input from the logical input port 3
Since 1030 is output to the physical output ports 5 and 6 of the unit switch, it is output to the logical output port 3 as an output signal # 3.

Input signal # input from logical input port 4
The data D1040 of No. 4 is bit sliced, and D1041 of the data is input to the switch control information conversion unit 1007 and D1042 is input to the switch control information conversion unit 1008. In the switch control information conversion unit 1007,
<000>, which represents the switch control information “0” of D1041 in binary, is input to the conversion circuit of FIG.
0>. Since this is switch control information “0”, it is output as D1043. The switch control information conversion unit 1008 inputs <000>, which represents the switch control information “0” of D1042 in binary, to the conversion circuit of FIG. 15B and converts it into <001>. Since this is switch control information “1”, it is output as D1044.

In the unit switch 1009, since the switch control information of the D1043 input from the physical input port 7 is “0”, it is output from the physical output port 1 and the switch control information of the D1044 input from the physical input port 8 is Since it is “1”, it is output from the physical output port 2. In this manner, the D input from the logical input port 4
Since 1040 is output to the physical output ports 0 and 1 of the unit switch, it is output to the logical output port 1 as an output signal # 1.

In the case of operating as a 2 × 2 switch, the switch control information conversion operation is performed by converting the switch control information expressed by a binary number into the conversion form shown in FIGS. Convert by circuit.

In the 2 × 2 switch, the input signal #
1 and # 2 are input from the logical input ports 1 and 2, respectively. The logical input port 1 corresponds to the physical input ports 1 to 4 of the unit switch, and the logical input port 2 is the physical input ports 5 to 5 of the unit switch. Equivalent to 8. The output signals # 1 to # 4 are output to the logical output ports 1 and 2, respectively. The logical output port 1 corresponds to the physical output ports 1 to 4 of the unit switch, and the logical output port 2 is the output of the unit switch. These correspond to physical output ports 5-8.

Referring to the configuration shown in FIG. 11, data of input signal # 1 is bit-sliced and input to switch control information converters 1001 to 1004, and data of input signal # 2 is bit-sliced to switch control information. Conversion unit 10
05 to 1008. The switch control information included in the data of each of the input signals # 1 and # 2 input to the switch control information conversion units 1001 to 1008 is replaced with new switch control information by the respective conversion circuits illustrated in FIGS. .

For example, when outputting the data of the input signal # 1 input from the logical input port 1 to the logical output port 1, the data of the input signal # 1 is bit sliced to
Is input to the switch control information conversion units. In each switch control information conversion unit, the switch control information “0” is set to 2
<000> expressed in base number is input to each conversion circuit and converted. The conversion circuit of FIG. 14A converts the data to <000>, and outputs the switch control information “0” to the physical input port 1.
To enter. In the conversion circuit of FIG.
1>, and inputs the switch control information “1” to the physical input port 2. The conversion circuit in FIG. 15A converts the data into <010>, and inputs the switch control information “2” to the physical input port 3. The conversion circuit of FIG. 15B converts the data into <011>, and inputs the switch control information “3” to the physical input port 4.

The unit switch outputs to the physical output port 1 because the switch control information of the data input from the physical input port 1 is “0”, and the switch control information of the data input from the physical input port 2 is “0”. Since the switch control information of the data input from the physical input port 3 is “2”, it is output to the physical output port 3 and the data input from the physical input port 4 is “1”. Since the held switch control information is “3”, it is output to the physical output port 4. In this manner, the data input from the logical input port 1 is output to the physical output ports 1 to 4 of the unit switch, so that it is output to the logical output port 1 as an output signal # 1.

Input signal # input from logical input port 1
When outputting the data of 1 to the logical output port 2, the data of the input signal # 1 is bit sliced and input to the four switch control information converters. In each switch control information conversion unit, <001> in which the switch control information "1" is represented in a binary number is input to each conversion circuit and converted. FIG.
The conversion circuit of FIG. 4A converts the data into <100> and inputs the switch control information “4” to the physical input port 1. The conversion circuit of FIG. 14B converts the data to <101>, and outputs the switch control information “5” to the physical input port 2.
To enter. In the conversion circuit of FIG.
0>, and inputs the switch control information “6” to the physical input port 3. The conversion circuit of FIG. 15B converts the data into <111> and inputs the switch control information “7” to the physical input port 4.

The unit switch outputs to the physical output port 5 because the switch control information of the data input from the physical input port 1 is “4”, and outputs the switch control information of the data input from the physical input port 2 to “4”. 5 ”, it is output to the physical output port 6, and the switch control information of the data input from the physical input port 3 is“ 6 ”, so that it is output to the physical output port 7, and the data input from the physical input port 4 is Since the held switch control information is “7”, it is output to the physical output port 8. In this manner, the data input from the logical input port 1 is output to the physical output ports 5 to 8 of the unit switch, so that the data is output to the logical output port 2 as the output signal # 2.

Input signal # input from logical input port 2
In the case of outputting the data of No. 2 to the logical output port 1, the data of the input signal # 2 is bit sliced and input to the four switch control information conversion units. In each switch control information conversion unit, <000> in which the switch control information “0” is represented in a binary number is input to each conversion circuit and converted. FIG.
The conversion circuit of FIG. 4A converts the data into <000>, and inputs the switch control information “0” to the physical input port 5. The conversion circuit of FIG. 14B converts the data into <001> and outputs the switch control information “1” to the physical input port 6.
To enter. In the conversion circuit of FIG.
0>, and inputs this switch control information “2” to the physical input port 7. The conversion circuit of FIG. 15B converts the data into <011>, and inputs the switch control information “3” to the physical input port 8.

The unit switch outputs the switch control information of the data input from the physical input port 5 to the physical output port 1 because the switch control information of the data input from the physical input port 5 is “0”. Since the switch control information of the data input from the physical input port 7 is “2”, it is output to the physical output port 3 and the data input from the physical input port 8 is “1”. Since the held switch control information is “3”, it is output to the physical output port 4. In this manner, the data input from the logical input port 2 is output to the physical output ports 1 to 4 of the unit switch, so that the data is output to the logical output port 1 as an output signal # 1.

Input signal # input from logical input port 2
In the case of outputting the data of No. 2 to the logical output port 2, the data of the input signal # 2 is bit sliced and input to the four switch control information conversion units. In each switch control information conversion unit, <001> in which the switch control information "1" is represented in a binary number is input to each conversion circuit and converted. FIG.
The conversion circuit of FIG. 4A converts the data into <100> and inputs the switch control information “4” to the physical input port 5. The conversion circuit of FIG. 14B converts the data to <101>, and outputs the switch control information “5” to the physical input port 6.
To enter. In the conversion circuit of FIG.
0>, and inputs this switch control information “6” to the physical input port 7. The conversion circuit of FIG. 15B converts the data into <111> and inputs the switch control information “7” to the physical input port 8.

The unit switch outputs to the physical output port 5 since the switch control information of the data input from the physical input port 5 is “4”, and outputs the switch control information of the data input from the physical input port 6 to “4”. 5 ”, the data is output to the physical output port 6, and the switch control information of the data input from the physical input port 7 is“ 6 ”. The switch control information is output to the physical output port 7, and the data input from the physical input port 8 is Since the held switch control information is “7”, it is output to the physical output port 8. In this manner, the data input from the logical input port 2 is output to the physical output ports 5 to 8 of the unit switch, and is output to the logical output port 2 as the output signal # 2.

[0178]

According to the effects of the present invention described above, a plurality of switch sizes can be realized by changing the number of unit switches and the connection of input / output signals. Is proportional to the switch size, so that it can be realized at a cost corresponding to the switch scale.

The reason is that the bit slice processing is a method of processing parallel signals by a plurality of processing circuits arranged in parallel, and utilizes the feature that the number of bit slices can be arbitrarily selected. .

As one method of controlling the unit switch, a plurality of input / output ports are logically set to one in the unit switch.
That is, the input / output ports can be handled as one input / output port, and the number of input / output ports to be combined in the unit switch is changed by an external setting such as a hardware DC signal or firmware.

As another method, switch control information accompanying an input signal to each input port of a unit switch and indicating an output destination is processed before input to the unit switch. That is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a switch configuration to which a switch configuration method according to the present invention is applied;

FIG. 2 is a block diagram showing a case in which the N × N switch shown in FIG. 16 is applied to the (N / s) × (N / s) switch shown in FIG. 1;

FIG. 3 is a block diagram showing a method for converting switch control information according to one embodiment of the present invention;

FIG. 4 is an example of a conversion table of a switch control information conversion unit in FIG. 3;

FIG. 5 is a block diagram when an 8 × 8 switch is configured using FIG. 1;

FIG. 6 is a block diagram when a 4 × 4 switch is configured using FIG. 1;

FIG. 7 is a block diagram when a 2 × 2 switch is configured using FIG. 1;

FIG. 8 is a block diagram showing a main signal system of a switch configuration method according to an embodiment of the present invention.

FIG. 9 is a block diagram showing a case where an 8 × 8 switch in a conventional example is applied to the 4 × 4 switch shown in FIG. 6;

FIG. 10 is a block diagram showing a selection circuit of a switch configuration method according to an embodiment of the present invention.

FIG. 11 is a block diagram illustrating a method for converting switch control information according to an embodiment of the present invention.

12 is a conversion table example of a switch control information conversion unit in FIG. 11;

13 is an example of a conversion table of a switch control information conversion unit in FIG. 11;

FIG. 14 is a block diagram showing a conversion circuit of a switch control information conversion unit in FIG. 11;

FIG. 15 is a block diagram showing a conversion circuit of a switch control information conversion unit in FIG. 11;

FIG. 16 shows N × N of a bit slice configuration in a conventional example.
Block diagram showing switches

FIG. 17 is a block diagram showing a configuration example of an output buffer type switch of the ATM communication system in a conventional example.

[Explanation of symbols]

1-3, 101-103, 201-204, 301, 3
02,401,501,601,1009,1201
Unit switch S10, S110 Input signal # 1 (m-bit parallel signal) S20, S120 Input signal # 2 (m-bit parallel signal) S30 Input signal # (N / s) (m-bit parallel signal) S130 Input signal #N (m S40, S140 Output signal # 1 (m-bit parallel signal) S50, S150 Output signal # 2 (m-bit parallel signal) S60 Output signal # (N / s) (m-bit parallel signal) S160 Output signal #N (M-bit parallel signal) S510 input signal # 1 S520 output signal # 2 602 to 607 switch control information converter S610 input signal # 1 (m-bit parallel signal) S210, S310, S410 Input signal # 1 (8-bit parallel signal) S215, S350, S430 Output signal # 1 (8-bit parallel S220, S320, S420 Input signal # 2 (8-bit parallel signal) S225, S360, S440 Output signal # 2 (8-bit parallel signal) S230, S330 Input signal # 3 (8-bit parallel signal) S235, S370 Output Signal # 3 (8-bit parallel signal) S240, S340 Input signal # 4 (8-bit parallel signal) S245, S380 Output signal # 4 (8-bit parallel signal) S250 Input signal # 5 (8-bit parallel signal) S255 output signal # 5 (8-bit parallel signal) S260 Input signal # 6 (8-bit parallel signal) S265 Output signal # 6 (8-bit parallel signal) S270 Input signal # 7 (8-bit parallel signal) S275 Output signal # 7 (8-bit parallel signal) ) S280 Input signal # 8 (8-bit S285 Output signal # 8 (8-bit parallel signal) D1210 Data input from input signal # 1 D1220 Data input from input signal # 2 D1230 Data input from input signal # 3 D1240 Input signal # 4 Input data 701 to 708, 801 to 808 Cell buffer 709 Cell multiplexing circuit S711 to S718 Input signal S720 Signal obtained by cell multiplexing of input signals S711 to S718 S721 Signal obtained by converting S720 signal into bus S731 to S738 Data bus S721 Pulled signal S741 to S748 Output signal 811 to 818, 901 to 908 Selection circuit 821 Cell multiplexing circuit with 2-bit width 8 inputs 822 Cell multiplexing circuit with 4-bit width 4 inputs 823 Cell multiplexing with 8-bit width 2 inputs Circuit S811 S818 Input signal S821-S824 Signal obtained by combining two sets of input signals S811-S818 S831, S832 Signal obtained by combining four sets of input signals S811-S818 S841 Signal obtained by cell-multiplexing S811-S818 S842 S821-S824 is cell-multiplexed S843 A signal obtained by cell multiplexing of S831 and S832 S844 A signal obtained by making the S841 signal into a bus shape S845 A signal obtained by making the S842 signal into a bus shape S8461 A signal obtained by making the S843 signal into a bus shape S851-S858 A signal pulled from the data bus S841 ~ S864 Signal pulled from data bus S842 S871, S872 Signal pulled from data bus S843 S881-S888 Signals selected by selection circuits 811-818 S891-S898 Output No. S911 to S918 Write enable signal S921 to S928 Signal for actually controlling writing to cell buffer 1001 to 1008 Switch control information conversion unit D1010 Data input from input port 1 D1020 Data input from input port 2 D1030 Input port 3 D1040 Data input from input port 4 1111-1111, 1121-1123, 1131-
1133, 1141 to 1143 Conversion circuit S1111 to S1113, S1121 to S1123, S
1131 to S1133, S1141 to S1143 Original switch control information S1114 to S1116, S1124 to S1126, S
1134 to S1136, S1144 to S1146 Converted switch control information

Claims (1)

(57) [Claims] 1. N (N: an integer that satisfies N ≧ 2) input signals are respectively subjected to m (m: an integer that satisfies m ≧ 2) bit parallel expansion, and m-bit parallel expansion of the input signal is performed. Each is k (k: m is an integer satisfying k ≧ 2,
Is divided into (m / k) groups bit by bit, and k
The k-bit signals divided into (m / k) groups are input to (m / k) unit switch circuits that process bit parallel signals as a set of input / output signals, and are processed in parallel. And outputs the signal of each k bits from the (m / k) unit switch circuits. In an N × N switch of a bit slice configuration having N input sides and N output sides, the switch size is N × N, a (a: 1 ≦ a ≦ N) is obtained by using (m / k) unit switch circuits.
The input signal of the (th integer satisfying) is b (b: 1 ≦ b ≦ m)
The k-bit signal of the (/ integer satisfying / k) -th group is input to the a-th logical input port of the b-th unit switch circuit, and the switch size is (N / s) × (N / s) (s) : S ≧ 2
Is an integer that is a divisor of N), (m / (s × k)) unit switch circuits are used,
The c-th (c: an integer satisfying 1 ≦ c ≦ N / s) signal is
(S × (d−1) + t) (d: 1 ≦ d ≦ m / (s × k)
An integer that satisfies, t: an integer that satisfies 1 ≦ t ≦ s−1) th
The k-bit signal of the group
Input to the tth logical input port of the path, and the e (e: an integer satisfying 1 ≦ e ≦ N / s) th logical input port
The signal input from the input port is represented by f (f: 1 ≦ f ≦ N /
output to the (integer satisfying s) th logical output port
In the case, the unit switch circuit to which the e-th input signal is input
S physical input ports output f-th output signal
One-to-one to s physical output ports
Connected to the e-th input signal.
Switch control information indicating the output destination of the e-th input signal is
The unit switch circuit converts the physical input
Switches attached to the input signal input from each of the ports
N for distributing the input signal according to the switch control information.
A switch configuration method characterized by operating as a × N switch .