JP3001464B2 - Microprocessor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a VLSI (Very L
The present invention relates to a microprocessor device that performs microinstruction control using arge scale integration).

[0002]

2. Description of the Related Art In a conventional micro-instruction-controlled microprocessor device, a part of all micro-instructions is stored in a built-in ROM (read only memory) or a cache memory so that micro-instructions can be read at a high speed. Is becoming Also, Japanese Patent Application Laid-Open No. 63-68930 discloses a microprocessor device in which reading of a microinstruction is accelerated by storing the microinstruction in a control storage ROM and a control storage cache incorporated in the microprocessor device. Have been.

[0003]

In the conventional microprocessor device, it is necessary to remanufacture the chip when the contents of the microinstructions assigned to the control storage ROM are changed or a problem occurs. The microinstructions allocated to the storage ROM are limited to the minimum necessary basic instructions. Therefore, the conventional microprocessor device has a drawback that the use rate of the control storage cache is increased, and the performance of supplying microinstructions is reduced. Further, in the conventional microprocessor device, when the control storage ROM becomes unusable, there is no means for reading the microinstruction allocated to the control storage ROM, so that a physical failure of the control storage ROM When a problem occurs in the microinstruction allocated to the storage ROM, there is a disadvantage that the microprocessor device itself cannot be used. The present invention has been made under such a background, and can improve the performance of supplying micro-instructions, as well as control storage ROM.
It is an object of the present invention to provide a microprocessor device that can use the microprocessor device itself even when the device fails.

[0004]

Means for Solving the Problems The first aspect of the present invention, a main storage means for storing all the micro-instruction data corresponding to all microinstructions corresponding to the basic microinstruction of the whole microinstruction A first storage means exclusively for reading storing basic microinstruction data, and a microinstruction used at a usage frequency equivalent to the basic microinstruction data among all the microinstructions , causing a problem.
A readable and writable second storage means for storing quasi-basic micro-instruction data corresponding to a quasi-basic micro-instruction having a high probability of being generated, and a defect in the basic micro-instruction data stored in the first storage means Occurs,
By accessing the main storage unit, data corresponding to the basic microinstruction data is stored in the main storage unit.
Control means for reading the data from the memory and writing the data to the second storage means. According to a second aspect of the present invention, in the microprocessor device according to the first aspect, data corresponding to a micro-instruction other than the basic micro-instruction and the quasi-basic micro-instruction among all the micro-instructions is stored. It is characterized by comprising a third storage means. According to a third aspect of the present invention, in the microprocessor device according to the second aspect, the first storage means is a read-only memory, the second storage means is a random access memory, The storage means of No. 3 is a cache memory.

[0005]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a microprocessor device according to one embodiment of the present invention. In this figure, 1 is a microprocessor. 2 is an address bus 600 and a data bus 7
It is a main memory connected to the microprocessor 1 via 00 and stores all microinstructions.

FIG. 2 shows the microprocessor 1 shown in FIG.
FIG. 3 is a block diagram showing the configuration of FIG. In this figure, parts corresponding to the respective parts in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. Reference numeral 10 shown in FIG. 2 is a control storage index address generation unit that generates an address for indexing the control storage,
The control storage index address data 100 is output. 33
Is a control memory RO for storing a small amount of basic microinstructions.
M, and the basic micro-instructions are allotted in a limited manner among all the micro-instructions in consideration of the risk of chip remanufacturing. This control storage ROM 33
Outputs output data 303.

Reference numeral 32 denotes a control storage RAM (random access memory) for storing quasi-basic microinstructions. Here, the quasi-basic microinstruction is the control memory R described above.
This is a microinstruction used at a usage frequency equivalent to the basic microinstruction allocated to the OM 33 and having a high probability of occurrence of a malfunction. The control storage RAM 32 outputs output data 302.

A ROM 20 stores an address area of a basic microinstruction allocated to the control storage ROM 33.
This is an address area storage register. The ROM address area storage register 20 stores the ROM address data 200
Is output. The RA 21 stores an address area of the quasi-basic microinstruction allocated to the control storage RAM 32.
This is an M address area storage register. The RAM address area storage register 21 stores the RAM address data 20
Outputs 1.

Reference numeral 80 denotes a control storage cache memory, which comprises a cache address array 30 and a cache data array 31. These cache address array 30 and cache data array 31
Stores microinstructions other than the basic microinstructions and the quasi-basic microinstructions described above. The cache address array 30 outputs the output data 300, and the cache data array 31 outputs the output data 3
01 is output.

Reference numeral 40 denotes the ROM address data 2 described above.
00, RAM address data 201, output data 300
And a read data determination circuit for comparing the control storage index address data 100 with the read data. That is, the read data determination circuit 40 outputs the output data 303 from the control storage ROM 33 and the output data 303 from the control storage RAM 32.
02, output data 3 from the cache data array 31
01 and output data from the main storage device 2 (see FIG. 1), which data is to be selected, and the result of the determination is output as a data determination signal 400.

Reference numeral 60 denotes a main memory data reading unit which transmits a microinstruction of an address area stored in the RAM address area storage register 21 at the time of initialization through the address bus 600 and the data bus 700 to the main memory 2. (See FIG. 1). The main memory data reading unit 60 also reads from the main memory device 2 when the read data determination circuit 40 determines that the corresponding data does not exist in the control storage ROM 33, the control storage RAM 32, and the control storage cache memory 80. The microinstruction is fetched via the address bus 600 and the data bus 700.

Reference numeral 41 denotes output data 303 and output data 3
02, the data corresponding to the determination result indicated by the data determination signal 400 is selected from the output data 301 or the output data (microinstruction) of the main storage device 2, and the selected data is output as the output data 401.

Reference numeral 50 denotes a microinstruction supply unit for supplying a microinstruction obtained from the output data 401 as output data 500. Reference numeral 51 denotes a microinstruction processing unit that processes a microinstruction obtained from the output data 500.

Next, the operation of the microprocessor device according to the above-described embodiment will be described. First, at the time of initialization, the RAM address area storage register 21
When the RAM address data 201 is input to the main storage data reading unit 60, the main storage data reading unit 60
The main storage device 2 is accessed via the address bus 600 and the data bus 700 based on the RAM address data 201. Thereby, the RAM address data 20
The data of the microinstruction is read by the main storage data reading unit 60 from the address of the main storage device 2 corresponding to the RAM area address obtained from the address 1.

The microinstruction data is written in the control storage RAM 32 as the above-described semi-basic microinstruction data. Here, an address for allocating the above-described quasi-basic microinstruction is allocated to the RAM address area storage register 21. Also,
The RAM address area storage register 21 has a control memory R
If there is a problem with the OM 33, the control storage ROM 33
It is also possible to set an address area (basic microinstruction). Therefore, in this case, the control storage ROM 3
Control micro-instructions stored in RAM 3
32. That is, when the RAM address data 201 corresponds to the basic instruction and the read data determination circuit 40 selects the RAM address data 201, the main memory data reading unit 60 Access the storage device 2. Thus, after the data corresponding to the basic microinstruction is read from the main storage device 2 via the data bus 700 from among all the microinstructions, the basic microinstruction is written to the control storage RAM 32.

Next, when the control storage index address generation unit 10 generates the control storage index address and outputs it as the control storage index address data 100, the cache address array 30, the cache data array 31, the control storage RAM 32, and the control storage The address of the ROM 33 is indexed. Thus, output data 300, output data 301, output data 302, and output data 303 are output, respectively.

In synchronization with the above-described indexing operation, the read data determination circuit 40 compares the control storage index address data 100, the ROM address data 200, the RAM address data 201 and the output data 300. That is, the read data determination circuit 40 outputs the output data 3
03, the output data 302, the output data 301 or the output data of the main storage device 2 (see FIG. 1), which data is to be indexed is determined, and the determination result is output as a data determination signal 400.

Here, when the output data of the main storage device 2 is selected by the read data judgment circuit 40, the main storage data reading section 60 accesses the main storage device 2 via the address bus 600. Thus, after the data of the microinstruction is read from the main storage device 2 via the data bus 700, the data of the microinstruction is stored in the cache data array 31.

The data selection section 41 outputs the output data 3
03, the output data 302, the output data 302, and the output data of the main storage device 2, the data determination signal 400
, Ie, the data selected by the read data determination circuit 40, and outputs the selected data as output data 401. As a result, the microinstruction supply unit 50 outputs the output data 401 as the output data 500, and then the microinstruction processing unit 51 executes the microinstruction obtained from the output data 500.

[0020]

As described above, according to the present invention,
Since the readable and writable second storage means is provided, the capacity of the basic microinstruction data stored in the first storage means can be increased. Therefore, according to the present invention, the supply performance of microinstructions can be improved. Further, according to the present invention, the control means controls the second
Since the storage contents of the storage means can be rewritten,
Even if a problem occurs in the quasi-basic microinstruction stored in the first storage means, the effect is obtained that the apparatus itself can be used.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a microprocessor device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a microprocessor 1 shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Microprocessor 2 Main storage device 10 Control storage index address generation unit 20 ROM address storage register 21 RAM address storage register 30 Cache address array 31 Cache data array 32 Control storage RAM 33 Control storage ROM 40 Read data determination circuit 41 Data Selection unit 50 Micro instruction supply unit 51 Micro instruction processing unit 60 Main memory data reading unit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 9/22 370 G06F 9/22 380

Claims (3)

(57) [Claims] 1. A total micro main storage means for storing all microinstructions data corresponding to the instruction, the entire microinstruction basic microinstruction first read-only storing a basic microinstruction data corresponding to one of the Storage means, a microinstruction used at a usage frequency equivalent to the basic microinstruction data among all the microinstructions ,
Readable and writable second storage means for storing quasi-basic micro-instruction data corresponding to a quasi-basic micro-instruction having a high probability of occurrence of a defect, and the basic micro-instruction data stored in the first storage means When a problem occurs in the basic microinstruction data , by accessing the main storage means ,
A microprocessor configured to read corresponding data from the main memory and write the data to the second memory. 2. The apparatus according to claim 1, further comprising: third storage means for storing data corresponding to micro-instructions other than said basic micro-instruction and said quasi-basic micro-instruction among said all micro-instructions. A microprocessor device as described. 3. The storage device according to claim 2, wherein the first storage unit is a read-only memory, the second storage unit is a random access memory, and the third storage unit is a cache memory. 3. The microprocessor device according to 2.