JP3007095B2 - Method of forming fine pattern - Google Patents

Description

The present invention relates to a method for forming a fine pattern, and more particularly, to a method for forming a fine resist pattern on a semiconductor substrate by electron beam drawing. The present invention also relates to a method for manufacturing a semiconductor device using such a method for forming a fine pattern.

<Prior Art> As is widely known, a field effect transistor (FE)
To improve the performance of T), it is extremely important to reduce the gate length (Lg).

When forming a gate of an FET, a common method is to first apply a single-layer resist on a semiconductor substrate, draw an electron beam on a portion where a gate is to be formed, and form an opening in the resist. There is a method of removing the metal on the resist by performing lift-off after depositing and vapor-depositing a metal thereon, while leaving the metal on the substrate in the opening as a gate electrode. However, in this method, as shown in FIG. 5, when a gate 12 having a gate length Lg of about 0.25 μm or less is formed on a semiconductor substrate 11, the tip 12a of the gate electrode is tapered when lift-off is performed. As a result, the gate resistance Rg increases, and the high-frequency characteristics, particularly the noise characteristics of the FET are impaired.

Recently, in order to reduce the gate resistance Rg, as shown in FIGS. 4 (a) to 4 (c), a PC having a T-shaped cross section (hereinafter, referred to as a “T-shaped”) has been proposed by PC Chao et al. (Referred to as 1983 IED, Proceding (IEDM, Prcoceeding) 27-5, P613). First, the semiconductor substrate
A low-sensitivity lower resist 28 made of PMMA (polymethyl methacrylate), a high-sensitivity middle resist 27 made of P (MMA-MAA) copolymer, and a medium-sensitivity upper resist made of PMMA 26 are sequentially stacked, and a portion where the gate 25 is to be formed is drawn substantially vertically by an electron beam from above (FIG. 4 (a)). Then, as shown in FIG. 4 (b), the resist in the portion irradiated with the electron beam (indicated by a broken line in FIG. 4 (a)) is developed and removed, and the above three-layer resists 26 and 27 are removed. , 28 are formed. The width of the opening 23 becomes narrower, wider, and medium in order from the substrate 21 side in accordance with the sensitivity of the resist in each layer. Subsequently, a metal 24 is deposited as a material of the gate 25 from above the upper resist 26. At this time, the metal 24a deposited in the opening 23 comes into contact with the substrate surface 21a and has a shape in which both wings 24b, 24b of the cross section spread into the opening 23m of the middle-layer resist 27. Then, as shown in FIG. 4 (c), the resists 26, 27, 28 of each layer are dissolved and lifted off to form a T-shaped gate 25 having both wings 25b, 25b. Thus, the gate resistance Rg is reduced.

Also, when performing electron beam writing, a vector scan type spot beam writing apparatus having a thermionic emission type emitter made of W (tungsten) or LaB ₆ (lanthanum hexaboride) material is used to emit an electron beam. are doing. The emitter diameter is about 10 μm or more,
The electron beam emitted from the emitter is narrowed by an electron optical system (reduction ratio of 10 or more) to have a submicron beam diameter.

<Problem to be Solved by the Invention> However, when the above-described conventional method of forming a T-shaped gate is applied to, for example, a HEMT (high electron mobility transistor) having a gate length of 0.1 μm, the gate resistance Rg is certainly reduced. Although effective, the following problems have been found. First, the input capacitance Cgs and the feedback capacitance Cgdt of the HEMT become larger than designed values. Second, there is large inter-element variation in the input capacitance Cgs. Third, the source resistance Rs must be increased from the design aspect. And therefore the transconductance gm is reduced.

According to the analysis of the inventor, the input capacitance Cgs and the feedback capacitance Cgd are increased by the following mechanism. The electron beam is scattered in the resist of each layer and in the substrate 21 (proximity effect), and as shown in FIG.
The opening end surfaces 28a of the 28 have a forward taper with respect to the substrate surface 21a. Therefore, the two wings 2 of metal 24a deposited on this
4b and 24b are reversely tapered and become the two wings 25b and 25b of the T-shaped gate 25 as they are, so that these two wings 25b and 25b and the substrate surface 21
The distance from a becomes shorter, causing parasitic capacitance. Also, due to the proximity effect, the openings 23u and 23m of the upper and middle resists 26 and 27 are 0.8 μm and 1.0 μm, respectively.
It spreads more than necessary to the extent that both wings of the above gate 25
25b, 25b spread accordingly, further increasing the parasitic capacitance. Next, a point at which the variation in the input capacitance Cgs between elements was large was observed by a scanning electron microscope (SEM).
Since a and 28a have forward taper and thin film thickness,
It has been found that the mechanical strength is weakened, and the end faces 28a, 28a are damaged in the deposition process of the metal 24, causing a variation in the gate length Lg. Finally, the reason why the source resistance Rs is large is that the two wings 25 of the T-shaped gate 25
This is because the source and the gate must be separated from each other in design so that the source and the gate do not come into contact with each other, because b and 25b spread more than necessary. Since the opening end of the lower resist 28 is thin, a gate is provided on a groove formed by etching using the resist 28 as a mask (recess gate structure) to prevent the contact, and the source and the gate are brought close to each other. Because they cannot do it.
As described above, there are many problems due to the shape of the opening 23 penetrating the resists 26, 27, and 28 of each layer.

By the way, the shape of the opening 23 is formed in accordance with the amount of charge accumulated in the resist when the electron beam is irradiated. As is known, for an electron beam whose intensity distribution is represented by a Gaussian distribution in the radial direction, the accumulated charge distribution F (r) is approximated by the following equation (1).

F (r) = K {exp (−r ² / α ² ) + (ηα ² / β ² ) exp (−r ² / β ² )} (1) In equation (1), the first term is forward scattering. , The second term indicates the contribution due to backscattering. Here, α is the incident beam size, η is the ratio of the backscattered absorbed energy to the forward scattered absorbed energy, and β is the backscattered absorbed energy distribution.
From the equation (1), if the incident beam size α is reduced,
It can be seen that the accumulated charge distribution F (r) becomes sharp. However, if the incident beam size α is simply reduced, the beam current is reduced in proportion to this, and the productivity is reduced, making it unusable for practical use.

Therefore, an object of the present invention is to suppress the above-mentioned proximity effect, thereby increasing the aspect ratio (ratio of height to width), optimizing the width of the openings of the upper and middle resists, and forming the opening end face of the lower resist on the substrate. It is possible to form a small T-shaped gate with both wings by increasing the mechanical strength by making it almost perpendicular to the surface, and it is possible to adopt a recess gate structure, and thus to produce a high-performance FET. An object of the present invention is to provide a practical method for forming a fine pattern. Another object of the present invention is to provide a method for manufacturing a semiconductor device using such a method for forming a fine pattern.

<Means for Solving the Problems> In order to achieve the above object, a method for forming a fine pattern according to the present invention comprises depositing a low-sensitivity first resist on a semiconductor, and forming a sensitivity on the first resist. After depositing a second resist having a high sensitivity, and further depositing a third resist having a medium sensitivity on the second resist, a pattern to be formed is exposed to a focused electron beam emitted from a thermal electric field type emitter. Wherein the thermal field emitter is made of zirconia-coated tungsten, and the tip diameter of the emitter is in the range of 0.4 μm to 0.6 μm.

Further, a method of manufacturing a semiconductor device according to the present invention includes the method of forming a fine pattern.

Further, a method of manufacturing a semiconductor device according to the present invention is characterized in that after forming a fine pattern by the method for forming a fine pattern, the semiconductor is etched using the first resist as a mask.

<Operation> When the emitter diameter of the electron gun is reduced, the bright spot of the electron beam (crossover occurring near the electron gun) decreases,
On the other hand, when the far-field pattern is widened and the beam convergence is lost, the convergence is increased, but the bright spot becomes large and the current density is reduced. Therefore, when electrons are emitted with the emitter diameter approximately equal to the width of any of the openings to be formed, the size of the bright spot is optimized. By reducing the reduction ratio of the electron optical system (the size of the bright spot / the size of the irradiation spot) to about one digit as compared with the conventional case, the aberration of the electron beam is reduced, and The aperture angle of the beam with respect to the irradiation direction becomes smaller.

According to the experiment of the present inventor, it is made of zirconia-coated tungsten and has an emitter tip diameter of 0.4 μm to 0.6 μm.
When a pattern to be formed is exposed on a laminated three-layer resist using a focused electron beam emitted from a thermal electric field type emitter within a range of m, the proximity effect is suppressed, and the conventional case is used. The widths of the openings of the upper and middle resists are smaller and optimized than those of the first embodiment, and the opening end faces of the lower resists are substantially perpendicular to the substrate surface. That is, the aspect ratio increases. Therefore, when forming a T-shaped gate by depositing a metal from above the resist, the spread of the two wings is suppressed, and the distance from the substrate surface is increased, so that the parasitic capacitance is reduced. Further, the thickness of the opening end of the lower resist is increased and the mechanical strength is increased, so that the variation of the gate length Lg is suppressed, and the recess gate structure can be adopted.

Further, according to the method of manufacturing a semiconductor device of the present invention, a semiconductor device having a fine pattern is manufactured with good reproducibility.

<Examples> Hereinafter, the method for forming a fine pattern according to the present invention will be described in detail with reference to examples.

FIGS. 1A to 1E show a first embodiment of the above-mentioned fine pattern forming method.

On a GaAs substrate 100, a low-sensitivity lower resist 10 made of methacrylic acid / phenyl methacrylate copolymer is used.
1, High-sensitivity middle-layer resist 102, Medium-sensitivity upper-layer resist 103
Are laminated as follows (FIG. 1 (a)). It is also possible to insert inorganic insulating film or a polyimide, such as SiO _2, SiN _X, an organic insulating film such as photoresist between the substrate 100 and the lower layer resist 101.

First, a 25.4 mol% solution of a methacrylic acid component (5% by weight methylcellosolve acetate solution) was applied as a low-sensitivity lower resist 101 on the GaAs substrate 100 at a rotation speed of 2000 r.
After spin coating at pm and applying, baking is performed at 230 ° C. for 30 minutes. The thickness of the lower resist 101 after baking is 0.15
μm. Next, a 5.7 mol% solution of a methacrylic acid component (8 wt% isoamyl ketone solution) is spin-coated at a rotation speed of 2000 rpm as a high-sensitivity middle layer resist 102, and baked at 230 ° C. for 30 minutes. The thickness of the middle layer resist 102 after baking was 0.45 μm. Next, a 20.0 mol% methacrylic acid component solution (5% by weight ethyl cellosolve solution) was used as the upper resist 103 at a rotation speed of 5000 rpm.
Spin coat at m. and bake at 230 ° C for 30 minutes. The thickness of the upper layer resist 103 after baking was 0.1 μm. The thickness of the entire three-layer resist was 0.7 μm, and no mixing of the resist was observed at the interface between the respective layers.

Next, as shown in FIG. 1 (b), the sample 200 is irradiated with an electron beam using a predetermined electron beam drawing apparatus.

As shown in FIG. 3, the electron beam writing apparatus includes a thermal field emission type emitter 201, an anode 202, an astigmatism correction lens 203, and second, third, and fourth electrostatic lenses 204, 205, Two
06, a beam blanker 208, a movable stop 209, and a moving stage 207 on which the sample 200 is mounted, between the third and fourth electrostatic lenses. The emitter 201 is a thermal field emission type emitter made of zirconia-coated tungsten, and has an optimum emitter diameter of 0.4 to 0.6 μm based on the results of various drawing tests performed by the inventors. The temperature of the emitter is 1800K, and the voltage of the anode 202 is 4-6K.
When V was set, a beam current with little change over time was obtained. Further, the reduction ratio of the electron optical system composed of each lens is set to 1, and the incident angle of the beam with respect to the surface of the sample 200 is set to 0.8.
mrad. Then, acceleration voltage 25KV, beam amount 1nA,
A line pattern is drawn under a drawing condition of a beam diameter of 300 mm and a line irradiation amount of 2.0 nC / cm.

As described above, when an electron beam is emitted from an emitter having a diameter approximately equal to the width of the opening 106 to be formed in each layer resist of the sample 200 (in this case, 0.1 to 0.6 μm), a bright spot
The size of 210 is reduced and optimized. Since the reduction ratio of the electron optical system is suppressed to 1, the aberration of the electron beam can be reduced, and the aperture angle of the beam with respect to the irradiation direction can be reduced. For this reason,
When irradiating the three layers of resists 101, 102, and 103, the proximity effect can be suppressed and the aspect ratio can be increased.

Next, dimethylacetamide 20% and butyl cellosolve
A first development process is performed at 23 ° C. for 180 seconds using a mixed solution of 80%, and then a second development process is performed at 23 ° C. for 120 seconds using a mixed solution of 80% methyl isobutyl ketone and 20% ethylcyclohexane. Then, a rinsing process was performed at 23 ° C. for 30 seconds using ethylcyclohexane, and FIG.
As shown in FIG. 5, an opening 106 penetrating the above three layers of resists 101, 102, 103 is formed.

In the above, as a result of using an electron beam lithography apparatus in which the emitter diameter was appropriately adjusted, the width of each opening 106u, 106m of the upper layer and the middle layer resists 103, 102 was 0.2 to 0.4 μm, 0.4 to 0.4, It was as small as 0.6 μm, and could be optimized. Further, the width of the opening 106l of the lower resist 101 was set to about 0.1 μm, and the end faces 101a, 101a could be made substantially perpendicular to the substrate surface 100a.

Subsequently, as shown in FIG.
Then, Al104 having a thickness of 0.6 μm is deposited using an electron beam vapor deposition machine. The Al 104a deposited in the opening 106 comes into contact with the substrate surface 100a, and the two wings 104b, 104b have a shape spread in the opening 106m of the middle layer resist 102. The width of each opening 106m, 106u of the upper and lower resists 103, 102 is,
Since it is smaller than the conventional case,
The spread of 4b and 104b is suppressed, and both become about 0.2 μm in width. Further, since the film thickness of the opening end of the lower resist 101 is substantially the same as the original film thickness, the distance between the two wings 104b, 104b and the substrate surface is set to about 0.15 μm as designed,
Variations in the gate length Lg can be suppressed. Further, since the three-layer resists 101, 102, and 103 are made of methacrylic acid / phenyl methacrylate copolymer, the mechanical strength is increased as compared with a conventional resist made of PMMA, and the variation in gate length can be suppressed. it can.

Then, as shown in FIG. 5 (e), the three layers of resists 101, 102 and 103 are dissolved in an acetone solution, and
04 is lifted off to form a T-shaped gate 105. In this way, it is possible to form a T-shaped gate having a good shape with the gate length Lg ≒ 0.1 μm, the blade length L ≒ 0.2 μm, and the height 0.6 μm on the substrate surface 100a.

FIGS. 2 (a) and 2 (b) show a second embodiment in which the method for forming a fine pattern according to the present invention is applied to manufacture of an HEMT.

First, as shown in FIG. 2A, a non-doped GaAs / AlGaAs superlattice buffer layer 112 having a thickness of 0.2 μm and a thickness of 0.025 μm are formed on a semi-insulating GaAs substrate 111 having (100) as a main surface.
m GaAs channel layer 120 and 0.002 μm thick undoped
AlGaAs layer 121, thickness 0.05μm, carrier concentration 2 × 10 ¹⁸ cm
^-3 n-type AlGaAs layer 113 and 0.1 μm thick n-type GaAs layer 114
Are sequentially grown and stacked at a temperature of 580 ° C. by a molecular beam epitaxy method (MBE).

Next, a lower resist 133 having a thickness of 0.1 μm and a thickness of 0.45 μm were formed on the n-type GaAs layer 114 as in the first and second embodiments.
μm middle resist 132, 0.15μm thick upper resist 13
1 are laminated, electron beam lithography is performed, and a first developing process, a second developing process, and a rinsing process are performed to form an opening 122 penetrating the above three layers of resist.

Subsequently, using the lower resist 133 as a mask, the n-type GaAs layer 114 is formed using phosphoric acid and an aqueous solution of hydrogen peroxide.
And etch the top of n-type AlGaAs layer 113 to a depth of
A recess groove 119 of 0.11 μm is formed. At this time, unlike the conventional case, since the thickness of the opening end portion 133a of the lower resist 133 is not thin, a good recess groove 11 is designed as designed.
9 can be formed.

Next, as shown in FIG. 3 (b), in the same manner as in the first to third embodiments, Al having a thickness of 0.6 μm is deposited and lift-off is performed to remove the n-type AlGaAs layer in the recess groove 119. On the etched surface 113a of 113, the gate length is 0.1 μm and the wing length is 0.15 μ
A T-shaped gate 115 having a height of 0.3 m and a height of 0.3 m is formed.

On the n-type GaAs layer 11A on both sides of the T-shaped gate 115, a 0.1 μm thick Au—Ge Ni 0.05 μm thick and a 0.1 μm thick A
u, respectively, and in a hydrogen stream at a temperature of 400 ° C, 1
The source 116 and the drain 117 are formed by performing heat treatment for minutes. Furthermore, Ti / Au with a film thickness of 0.1 μm and 1.0 μm respectively
The wiring / pads 118 having the two-layer structure are formed.

The HEMT manufactured in this manner has a cutoff frequency fT = 60GH.
z, the transconductance gm = 60 mS, the input capacitance Cgs = 150 fF, the source resistance Rs = 1 Ω, the gate resistance 2 Ω, and the maximum transconductance 500 mS / mm, exhibiting extremely good performance.

<Effects of the Invention> As is clear from the above, according to the method for forming a fine pattern of the present invention, the proximity effect can be suppressed in the laminated three-layer resist, the aspect ratio can be increased, and the upper and middle resists can be formed. By optimizing the width of the opening and making the opening end face of the lower resist substantially perpendicular to the substrate surface, the mechanical strength can be increased. Therefore, a small T-shaped gate having both wings can be formed with high accuracy, and a recess gate structure can be employed, and thus a high-performance FET can be manufactured.

Further, according to the method for manufacturing a semiconductor device of the present invention, a semiconductor device having a fine pattern can be manufactured with good reproducibility.

[Brief description of the drawings]

FIGS. 1A to 1E show the steps of a first embodiment of the method for forming a fine pattern according to the present invention. FIGS.
(B) is a diagram showing a process of a second embodiment in which the above-described method for forming a fine pattern is applied to manufacture of an HEMT, and FIG. 3 is a diagram showing a configuration of an electron beam drawing apparatus used for the method for forming a fine pattern. FIG. 4 is a view showing the steps of a conventional method for forming a T-shaped gate, and FIG. 5 is a sectional view showing the structure of the conventional gate. 100 semiconductor substrate, 101,133 lower resist, 102,132 middle resist, 103,131 upper resist, 104 Al, 105,115 T-shaped gate, 106,122 opening, 111 semi-insulating GaAs Substrate, 112: GaAs / AlGaAs super lattice buffer layer, 120: GaAs channel layer, 121: undoped AlGaAs layer, 113: n-type AlGaAs layer, 114n-type GaAs layer, 116: source, 117: drain, 118: pad, 119: recess groove, 200: sample, 201: emitter, 207: moving stage, 210: bright spot.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-77370 (JP, A) JP-A-55-105326 (JP, A) JP-A-56-406536 (JP, A) JP-A 54-105 161263 (JP, A) JP-A-60-79636 (JP, A) JP-A-64-12450 (JP, A) JP-A-1-112730 (JP, A) JP-A-56-69625 (JP, A) 56-61960 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/027 G03F 7/26

Claims (3)

(57) [Claims] 1. A low-sensitivity first resist is deposited on a semiconductor, a high-sensitivity second resist is deposited on the first resist, and a medium-sensitivity is deposited on the second resist. After depositing the third resist, a method for forming a fine pattern in which a pattern to be formed is exposed by a focused electron beam emitted from a thermal field emitter, wherein the thermal field emitter is made of zirconia coated tungsten; And emitter tip diameter is 0.4μm to 0.6μm
A method for forming a fine pattern, wherein 2. A method for manufacturing a semiconductor device, comprising the method for forming a fine pattern according to claim 1. 3. A method for manufacturing a semiconductor device, comprising: forming a fine pattern by the method for forming a fine pattern according to claim 1; and etching the semiconductor using the first resist as a mask.