JP3007253B2 - Multi-level drive circuit for display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device driving circuit,
Above all, it is used for a driving circuit of an active matrix type liquid crystal display device which performs gradation display.

[0002]

2. Description of the Related Art A conventional active matrix type liquid crystal display device (hereinafter, referred to as a liquid crystal display device)
The driving circuit of the display device) will be described. The display device is
The display unit includes a display unit in which pairs of a plurality of picture elements and switching elements are arranged in a matrix, and a driving circuit that drives the display unit for display. The display unit is configured to include a plurality of data lines for respectively supplying image data signals for display to the plurality of switching elements, and a plurality of gate lines for driving on / off the plurality of switching elements for each row. You.
Hereinafter, the digital drive circuit will be described first. FIG.
Is a block diagram of the conventional digital drive circuit 210 corresponding to one output. This drive circuit 210 is a circuit for realizing eight gradation displays corresponding to 3-bit display data. As an actual drive circuit, a large number of circuits shown in FIG. 27 are used for each data line. When a plurality of circuits are further used, a plurality of drive circuits 210 corresponding to FIG. 1 exist as many as the number M of data lines of the display section. FIG. 28 is a timing chart for explaining the operation of this drive circuit. The image data corresponding to one horizontal scanning period of the display unit is once taken into the sampling data storage means Msmp (i) of FIG. 27 by the sampling pulse Tsmp (i) given at an appropriate time, and the picture data of one horizontal line is displayed. At an appropriate time after all the data corresponding to the data is sampled, the data is simultaneously transferred to the output holding means MH (i) by an output pulse OE (i) given from a control circuit (not shown), and the output selection circuit D
Input to EC. Here, the symbol i is i
This indicates that the signal is a circuit or a signal corresponding to the data line.

An output selection circuit DEC is provided with output holding means MH
One of the analog switches ASW0 to ASW7 connected to the eight gradation voltages V0 to V7 input from the outside of the drive circuit 210 in accordance with the value of the image data held and output in (i). One is turned on, one of the gradation voltages V0 to V7 is selected and output, and the data line is driven. For example, when the value of the image data is 3, the analog switch ASW3 is turned on, and the gradation voltage V3 is output.

FIG. 2 is a block diagram corresponding to one output of a 4-bit driving circuit 220 when designing based on the conventional method.
It is shown in FIG. This circuit is provided with the sampling data storage means Msmp shown in FIG. 27 as the number of bits of the image data increases.
(I), output holding means MH (i), gradation voltages V0 to V
7 and the number of bits of the analog switches ASW0 to ASW7 have increased. In such a conventional technique, the same number of gradation voltages as the number of gradations is required. Therefore, when the number of bits of the image signal increases and the number of gradations of the image displayed on the display unit increases, the number of gradation voltages becomes enormous, and the configuration of the circuit for generating the gradation voltages increases. Problem arises.

In order to solve this problem, the inventor of the present invention has invented a multi-gradation driving method which does not require a gradation power supply, and has already filed an application.

Next, the contents will be briefly described.

FIG. 30 is a block diagram corresponding to one output of a 4-bit drive circuit 230 having a configuration based on the present invention, which is the basis of the present invention, and corresponds to the circuit of FIG. 29 according to the prior art. . In the basic configuration, a 4-bit sampling data storage unit Msmp (i) corresponding to 4-bit image data and an output holding unit MH
(I), and an AND circuit AND0 is provided in place of the conventional analog switches ASW0 to ASW15 of FIG.
~ AND15 are used. 4-bit decoding circuit DE
Outputs s0 to s15 of C are connected to one input terminals of corresponding AND circuits AND0 to AND15, respectively.
Also, 16 signals of duty signals T0 to T15 are input from the outside of the drive circuit 230 shown in FIG. 30, and are connected to the other input terminals of the AND circuits AND0 to AND15, respectively. AND circuit AND0
The output of AND15 is input to a 16-input OR circuit 0R, and its output is input to a buffer circuit OB.
The output is the output of the drive circuit 230 in FIG. The buffer circuit OB is driven by power supply voltages VSH and VSL different from other logic circuits such as the sampling data storage means Msmp (i) and the output holding means MH (i).

FIG. 31 shows the duty signals T0 to T1.
5 shows the waveform. Thus, the duty signal T
1 to T14 are periodic signals having a duty ratio of m (k): n (k). For example, in the driving example of FIG. 28, a plurality of signals are output during one output period such as a pulse interval of the driving pulse OE. It is a signal that vibrates twice. Here, the duty ratio m
(K), n (k)

[0009]

When the duty ratios m (k) and n (k) are determined so that m (k) + n (k) = constant, each variable m (k) (k = 1, 2,...) About

[0010]

The relationship of m (1)> m (2)> m (3) >>...> M (14) holds. Also, duty signals T0, T1
Numeral 5 is a high-level or low-level constant level signal during one output period.

The driving circuit 230 of FIG. 30 operates as follows. Considering the case where the value of the image data is 4, only the output s4 of the decoding circuit DEC becomes high level, and only the duty signal T4 passes through the AND circuit AND4.
The signal is output after passing through the OR circuit OR and the buffer circuit OB. As a power supply of the buffer circuit OB, a power supply voltage VS
Since H and VSL are supplied, the output O (i) of the buffer circuit OB has the same waveform as the duty signal T4 and oscillates between the power supply voltages VSH and VSL as shown in FIG. .

Similarly, in accordance with the value of the image data, the AND circuits AND0 to AND0 to A
One of the waveforms of the duty signals T0 to T15 is selected, and the output O
The waveform of (i) is determined. That is, when the value of the image data is 0 or 15, the output O (i) becomes a constant voltage corresponding to either the power supply voltage VSH or the power supply voltage VSL, and when the image data value is 2 to 14, The output O (i) outputs the duty signals T2 to T14 between the power supply voltages VSH and VSL.
Oscillates with any of the corresponding waveforms.

Incidentally, such power supply voltages VSH and V
When a voltage oscillating with any of the waveforms of the duty signals T2 to T14 during SL is output, what voltage is applied to the picture element of the display unit will be discussed below.

As an example, a periodic function such as a periodic function having a period of 2π can be represented by a Fourier series represented by the following equation if the function value is finite and can be integrated. It is described in the introduction, Chapter 6, etc., and is well known.

[0015]

(Equation 3)

The first term on the right side of this equation is a periodic function f (x)
And the periodic function f (x) is a voltage waveform when the periodic function f (x) is a voltage waveform. By the way, since it is clear that an actual voltage waveform can be integrated, all voltages that change periodically can be expressed by the Fourier series. That is, it can be seen that the periodically fluctuating voltage is a waveform in which the average value, which is the average voltage of one cycle, and the fundamental cycle voltage and its harmonics are added indefinitely. Therefore, when the driving circuit outputs the periodic voltage, if the fundamental periodic component and the harmonic component of the periodic voltage can be sufficiently suppressed, the average value voltage which is the DC component of the periodic voltage is given to the picture element of the display unit. It will be.

By the way, various capacitance components and resistance components exist in the display section, particularly in the signal path from the output of the drive circuit of the active type liquid crystal display device to the picture element. When these capacitance components and resistance components are viewed as the load of the drive circuit, they have the characteristics of a high-frequency filtering circuit (low-pass filter, LPF), and by appropriately setting the period of the periodic voltage,
The periodic component of the periodic voltage can be sufficiently suppressed, and an average value as a DC voltage is applied to the picture element.

By the way, as shown in FIG. 31, the duty ratio m (4): n is set between the power supply voltages VSH and VSL.
The average value VA of the voltage oscillating in (4) is

[0019]

(Equation 4)

It is obvious that Therefore, by appropriately setting the values of the variables m (4) and n (4), an arbitrary voltage between the power supply voltages VSH and VSL can be applied to the picture element.

Similarly, the duty signals T1 to T in FIG.
By appropriately setting the duty ratio of the 14 waveforms in advance, a driving circuit capable of applying an appropriate voltage corresponding to values 0 to 15 of 4-bit image data to picture elements, that is, 4-bit 16 gradations Can be realized.

The operating mechanism of the oscillating voltage driving method is described in the following paper.

"TFT-LCDs Using New
ly Designed 6-bit Digital
Data Drivers "SID 93 DIGES
T p11-p15

[0024]

As described above, FIG.
The invention of the prior application whose circuit example is shown in FIG. 29 is an invention which does not require a large number of power supplies for gradation, which were required in the prior art shown in FIG. However, in the circuit examples of the invention of the patent application shown in FIGS. 30 and 31, there is a problem that the same number of gradation signals as the number of gradations is required. This problem does not become a serious problem when, for example, a driving circuit having about three bits of image data is used. This is because only eight gradation signals are required at most. However, when the number of bits exceeds 3 bits, a serious problem occurs immediately.

The reason is that if the image data is 4 bits, 16
This is because if the image data is 6 bits, 64 gradation signals are required. In addition, since each of the gradation signals needs to have an average voltage corresponding to the image data, the more the number of gradation signals increases, the more delicate the adjustment of the signal level between the gradation signals becomes. It is inevitable that sex will deteriorate.

The present invention has been made from this point of view, and its object is to provide a gray scale display by realizing an interpolation gray scale between gray scales determined by a given gray scale signal. An object of the present invention is to provide a multi-gradation driving circuit of a display device in which the number of gradation signals can be significantly reduced.

[0027]

According to the present invention, there is provided a multi-grayscale drive circuit for transmitting and receiving a display, in which a plurality of picture elements each having a capacity are arranged in a matrix, and a gradation signal for each picture element is provided.
Drive circuits for generating and outputting
On the basis of at least one reference gradation signal,
Each gradation of image signal data composed of several bits
Generate a plurality of corresponding grayscale signals as periodic signals.
It is characterized by that .

In the present invention, one of the generated gradation signals
One is the same periodic signal as the reference gradation signal .

In the present invention, one of the generated gradation signals
One corresponds to the reference gradation signal and logic 1 or logic 0
This is a periodic signal obtained by combining each level signal .

In the present invention, the plurality of reference gray-scale signals
And one of the generated gradation signals is a pair of reference gradations.
This is a periodic signal obtained by combining signals .

In the present invention, a plurality of the reference gradation signals are provided.
And one of the generated gradation signals is a pair of reference gradations.
A periodic signal combining signals or one reference gray level
Signal and each signal of level corresponding to logic 1 or logic 0
The periodic signal is a combination of
Is generated based on the interpolation signal that is a periodic signal.
Is to be determined .

In the present invention, the interpolation signal is created.
Means for creating an interpolation signal and means for creating the interpolation signal.
A pair of reference gradation signals based on the interpolated interpolation signal.
Combined with a periodic signal or one reference tone signal
Each signal at the level corresponding to logical 1 or logical 0 is combined
A combination that selects which of the combined periodic signals to generate
Selection means and the cycle selected by the combination selection means
A signal and an interpolation signal created by the interpolation signal creation means.
And a waveform synthesizing means for generating a grayscale signal by synthesizing
Be prepared .

In the present invention, the interpolation signal is a reference signal.
Created based on the tone signal .

In the present invention, whether the interpolation signal is external
Based on the periodic signal input from the
Is done .

In the present invention, the period of the interpolation signal is based on
It is an integral multiple of the period of the quasi-tone signal .

In the present invention, the rise of the interpolation signal is
Rise or fall timing of the reference gradation signal.
Significant for rising or falling timing
Are synchronized with each other with a phase difference equal to or less than a small phase difference .

In the present invention, a plurality of the reference gradation signals are provided.
And the period of one reference gradation signal is different from the other reference gradation signal.
It is an integer multiple of 1 or more of the period of the gradation signal .

In the present invention, the rise of one reference gradation signal
When the rising or falling timing is
The rising or falling timing of the gradation signal
To synchronize with a phase difference less than the significant phase difference
Have .

In the present invention, a plurality of the reference gradation signals are provided.
And all the reference gradation signals have the same period.
You .

In the present invention, each of the reference gradation signals is
Each rising timing or falling tie
Phase difference is less than the significant phase difference
Synchronized with each other .

In the present invention, the rise of each of the reference gradation signals is set.
All rising timings or falling ties
All of the mining are in agreement .

In the present invention, the number of the reference gradation signals,
Or to the number of reference gradation signals and logic 1 or logic 0
Any number of the sum with the number of each signal of the corresponding level is
For the number n of bits constituting the image signal data, 2 ^n-1
+1 or less .

In the present invention, the image signal data is composed
Based on multiple high-order bits
A pair of reference gray-scale signals or a logical 1 or a logical 0
One base used in combination with each signal of the corresponding level
The quasi-tone signals are determined respectively, and the other lower bits are
Each reference gradation signal determined by the upper bits of the image signal data
Decide which signal to combine for the signal .

In the present invention, the rise of the interpolation signal is
Rise or fall timing of the reference gradation signal.
Rise or fall timing and significant phase
Synchronization with a phase difference less than or equal to the
At the timing, the signals to be combined are determined .

In the present invention, the lower bits
The number is two .

In the present invention, the reference gradation signal and the logic
Each signal of the level corresponding to 1 or logic 0 is the period ratio
3: 1 or 1: 3 combined, a pair of criteria
The gradation signals are combined at a period ratio of 2: 2 .

In the present invention, the number of the reference gradation signals is
5

[0048] In the present invention, the number of bits of the lower significant bit is 2.

In the present invention, when the number of the interpolation signals is plural,
One interpolation signal inverts the other one interpolation signal
Have been created .

In the present invention, at least one pair of reference floors
The tone signals are combined at a 1: 1 ratio to create a new
Generating a gradation signal for output, and a gradation signal for output;
By combining with other reference gradation signals,
And generate an output gradation signal .

In the present invention, a 4-bit image signal data
Each of the levels corresponding to logic 1 or logic 0
Signals and their respective period ratios are 1: 3 and
4 constituted by a pair of 3: 1 periodic signals
16 gray scale signals are generated based on one reference gray scale signal.
So that the intermediate gradation signal has a different period
Combining a pair of reference gray level signals at a ratio of 1: 1
Generated .

In the present invention, the intermediate gradation signal is
Select one of the other newly set reference gradation signals
It is being used in a typical way .

In the present invention, the maximum order of the image signal data
The grayscale signal generated corresponding to the grayscale or minimum grayscale
The difference is the same as one of the reference gradation signals .

In the present invention, the generated gradation signal is
Output driven by a power supply other than the display power supply
The data is output to the display unit via the buffer circuit .

In the present invention, the power supply voltage on the high level side of the power supply of the output buffer circuit is selected to be less than the minimum value of the power supply voltage on the high level side of the circuits other than the output buffer circuit, and the power supply voltage of the output buffer circuit is selected. Power supply voltage on the low level side
Is selected to be equal to or less than the minimum value of the power supply voltage on the low level side of the circuits other than the output buffer circuit.

In the present invention, the low-level power supply of the output buffer circuit is used in common with the low-level power supply voltage of circuits other than the output buffer circuit.

[0057]

The multi-grayscale driving circuit of the display device according to the present invention generates a first driving signal for driving a display section in which a plurality of picture elements each having a capacitance are arranged in a matrix at a plurality of grayscales. Output. In order to generate the first driving signal, at least one gradation signal corresponding to the plurality of gradations of an image displayed on the display unit and image signal data are input to the multi-gradation driving circuit. You. The multi-gradation driving circuit is configured to generate, based on the at least one gradation signal, the first driving signal having a gradation component that is a signal component corresponding to a gradation of the image signal data. A tone signal is created, and the first drive signal is created and output based on the input at least one tone signal and the other tone signals.

According to the present invention, the number of gray scale signals to be externally input to the multi gray scale drive circuit to generate the first drive signal for driving the display section with a plurality of gray scales is reduced. In the tone driving circuit, a new gradation signal is generated based on at least one input gradation signal according to the value of the image signal data, and an output waveform corresponding to each image signal data is determined. As a result, a plurality of interpolations can be displayed between gradations determined by each gradation signal.

[0059]

Embodiments of the present invention will be described below. Hereinafter, an active matrix type liquid crystal display device will be described as an example of a display device, but the present invention is also applicable to other types of display devices.

(Embodiment 1) FIG. 1 is a block diagram of a part of a signal wiring driving circuit 20 of a data driving circuit 200 according to a first embodiment of a multi-gradation driving circuit of the present invention, and FIG. FIG. 2 is a block diagram of an active matrix liquid crystal display device (hereinafter, a display device) 110 in which the signal line driving circuit 20 is used. 2, a display device 110 includes a display unit 107.
And a drive circuit 108 for driving the display section 107 for display. In the display unit 107 of the display device 110 shown in FIG.
Liquid crystal, which is a display medium, is sealed between the substrates 101, and a plurality of pixel electrodes 103 are arranged in a matrix on the liquid crystal side surface of one substrate 100. On the substrate 100, as a switching element for driving the plurality of pixel electrodes 103, a thin film transistor (TFT) is provided.
A plurality of parallel signal wirings (data wirings) 104 are connected to signal input portions of the TFTs 102, respectively.
In the control signal input section of the FT 102, a plurality of scanning wirings (gate wirings) 105 which are parallel to each other and extend in a direction crossing the signal wirings 104 are provided.

On the liquid crystal side surface of the other substrate 101, a common electrode (not shown) is formed over the front surface of the substrate 101, for example, or for each group connected in the row direction of the pixel electrodes 103. Between the common electrode 101 and the picture element electrode 103, a liquid crystal capacitance that contributes to display is formed using liquid crystal as a dielectric. The drive circuit 108 is connected to a control circuit 600 that outputs various control signals, a power supply circuit 400 that outputs power supply voltages VSH and VSL, and the signal wirings 104. Power supply voltage V from circuit 400
SH and VSL are supplied, and a source drive circuit 200 to which 4-bit image data is externally input, for example, and a gate drive circuit 300 to which each of the scanning lines 105 is connected
It is comprised including. The source drive circuit 200 includes drive voltages S0,..., S for performing display drive for each signal wiring 104.
i,..., Sn are supplied. Gate drive circuit 30
0 outputs a gate signal G0,..., Gi,..., Gm for turning on / off the TFT 102 for each row.

In the following description, a digital source driving circuit to which a video signal is given in a digital signal format will be described.

FIG. 1 is a block diagram showing a configuration of a signal wiring driving circuit 20 for outputting an image signal to a single signal wiring when the present invention is applied to a 4-bit driving circuit. In FIG. 1, 4-bit image data (D ₀ , D ₁ , D ₂ , D ₃ ) is
It has 16 values from _{0 to 15} , and the signal voltage applied to each pixel is one of 16 levels from V0 to V15.
The signal line driving circuit 20 is provided for each bit (D ₀ , D ₁ , D ₂ , D ₃ ) of the image signal data, and is a first-stage D-type flip-flop M used for a sampling operation.
_SMP , second stage D-type flip-flop _MH used for hold operation, and output waveform selection circuit SHSSK
And an output buffer circuit SB.

The signal line driving circuit 20 operates as follows. Data to be output from the flip-flop _MH is input to the output waveform selection and creation circuit SHSSK, and four interpolation signals H0, H1, H2, H
3, and five reference gradation signals T0, T4, T8, T12,
T16 is provided. Output waveform selection circuit SSHSK
Is output to the signal wiring 104 outside the signal wiring driving circuit 20 through the output buffer circuit SB.

FIG. 3 is a block diagram showing a configuration example of an internal circuit of the output waveform selection circuit SHSSK. As shown in FIG. 3, the output waveform selection and creation circuit SHSSK basically includes three functional parts. That is, a reference gradation signal selection circuit KKSK, an interpolation signal selection circuit HSSK, and a waveform synthesis circuit HGK for synthesizing their outputs. The reference gradation signal selection circuit KKSK includes upper two bits d3 and d2 of the 4-bit image data and reference gradation signals T0 and T4 each having a mutually different duty as described later.
T8, T12, and T16 (indicated by a symbol T in a generic name) are input. From the reference gradation signals T, a set of reference gradation signals T whose duty ratios are adjacent to each other is selected. The interpolation signal selection circuit HSSK includes lower two bits d1 and d0 of the image data and interpolation signals H0 and H having different duties as described later.
1, H2, and H3 (indicated by the symbol H in the generic case) are input, and the four interpolation signals H0, H1, and H
One interpolation signal H is selected from 2, H3.

The reference gradation signal T selected by the reference gradation signal selection circuit KKSK and the interpolation signal selection circuit HSSK
The interpolation signal H is input to the waveform synthesizing circuit HGK, and the output waveform of the signal line driving circuit 20 is determined. The output whose output waveform is determined is output via the output buffer circuit SB.
The signal is output to each signal wiring 104.

FIG. 4 is a timing chart of the reference gradation signals T0 to T16 and the interpolation signals H0 to H3. FIG.
As shown in (1) to (5) of FIG.
Average value AT (i) of each signal of reference gradation signals T0 to T16
(I = 0, 4, 8, 12, 16)

[0068]

## EQU5 ## AT (0)> AT (4)> AT (8)> AT
(12)> AT (16) so that each of the reference gradation signals Ti (i = 0, 4, 8,
12, 16) are selected. Further, as shown in FIG. 4, the reference grayscale signals T0 and T16 are high-level and low-level signals, respectively, and the average value of the reference grayscale signals T0 and T16 is equal to the reference grayscale signal Ti. Is selected as the maximum and minimum within. On the other hand, the remaining reference gradation signal T
4, T8 and T12 have clock waveforms as shown in FIG. In the present invention, the reference gradation signal Ti
What is important about is the average value, not the signal waveform itself.

Among the interpolation signals H0 to H3, the interpolation signal H0 is a high-level fixed-level signal, and the interpolation signals H1, H2, and H3 correspond to the corresponding reference gradation signals T4, T3.
8, T12 and the interpolation signals H1, H
2 and H3 each correspond to the corresponding reference gradation signal T4 or T4.
8 and a signal selected to be four times the cycle of T12. The duty ratios of the interpolation signals H1, H2, H3 are selected to be 3: 1, 2: 2, and 1: 3, respectively. Tables 1 and 2 below show output waveform selection circuits SHS.
The logic table of the signal selection function of the reference gradation signal selection circuit KKSK and the interpolation signal selection circuit HSSK which are the components of SK is shown.

[0070]

[Table 1]

[0071]

[Table 2]

Hereinafter, the operation of the output waveform selection circuit SHSSK of this embodiment shown in FIGS. 1 and 3 will be described, taking the case where the value of the image data is 5 as an example. At this time, the output waveform selection circuit SHSSK causes the reference gradation signals T4, T8
, A gradation signal corresponding to the reference gradation signal T5 is output from the output waveform selection circuit SHSSK. When the value of the image data is 5, bit data (D ₀ , D ₁ , D ₂ , D ₃ )
= (0,1,0,1), and from Table 1, bit data d3 = 0 and d2 = 1. Therefore, At a reference gray signal selection circuit KKSK, reference gray signal T4, T8 are selected as the reference gray signal T outputted, respectively as the output signal _{sT 0 = T4, sT 1 =} 8, the waveform Synthesis circuit H
GK input. Further, since the bit data d1 = 0 and d0 = 1 input to the interpolation signal selection circuit HSSK, the interpolation signal H1 is selected based on Table 2 above.
The output sH of the interpolation signal selection circuit HSSK = H1, and this output sH is an input of the waveform synthesis circuit HGK.

FIG. 5 is a timing chart for explaining the operation of the waveform synthesizing circuit HGK. Table 3 shows a logic table of the waveform synthesizing circuit HGK.

[0074]

[Table 3]

In the waveform synthesizing circuit HGK, the input signal sH
There is at the high level, the output SK next input signal sT ₀ the waveform synthesizing circuit HGK, when the input signal sH is low, the input signal sT _1, the output SK of the waveform synthesizing circuit HGK. Therefore, as the output SK of the waveform synthesizing circuit HGK, a waveform corresponding to the reference gradation signal T5 as shown in FIG. The waveform synthesizing circuit HGK can generate the reference gradation signal T5 based on the reference gradation signals T4 and T8. The reference gradation signal T5, which is the output SK of this waveform, is output from the signal line driving circuit 20 to each signal line 104 via the output buffer circuit SB.

On the other hand, the waveform of the output SK shown in FIG. 5 (4) is a waveform in which the reference gradation signals T4 and T8 are temporally combined 3: 1. The average value A (T5) is

[0077]

(Equation 6)

Is obtained. Here, the symbol A (T5) is 1
This represents the average value of one cycle of the reference gradation signal T5 when the cycle is 1. The same notation is used for the other reference gradation signals T. Further, the reference gradation signal T5 represents a waveform when the value of the image data is 5, and when the value of the image data is another value i, the output waveform selection circuit SHSSK generates the same signal as the reference gradation signal Ti. Can be created.

FIG. 6 shows the output O of the output buffer circuit SB when the waveform synthesizing circuit HGK creates the reference gradation signal T5 and inputs it to the output buffer circuit SB as the output SK.
It is a timing chart which shows (i). The output buffer circuit SB outputs the voltage V as its high-level power supply voltage.
SH is supplied with a voltage VSL as a low-level power supply voltage. Accordingly, the output O (i) oscillates between the power supply voltages VSH and VSL at the timing shown in FIG. 5 (4), thereby displaying an AC drive signal having an average voltage corresponding to the reference gradation signal T5. It can be supplied to the unit 107. The average voltage Av (T5) in this case
Is the potential relative to 0 volts,

[0080]

[Expression 7] Av (T5) = VSL + A (T5) (VSH-VSL)

FIG. 7 is a circuit diagram of a reference gradation signal selection circuit KKSK created from the logic table shown in Table 1 above, and FIG. 8 is an interpolation signal selection circuit created from Tables 2 and 3 above. It is a circuit diagram of HSSK and a waveform synthesis circuit HGK. The circuits of FIGS. 7 and 8 use the following logical expressions of Expressions 8, 9, 10, and 11 obtained from the logical tables of Tables 1 to 3 below.
It can be realized by converting to a logic circuit.

[0082]

ST ₀ = {0} T0 + {4} T4 + {8} T8
+ {12} T12

[0083]

ST ₁ = {0} T4 + {4} T8 + {8} T1
2+ {12} T16

[0084]

(Equation 10)

[0085]

[Equation 11]

The reference gradation signal selection circuit KKSK of FIG.
AND circuits 21, 22, 23 and 24 are provided. Bit data d3 is inputted to AND circuits 23 and 24, and inverted bit data of the bit data d3 by the inverting circuit 50 is inputted to AND circuits 21 and 22. You. Bit data d2
Is input to AND circuits 22 and 24 and bit data d
The inverted bit data from the two inverting circuits 51 is input to the AND circuits 21 and 23.

The outputs of the AND circuits 21, 22, 23, and 24 are output to AND circuits 25, 30, 26, 31, 27, and 3, respectively.
2: 28, 33 respectively. Reference gradation signal T
0 is input to the AND circuit 25 and the reference gradation signal T4
Is input to the AND circuits 26 and 30, and the reference gradation signal T
8 is inputted to AND circuits 27 and 31, the reference gradation signal T 12 is inputted to AND circuits 28 and 32, and the reference gradation signal T 16 is inputted to the AND circuit 33. Each output of the AND circuits 25, 26, 27, and 28 is output to an OR circuit 29.
Is input to The output of the OR circuit 29 becomes the output sT0. Each output of the AND circuits 30, 31, 32, and 33 is input to the OR circuit. The output of the OR circuit 34 becomes the output sT1.

The interpolation signal selecting circuit HSSK and the waveform synthesizing circuit HGK shown in FIG.
The bit data d1 is input to AND circuits 39 and 40, and the inverted bit data of the bit data d1 by the inverting circuit 35 is input to AND circuits 37 and 38.
The bit data d0 is input to AND circuits 38 and 40, and the inverted bit data of the bit data d0 by the inverting circuit 36 is input to AND circuits 37 and 39.

The outputs of the AND circuits 37 to 40 are respectively input to AND circuits 41, 42, 43 and 44, and the interpolation signals H0, H1, H2 and H3 are output to the respective AND circuits 41 and 42.
To 44 respectively. Each output of the AND circuits 41 to 44 is input to the OR circuit 45. OR circuit 4
5 is input to the AND circuit 47, and the inverted output of the output SH by the inverting circuit 46 is input to the logical product circuit 48. On the other hand, outputs sT0 and sT1 of the reference gradation signal selection circuit KKSK are input to AND circuits 47 and 48, respectively. Each output of the logic circuit 47, 48 is input to the OR circuit 49. The output of the OR circuit 49 becomes the output SK of the output waveform selection circuit SHSSK of FIG.

FIG. 9 shows the output waveform in the present embodiment by the reference gradation signal T. In FIG. 9, the symbols T0, T
4, T8, T12 and T16 correspond to FIGS. 4 (1) to 4 (5).
, The reference gradation signals T0, T4, T8, T12, T
One cycle of each of the 16 waveforms is shown. Hereinafter, the same applies. Table 4 below shows the relationship between the gradation voltage data obtained in this case and the data values. Here, V0, V
4, V8, V12, and V16 are voltages applied to the picture elements by the respective reference gradation signals.

[0091]

[Table 4]

The above is the operation of the first embodiment based on the first invention of the present application. The essence of Invention 1 of the present application is that by combining the reference grayscale signals T, a signal having an average value between the combined reference grayscale signals T is created in the drive circuit 108 and the original reference grayscale signal T is used. An object of the present invention is to create an interpolation gradation having a gradation between fixed gradations. The above embodiments are merely examples.

(Embodiment 2) For example, the combination of the reference gradation signals T0, T4, T8, T12, and T16 in the above-described embodiment 1 can be other combinations. It is. The period of the reference gray-scale signal generated by combining at least one reference gray-scale signal is sufficiently averaged by the low-pass circuit (LPF) composed of various capacitances of the display unit 107 as a load. The combination of the reference gradation signals T may be any combination as long as it is as short as possible and its average value is a target value.

For example, as an example, the display unit 107 may be driven for display at the timing shown in FIG. 9 using the signal wiring driving circuit 20 shown in FIGS. FIG.
, The signal Tn (n = 0, 4, 8, 12, 16) at
Two cycles of the reference gradation signal of the first embodiment may be used, or the order of the combination may be different from the order shown in the character 9. For example, if the value of the image data is 14
One cycle at the time of the signal T12, T16, T12, T16
Or the order of the signals T16, T12, T12, T16. In this case, one cycle is the signal T12,
It may be composed of T16.

(Embodiment 3) In order to create this combination of reference gradation signals, in the examples so far, the interpolation signal H is input from outside the signal line driving circuit 20 or the signal line driving circuit 20 is used. Or prepared in advance. Such a method is used to simplify the circuit configuration of the signal line driving circuit, and the essence of the first aspect of the present invention is not limited to such a method.

(Embodiment 4) In the above example, the interpolation signal H has been described as being synchronized with the reference gradation signal T. However, the present invention is limited to the synchronization relationship between such signals. It is not something to be done. The interpolation signal H and the reference gradation signal T are
They may be asynchronous with each other.

The reason is briefly described below.

FIG. 10 is a waveform chart for explaining the operation. If the period of the two reference gradation signals Ti and Tj is sufficiently short, and the interpolation signal H is used as in this embodiment, the reference gradation signals Tm and Tm corresponding to the period of the interpolation signal H are used. The cycle for switching Tn is equal to the reference gradation signal Ti,
If the period is sufficiently longer than the period of Tj and sufficiently shorter than the period of the cutoff frequency of the low-pass circuit of the display unit 107,
For at least one output period as a whole, as shown in FIG.
Average values A (Ti), A (T) of reference gradation signals Ti, Tj
The DC voltage of the value j) has the same value as that when the DC voltage is switched mutually at the period ratio m: n, and the average value is as follows:

[0099]

(Equation 12)

Is obtained.

However, when the reference gradation signal T and the interpolation signal H are combined in synchronism as in the first embodiment,
In general, the effect of preventing noise from being mixed into the display can be achieved. That is, the use of the interpolation signal synchronized with the reference gradation signal not only facilitates the analysis of the operation of the signal line driving circuit 20, but also has the effect of reducing noise and improving display quality.

(Embodiment 5) In the above example, between the five gradations corresponding to each of the five reference gradation signals Tn (n = 0, 4, 8, 12, 16). Into four equal parts,
Although a 4-bit drive circuit that creates three interpolation grayscales between a pair of adjacent grayscales has been described as an example, it goes without saying that the present invention is not limited to this specific example.

Hereinafter, another embodiment of the present invention will be described.

(Embodiment 6) FIG. 11 shows a timing chart of an operation example when only one gray scale signal is externally input to the signal wiring drive circuit 20 shown in FIGS.
The present embodiment is an example of a gradation signal for each image data value in the case of a 2-bit 4-gradation drive circuit, and only one gradation signal T2 is externally supplied.

When the value of the image data is 0, the power supply voltage V of the voltage level corresponding to the logic 1 in the signal line driving circuit 20
H is selected instead of the gray scale signal, and the output SK is the voltage V
H. When the value of the image data is 1, the reference gradation signal T
An output waveform is a signal T1 obtained by combining 2 with the power supply voltage VH corresponding to the logic 1 at a period ratio of 2: 1. When the value of the image data is 2, the waveform of the reference gradation signal T2 becomes the waveform of the output SK as it is, and when the value of the image data is 3, the power supply voltage VL of the voltage level corresponding to logic 0 is selected. And the output S of the signal line driving circuit 20
K becomes the voltage VL. Thus, in this embodiment,
Four gradation displays are possible.

In each of the above embodiments, for example, the interpolation signals H0, H1, H2, and H3 in FIG. 4 may be generated inside the signal line driving circuit 20.

Alternatively, for example, the interpolation signal H1 in FIG.
H2 and H3 may be created using, for example, the reference gradation signal T4. FIG. 12 shows the reference gradation signal T4.
5 shows a circuit example of a signal generation circuit 50 that generates interpolation signals H1, H2, and H3 from. 12 is provided in the output waveform selection circuit SHSSK shown in FIG. 1 as an example. The signal generation circuit 50 includes two D-type flip-flops 51 and 52, and the reference gradation signal T4 is commonly input to clock terminals CK of the flip-flops 51 and 52. The inverted output terminal Q bar of the flip-flop 51 is
The flip-flop 51 is connected to the data terminal D of the flip-flop 51 and is connected to the AND circuit 54 in an inverted manner. The non-inverting output terminal Q of the flip-flop 51 is connected to the flip-flop 5
2 and a logical product circuit 53
Connected to. Inverted output terminal Q of flip-flop 52
The bar is inverted and connected to the AND circuit 54,
The output is the interpolation signal H2. Flip-flop 52
Is connected to the AND circuit 53.
Outputs of the AND circuits 53 and 54 become interpolation signals H1 and H3.

Here, in the signal generation circuit 50 of FIG. 12, if the reference gradation signal T4 is replaced by another signal supplied from outside (hereinafter referred to as a reference interpolation signal), the reference gradation signal T4 is The period of the interpolation signal can be determined independently. It is also possible to supply all of the interpolation signals H1, H2, H3 from outside.

However, the source driving circuit 200 shown in FIG.
It is preferable that the number of signal lines to be input to the drive circuit is as small as possible. In this regard, the output waveform selection circuit SH shown in FIG.
The configuration incorporated in the SSK increases the ease of wiring design of the output waveform selection circuit SHSSK and increases the degree of freedom in wiring design.

On the other hand, when one type of source driving circuit 200 (see FIG. 1) is intended to support various driving of the display unit 107, the interpolation signal H depends on the characteristics of the display unit 107.
It may be better to change the cycle of In this case, as described above, as shown in FIG.
4 is replaced with another reference interpolation signal supplied from the outside, so as to determine the cycle of the interpolation signal H independently of the reference gradation signal T4. The display drive can be realized by a single source drive circuit 200, and the necessity of creating the source drive circuit 200 for each of the various display units 107 is eliminated.

(Embodiment 7) FIG. 13 shows a signal generation for generating interpolation signals H1, H2 and H3 by using both a reference interpolation signal H inputted from outside and a reference gradation signal T4 inputted from outside. FIG. 6 is a block diagram of a circuit 55. 13 is provided in the output waveform selection circuit SHSSK shown in FIG. 1 as an example. The signal generation circuit 55 includes two D-type flip-flops 56 and 57, and the interpolation signal H
Are commonly input to the clock terminals CK of the flip-flops 56 and 57. The inverted output terminal Q bar of the flip-flop 56 is connected to the data terminal D of the flip-flop 56 and is also inverted and connected to the AND circuit 59. The non-inverting output terminal Q of the flip-flop 56 is connected to the data terminal D of the flip-flop 57,
It is connected to an AND circuit 58.

The inverted output terminal Q bar of the flip-flop 57 is invertedly connected to the AND circuit 59 and connected to
Type flip-flop 61 is connected to the data terminal D. The non-inverting output terminal Q of the flip-flop 57 is connected to the AND circuit 58. The outputs of the AND circuits 58 and 59 are connected to the data terminals D of the D-type flip-flops 60 and 62, respectively.
Connected to each other. The clock terminal CK of the flip-flops 60 to 62 is supplied with the reference gradation signal T4. Outputs from the inverted output terminals Q of the flip-flops 60 to 62 become interpolation signals H1, H2, and H3.

By using such a signal generation circuit 55, even if there is a phase difference between the reference interpolation signal H and the reference gradation signal T4, the phase of the interpolation signal generated by the signal generation circuit 55 is changed to the reference level. It can be aligned with the phase of the tuning signal T4. This makes it possible to eliminate a phase difference between the reference interpolation signal H and the reference gradation signal T4, which would cause noise to appear in the display image.

FIG. 14 is a timing chart for explaining the operation of the signal generating circuit 55 of the present embodiment. FIG.
As shown in (1) and (2), based on a reference interpolation signal H and a reference gradation signal T4 which are input from the outside and have a phase difference with each other, interpolation signal signals H1 ', H2',
H3 'is created, and the interpolation signal signals H1', H2 ',
Based on H3 ', as shown in FIGS. 14 (6) to (8), reference interpolation signals H1, H2, H3 synchronized with the reference gradation signal T4 are created.

Thus, as described above, the display unit 10
7, the period of the interpolation signal H can be changed, and the display drive can be realized by the single source drive circuit 200 for the various display units 107. The effect of eliminating the need to create the source drive circuit 200 is achieved.

As described in the description of FIG. 10, the interpolation signal H
Need not absolutely be synchronized with the gradation signal T. Therefore, the cycle of the interpolation signal H does not need to be an integral multiple of the cycle of the gradation signal T. For example, if necessary, the interpolation signal H
May be switched at a cycle such as 2.5 times the cycle of the gradation signal T.

As described above, the configuration in which the interpolation signal H is switched at a cycle that is not an integral multiple of the cycle of the gradation signal T is compared with the configuration that switches the interpolation signal H at a cycle that is an integral multiple of the cycle of the gradation signal T. As described above, the problem that noise is mixed in the display image is solved. Therefore, in the specific example of the present invention, unless there is a special reason, the period of the interpolation signal is an integral multiple of the reference gradation signal, and the duty ratio of the interpolation signal is set such that the period of the reference gradation signal is 1. Use an integer ratio. This stipulates that, as an example, the cycle of the interpolation signal is set to five times the cycle of the gradation signal, and the duty ratio of the interpolation signal is not an integer ratio such as 2.5: 2.5. I do. In FIG. 14, the interpolation signal H
It is clear that 1, H2, and H3 all satisfy the conditions of the above items and items.

In FIG. 14, interpolation signals H1, H2, H
Regarding 3 and the reference gradation signal T4, the timing indicated by the broken line satisfies the above-mentioned item and the condition of the item.

FIG. 15 shows, as an example, the interpolation signals H1, H
2 is a timing chart for explaining the necessity of H3 and the reference gradation signal T4 to satisfy the above-mentioned item and the condition of the item. Each signal shown in FIG. 15 is obtained by extracting the reference gradation signal T4 and the interpolation signal H1 from each signal shown in FIG. 14, and further adding a gradation signal T8 as a reference gradation signal input from the outside. It is. In this example, the reference grayscale signals T4 and T8 are combined at a period ratio of 3: 1 to obtain a signal shown in FIG.
The gradation signal shown in (4) is created. In this manner, the reference gradation signals T4 and T8 are combined at timings corresponding to the high level / low level of the interpolation signal H1. Therefore, if there is a significant phase difference between the reference grayscale signals T4 and T8 and the interpolation signal H1 such that noise is mixed in the display image, the two when combining the reference grayscale signals T4 and T8 are used. At the switching timing, there is a possibility that the generated waveform shown in FIG. 15 (4) is distorted and the gradation is fluctuated.

(Embodiment 8) In the following description, FIG.
A description will be given by taking the 4-bit signal wiring drive circuit 20 as shown in FIG.

FIG. 16 shows reference gradation signals T4, T8, T1.
6 is a timing chart showing one example of a waveform 2. In the present embodiment, the reference gradation signal T4 has a cycle twice as long as the reference gradation signal T8 and three times as long as the reference gradation signal T12. In this case, if the cycle of the reference gradation signal T4 is used as a basic unit of the combination as described above, each reference gradation signal T4
It is clear that a combination of cycles of an integral multiple of the cycle of 4, T8 and T12 can be easily realized. Alternatively, the reference gradation signal T
8, a signal T8 'corresponding to two periods, and a reference gradation signal T12.
Are sequentially generated, the signals T0 ', T4', T8 ', T12', T16 '
In contrast, a combination similar to the combination of signals described with reference to FIG. 9 can be realized.

Referring to FIG. 16, reference gradation signals T4, T
The timing at which the periods of T8 and T12 are synchronized is shown in FIG.
The point indicated by the arrow attached to (3). In this example,
This is the start point of each cycle of the reference gradation signal T4. Since this timing can be a switching point when combining the reference gradation signals T4, T8, T12, at the timing indicated by the arrow, the reference gradation signals T4, T8, T12
If the phases of the twelve are significantly shifted from each other, as described above, it is apparent that a problem such as the incorporation of noise into the display image occurs. Accordingly, the above-mentioned terms and terms are such that, when the reference gradation signal is externally applied as shown in FIG. 16, the waveform obtained by combining these reference gradation signals is such that noise is mixed into the display image. This is a condition under which no significant fluctuation occurs.

The reference gray scale signals T4, T8, T12 input from the outside shown in FIG. 4 all have the same cycle. As described above, by using waveforms having the same cycle as the reference gradation signal, the configuration of a circuit for generating the reference gradation signal T or a circuit for processing a plurality of reference gradation signals can be simplified. Can be.

In each of the reference gradation signals T shown in FIG. 6, at least one of the rising and falling timings of each of the reference gradation signals T is synchronized with each other. From the viewpoint of combining these reference gradation signals T, it is not always necessary that both the rising and falling timings of each reference gradation signal T be synchronized with each other. On the other hand, in the source drive circuit system using the signal line drive circuit 20 using the timing signal of FIG. 6, for example, when adjusting the gradation, both the rise and fall timing of each reference gradation signal T Are synchronized with each other, it is possible to achieve the effects specific to the eighth embodiment as described above.

(Embodiment 9) FIG. 17 is a block diagram of one example of a 3-bit signal line drive circuit 20a corresponding to one output. The signal line drive circuit 20a of the present embodiment is similar to the signal line drive circuit 20 shown in FIG. 3, and corresponding portions are denoted by the same reference numerals. In this example, five reference gradation signals T0, T2, T4, T6, and T8 are provided from outside the drive circuit 20a, and the gradation signals T1, T3, T5, and T are internally provided.
7 are made as output waveforms for the corresponding data.

FIG. 18 shows reference gradation signals T0, T2, T
4 is a timing chart showing the relationship between T4, T6, T8 and gradation signals T1, T3, T5, T7. Table 5 below shows the relationship between the voltage and data obtained by each reference gradation signal, and Tables 6 and 7 are logical tables thereof. Note that the logic tables in Tables 6 and 7 correspond to the signal wiring drive circuit 20 shown in FIG.
The symbols used for are used.

The following Expressions 13 to 16 show logical expressions derived from the logical tables of Tables 6 and 7, and FIG. 19 shows a reference gradation signal selection circuit KKSK corresponding to FIG.
FIG. 20 shows a circuit example of the interpolation signal selection circuit HSSK and the waveform synthesis circuit HGK corresponding to FIG.

[0128]

[Table 5]

[0129]

[Table 6]

[0130]

[Table 7]

[0131]

(Equation 13)

[0132]

[Equation 14]

[0133]

(Equation 15)

[0134]

(Equation 16)

The reference gradation signal selection circuit KKS shown in FIG.
The configuration of K is similar to the configuration of the above-mentioned enforcement order shown in FIG. 7, and corresponding parts are denoted by the same reference numerals. The reference gradation signal selection circuit KKSK of the present embodiment is a logical product circuit 2
1, 22, 23, and 24. The bit data d2 is input to the AND circuits 23 and 24, and the inverted bit data of the bit data d2 by the inverting circuit 50 is output to the AND circuit 2.
1 and 22 are input. The bit data d1 is input to the AND circuits 22 and 24, and the inverted bit data of the bit data d1 by the inverting circuit 51 is output to the AND circuits 21 and 23.
Is input to

The outputs of the AND circuits 21, 22, 23, and 24 are output to the AND circuits 25, 30, 26, 31, 27, and 3, respectively.
2: 28, 33 respectively. Reference gradation signal T
0 is input to the AND circuit 25 and the reference gradation signal T2
Is input to the AND circuits 26 and 30, and the reference gradation signal T
4 is input to AND circuits 27 and 31, the reference gradation signal T 6 is input to AND circuits 28 and 32, and the reference gradation signal T 8 is input to the AND circuit 33. AND circuit 2
Outputs of 5, 26, 27, and 28 are input to an OR circuit 29. The output of the OR circuit 29 becomes the output sT0.
Each output of the AND circuits 30, 31, 32, and 33 is input to the OR circuit. The output of the OR circuit 34 is the output s
It becomes T1.

The interpolation signal selecting circuit HSSK shown in FIG. 20 includes an AND circuit 83. The bit data d0 is input to the AND circuit 83. The inverted bit data of the bit data d0 by the inverting circuit 81 is converted into an OR circuit 82. Is input to
The reference interpolation signal H is input to the AND circuit 83, and the output of the AND circuit 83 is input to the OR circuit 82. The output of the OR circuit 82 is the output S of the interpolation signal selection circuit HSSK.
H.

Inverting circuit 84 of output SH of OR circuit 82
Is output from the logical product circuit 8 of the waveform synthesis circuit HGK.
Input to 0. The output SH of the OR circuit 82 is
The signal is input to the logical product circuit 85 of the waveform synthesis circuit HGK. On the other hand, the output sT0 of the reference gradation signal selection circuit KKSK,
sT1 is input to AND circuits 85 and 80, respectively.
Each output of the AND circuits 80 and 85 is input to the OR circuit 87. The output of the OR circuit 87 becomes the output SK of the output waveform selection circuit SHSSK of FIG.

By the way, as in this embodiment, a case is considered in which an interpolation gray scale is created one by one between each reference gray scale and a display of 2 ⁿ gray scales is realized as a whole. The number of signals is 2 ^n-1 +1. In the present embodiment, as described above, if a new tone signal waveform is created by combining tone signals or logic 1 or logic 0, it is necessary to input the signal from outside. It is possible to reduce the number of reference grayscale signals. Thereby, simplification of circuit wiring, simplification of circuit configuration, and downsizing can be achieved.

The 4-bit drive circuit S shown in FIGS. 3 and 4
The HSSK and the 3-bit drive circuit 20a shown in FIGS. 17 and 18 determine the combination between a plurality of reference gradation signals T using the upper 2 bits of the image data, respectively, and the lower 2 bits or lower 1 of the image data. The interpolation signal H is determined by bits.

(Embodiment 10) Incidentally, the drive circuit 108 according to the present invention is not limited to such a configuration. FIG. 21 is a circuit diagram of the 3-bit driving circuit 20a shown in FIG.
FIG. 15 is a block diagram of a 3-bit drive circuit 20b according to a modified example of FIG. This embodiment is similar to the ninth embodiment, and corresponding parts are denoted by the same reference numerals.

In the drive circuit 20b of this embodiment, reference gradation signals T0, T2, T5, T7 corresponding to image data values 0, 2, 5, and 7 are externally provided, and an interpolation signal is provided. The output waveform selection and creation circuit SHS determines whether the two signals of the reference gradation signals H1 and H2 are created inside the drive circuit 20b or given externally.
SK has been entered.

FIG. 22 is a timing chart for explaining the operation of this embodiment. FIG. 22 shows the relationship between each gradation signal, the interpolation signal, and the output waveform. In the present embodiment, the gradation signal corresponding to the image data value 1 is created by combining the reference gradation signals T0 and T2 at a period ratio of 1: 2, and corresponds to the image data values 3 and 4. The gradation signal is created by combining the reference gradation signals T2 and T5 at a period ratio of 2: 1 and 1: 2, respectively, and the image signal value 6
Is created by combining the reference gradation signals T5 and T7 at a period ratio of 2: 1.

Table 8 below shows a logic table of the output waveform selection and creation circuit SHSSK of this embodiment, and Table 9 shows data values obtained by the drive circuit of this embodiment and gradation voltages obtained by the reference gradation signal T. The relationship is shown below.

[0145]

[Table 8]

[0146]

[Table 9]

Each of the circuit operations shown in FIGS. 9, 18, and 22 is such that the rising or falling of the input interpolation signal is the same as the rising or falling of the externally input reference gradation signal. Synchronization timing is provided, and at the synchronization timing, the interpolation signal is realized using an interpolation signal having no significant phase difference between the interpolation signal and the reference gradation signal.

Example 11 Hereinafter, Example 1 of the present invention will be described.
1 will be described. This embodiment is similar to the above embodiments, and in the following description, reference is made to the block diagram of FIG. 3 and the timing chart of FIG. The circuit operation of the 4-bit drive circuit shown in FIG. 4 is based on the combination of the gray scale signals for generating the gray scale signal
Alternatively, a combination with each signal of a level corresponding to logic 0 is determined by the lower two bits of the image signal data. In addition, the combination of the gradation signals or the combination between the gradation signal and each signal of the level corresponding to the logic 1 or the logic 0 is related to the period of each signal with the period ratio of 3: 1, 2:
2, and 1: 3. Here, the number of at least one input gray-scale signal is five, and a combination of the gray-scale signals or a signal between the gray-scale signal and each signal of a level corresponding to logic 1 or logic 0 is provided. The number of lower-order bits of image signal data that defines a combination of the gray-scale signals or each signal of a level corresponding to logic 1 or logic 0 used in the combination is two.

The operation of the circuit having the above configuration will be described based on the 4-bit drive circuit 20 shown in FIG. The interpolation signals H1 and H3 in the timing chart shown in FIG. 9 are signals having duty ratios of 2: 1 and 1: 2, respectively. Therefore, it is clear that an inverted signal of the interpolation signal H1 may be used instead of the interpolation signal H3. Further, by using this inverted signal, the interpolation signal H to be input to the output waveform selection and creation circuit SHSSK of FIG. 1 which is the same as the number of output terminals to each signal wiring 104 in the source drive circuit 200 shown in FIG. Can be reduced, the circuit wiring of the source drive circuit 200 can be simplified, and the configuration can be downsized. The drive circuit 1 including the source drive circuit 200
This is convenient in manufacturing an LSI (Large Scale Integrated Circuit) that realizes the 08.

(Embodiment 12) FIG. 23 shows a modification of the 4-bit drive circuit 20 shown in FIG.
It is a block diagram of c. This embodiment is similar to the configuration of the first embodiment shown in FIG. 1, and corresponding portions are denoted by the same reference numerals. In the drive circuit 20c of this embodiment, four reference grayscale signals T0, T4, T12, and T16 are externally supplied to the output waveform selection and creation circuit SHSSK.

FIG. 24 is a timing chart showing gradation signals when the value of image data is 4 to 12 in the drive circuit 20c of this embodiment. As described above, in the present driving circuit 20c, the gradation signal T8 is created by combining the reference gradation signals T4 and T12 at a period ratio of 1: 1. Further, the combination of the gradation signal T8 and the reference gradation signal T4 is performed. Thus, the gradation signals T5, T6, and T7 are created, and the combination of the reference gradation signals T8 and T12 produces the gradation signals T9, T9,
T10 and T11 have been created. Here, in the circuit operation shown in FIG. 24, the reference gradation signals T4 and T12 in the gradation signals T5 to T11 correspond to two periods of the reference gradation signals T4 and T8, respectively. As a result, finally, from the reference gradation signals T4 and T12 to the gradation signals T5 to T5.
11 have been created.

Such an embodiment is not limited to the 4-bit case of the present embodiment. Especially when the image data is 5
In a drive circuit having more than one bit, the circuit configuration concept shown in this embodiment can reduce the number of reference gradation signals to be input from the outside, thereby simplifying the circuit configuration and reducing the size. Has a great effect.

In the above-described embodiment, in the drive circuit in which the image data is 4 bits, the gray scale signal T8 is created by combining the reference gray scale signals T4 and T12 with a period ratio of 1: 1 inside the drive circuit. Whether to use the gray scale signal T8 or a signal input from the outside as the reference gray scale signal T8 may be selectable by a separately input selection signal. With such a circuit configuration, it is possible to realize a driving circuit in which an optimum method can be selected depending on conditions for using the driving circuit.

(Embodiment 13) Table 10 below shows the relationship between image data values and gradation voltages in a modification of the 4-bit drive circuit 20 shown in FIGS. 1 and 3. .

[0155]

[Table 10]

In Table 10, the gradation signal voltages V0, V
4, V8, V12, and V16 are gray scale voltages obtained by a single reference gray scale signal. In the present embodiment, the output corresponding to the value 15 of the image data is not the gradation signal obtained by the combination of the reference gradation signals T12 and T16 input from the outside, but the reference gradation signal T16 input from the outside. The output waveform is determined as it is as the gradation voltage. By doing so, the gradation signals T14, T15
The voltage difference between them increases, and the display 107 shown in FIG.
It is easy to give a contrast difference to the display in the above. This is based on the finding that the relationship between the applied voltage and the transmittance of the liquid crystal is such that the nonlinearity is large near the maximum transmittance or the minimum transmittance, and the change in transmittance becomes small with the change in applied voltage. Based. Therefore, when a display unit such as a liquid crystal display element having such characteristics of the applied voltage and the transmittance is used, the drive circuit having the circuit configuration and the circuit operation of this embodiment can improve the display quality. The effect described above can be achieved.

(Embodiment 13) Driving circuit 2 shown in FIG.
At 0, the output buffer circuit SB is driven by a power source different from a driving power source such as the output waveform selection / creating circuit SHSSK, for example. FIG. 6 shows that the power supply voltage VHS is supplied as the power supply on the high level side of the output buffer circuit SB, and the power supply voltage VSL is supplied as the power supply on the low level side. With this feature, the present embodiment has the following effects.

The driving circuit 20 whose display characteristics are not affected by the voltage fluctuation of the other driving power supply can be realized. In general, as a use condition of the drive power supply of the display device 110 including the drive circuit 20, a width of, for example, 5 V ± 10% is usually given. Therefore, if this drive power supply is used as it is as the power supply of the output buffer circuit SB of the drive circuit 20, the voltage level of the output of the output buffer circuit SB fluctuates due to the fluctuation of the power supply voltage of the drive power supply, The gradation at the time of display may change. This degrades the display quality of the display device. Therefore,
In the first embodiment, by supplying a stable power source different from other circuit portions as a power source of the output buffer circuit SB, even if the drive power source of the display device 110 fluctuates within the range of the above specification, It is possible to realize a drive circuit in which the gradation at the time of display does not change.

(Embodiment 14) When the stable power supply voltage to the output buffer circuit SB may be lower than the drive power supply Vdd of the display device 110, the output buffer circuit SB
For example, a power supply circuit common to the drive circuit 108 shown in FIG. 2 can be easily obtained by using a three-terminal regulator, a combination of a constant voltage diode and a transistor, or the like.

(Embodiment 15) The output buffer circuit SB
If the power supply voltage on the low-level side fluctuates, the gradation at the time of display also changes, and the display quality deteriorates. However, the power supply voltage on the low level side is naturally lower than the power supply voltage on the high level side.
D.

Furthermore, when a low-level power supply voltage of the drive circuit 20 such as the ground potential GND is used as the low-side power supply voltage VSL, a low-level power supply voltage for the output buffer circuit SB is separately prepared. No longer needed
The configuration can be simplified and the size can be reduced.

(Embodiment 16) FIG. 25 is a block diagram of a signal wiring drive circuit 20d according to Embodiment 16 of the present invention, and FIG. 26 is a timing chart for explaining the circuit operation of the drive circuit 20d of this embodiment. . This embodiment is shown in FIG.
3 is similar to the configuration of the first embodiment shown in FIG. 3, and corresponding portions are denoted by the same reference numerals.

FIG. 25 shows a configuration for outputting an image signal to a single signal line when the present invention is applied to a 4-bit drive circuit. In FIG. 1, the signal line driving circuit 20d
Represents each bit (D ₀ , D ₁ , D ₂ , D ₃ ) of the image signal data
A first-stage D-type flip-flop M _SMP provided for each sampling operation and used for a hold operation, a second-stage D-type flip-flop M _H used for a hold operation, and the same number of bits as image data AND circuits 71, 72, 7
3, 74, and an output buffer circuit SB. The output of each bit of the flip-flop _MH is output to each AND circuit 7.
1 to 74 respectively. AND circuits 71 to 7
Each output of 4 is input to a 4-input OR circuit 75, and the output of the OR circuit 75 is input to an output buffer circuit SB. On the other hand, the reference interpolation signals TM0, TM1, TM2, and TM3 are input to the AND circuits 71 to 74, respectively.

The signal line driving circuit 20 operates as follows. Reference interpolation signals TM0, TM1, TM2, TM
As shown in FIG. 26, No. 3 is set such that the duty ratio increases in this order and the high-level periods do not overlap each other. The data to be output is output from the hold operation flip-flop _MH , and the four reference interpolation signals TM0, TM1, TM2, TM3 are output.
Is given. 4-bit image data D ₃ , D ₂ , D
_In response to the cases where ₁ and D ₀ are (0000) to (1111) in the binary system, the output waveforms shown in FIGS. 26 (5) to (20) are output from the output buffer circuit SB. Created. This output waveform is output to each signal wiring 104.

According to such an embodiment, the same effects as those described in the above embodiments can be achieved.
Further, in this embodiment, only the interpolation signal is used instead of the reference gradation signal in each of the above embodiments, so that the circuit wiring of the drive circuit 20d of this embodiment is simplified, and the circuit configuration is reduced. Can be achieved.

[0166]

As described above, there are many effects of the present invention, but the greatest effect is that a plurality of gradation power supplies, which have been indispensable in the past, are expelled from the driving circuit system of the display device, and only a complete digital circuit is required. It is possible to realize a drive circuit system. Further, in addition to the above, the present invention can reduce the number of gray scale signals which are digital signals required for gray scale generation, and can greatly reduce the number of signal inputs to the drive circuit system. Furthermore, in the case of a 6-bit drive circuit, for example, a large number of gray scale signal input terminals are required, so that a multi gray scale drive circuit has been substantially difficult to realize. This is because, for example, in the case of a 6-bit drive circuit, normally 64 gradation signals are required, and the circuit configuration becomes complicated. On the other hand, the driving circuit of the present invention can realize a multi-gradation driving circuit. Another major effect of the present invention is that the drive circuit for driving the display section can be entirely constituted by digital circuits, thereby greatly improving the reliability of the display device as a module. Becomes Also, the cost reduction effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram of a signal line driving circuit 20 according to a first embodiment of the present invention.

FIG. 2 is a system diagram of a display device 110 according to the first embodiment.

FIG. 3 is a block diagram corresponding to one output of the 4-bit drive circuit according to the first embodiment.

FIG. 4 is a timing chart illustrating the operation of the first embodiment.

FIG. 5 is a timing chart for explaining the operation of the waveform matching circuit according to the first embodiment.

FIG. 6 is a timing chart of an output waveform example of the first embodiment.

FIG. 7 is a circuit diagram illustrating a configuration example of a reference gradation signal selection circuit according to the first embodiment.

FIG. 8 is a circuit diagram illustrating a configuration example of an interpolation signal selection circuit and a waveform synthesis circuit according to the first embodiment.

FIG. 9 is a diagram showing a relationship between combinations of gradation signals with respect to values of respective data.

FIG. 10 is a timing chart for explaining an operation based on a combination of reference gradation signals.

FIG. 11 is a timing chart showing a waveform example with respect to each data value when only one reference gray scale signal is input from the outside.

FIG. 12 is a circuit diagram when an interpolation signal is created from a reference gradation signal T4.

FIG. 13 is a circuit diagram when an interpolation signal is created using both a reference gradation signal input from outside and a reference interpolation signal H;

FIG. 14 is a timing chart illustrating the operation of the circuit in FIG. 13;

FIG. 15 is a timing chart illustrating an operation of creating an interpolation signal from reference gradation signals T4 and T8 and an interpolation signal H1.

FIG. 16 is a timing chart for explaining another embodiment.

FIG. 17 is a block diagram of a 3-bit drive circuit according to another embodiment of the present invention.

FIG. 18 is a timing chart showing a relationship of a gradation signal created by combining with a value of each data in the circuit of FIG. 17;

FIG. 19 is a circuit diagram of a reference gradation signal selection circuit according to another embodiment of the present invention.

FIG. 20 is a circuit diagram of an interpolation signal selection circuit and a waveform synthesis circuit of the present embodiment.

FIG. 21 is a block diagram of another embodiment of a 3-bit drive circuit.

FIG. 22 is a timing chart showing a relationship between a combination of a data value and a reference gradation signal according to the present embodiment.

FIG. 23 shows a 4-bit drive circuit according to another embodiment of the present invention.
It is a block diagram equivalent to an output.

FIG. 24 is a timing chart showing a relationship between a combination of a data value and a reference gradation signal in the present embodiment.

FIG. 25 is a block diagram of a 4-bit drive circuit according to another embodiment of the present invention.

FIG. 26 is a timing chart of the present embodiment.

FIG. 27 is a block diagram of a drive circuit corresponding to one output according to the related art.

FIG. 28 is a timing chart illustrating the operation of the conventional technique.

FIG. 29 is a block diagram of another conventional driving circuit.

FIG. 30 is a block diagram of still another conventional driving circuit.

FIG. 31 is a timing chart illustrating the operation of the related art.

[Explanation of symbols]

20, 20a, 20b, 20c, 20d Signal wiring drive circuit 107 Display section 108 Drive circuit 110 Display device 200 Source drive circuit D ₀ , D ₁ , D ₂ , D ₃ Image data bits KKSK Reference gradation signal selection circuit HGK Waveform Synthesis circuit HSSK interpolation signal selection circuit M _SMP , _MH flip-flop SHSSK output waveform selection circuit SB output buffer circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/133 575 G02F 1/133 550

Claims (30)

(57) [Claims] 1. A drive circuit in which a plurality of picture elements each having a capacity are arranged in a matrix, and each of the drive circuits generates and outputs a gradation signal for each picture element. A multi-gradation driving circuit for a display device, wherein a plurality of gradation signals respectively corresponding to each gradation of image signal data composed of a plurality of bits are generated as a periodic signal based on a reference gradation signal. . 2. The multi-grayscale driving circuit for a display device according to claim 1, wherein one of the generated grayscale signals is the same periodic signal as the reference grayscale signal. 3. The display device according to claim 1, wherein one of the generated gray scale signals is a periodic signal obtained by combining a reference gray scale signal and each signal of a level corresponding to a logic 1 or a logic 0. Multi-tone drive circuit. 4. The display according to claim 1, wherein there are a plurality of said reference gradation signals, and one of the generated gradation signals is a periodic signal obtained by combining a pair of reference gradation signals. Multi-gradation drive circuit of the device. 5. A method according to claim 1, wherein a plurality of the reference gray scale signals are provided, and one of the generated gray scale signals is a periodic signal obtained by combining a pair of reference gray scale signals, or one reference gray scale signal and a logic 1 or a logic 2. A periodic signal obtained by combining each signal of a level corresponding to 0, and which periodic signal is generated is determined based on an interpolation signal which is a periodic signal. Multi-gradation drive circuit of the display device. 6. An interpolation signal creating means for creating the interpolation signal, and a periodic signal obtained by combining a pair of reference gradation signals based on the interpolation signal created by the interpolation signal creating means.
Alternatively, combination selecting means for selecting which one of a periodic signal obtained by combining one reference gradation signal and each signal of a level corresponding to logic 1 or logic 0, and selecting the combination signal by the combination selecting means 6. A waveform synthesizing unit for synthesizing a periodic signal and an interpolation signal created by the interpolation signal creation unit to generate a grayscale signal.
5. A multi-gradation drive circuit for a display device according to claim 1. 7. The multi-gradation driving circuit according to claim 5, wherein the interpolation signal is created based on a reference gradation signal. 8. The multi-gradation driving circuit according to claim 5, wherein the interpolation signal is created based on a periodic signal input from the outside and a reference gradation signal. 9. The multi-gradation driving circuit for a display device according to claim 7, wherein a cycle of said interpolation signal is an integral multiple of a cycle of a reference gradation signal. 10. A rising or falling timing of the interpolation signal is synchronized with a rising or falling timing of the reference gradation signal while having a phase difference smaller than a significant phase difference. 10. The multi-gradation driving circuit of the display device according to 9. 11. The method according to claim 1, wherein there are a plurality of the reference gradation signals, and a period of one reference gradation signal is an integer multiple of one or more of a period of another reference gradation signal. Multi-gradation drive circuit of the display device. 12. A state in which the rise or fall timing of one reference gradation signal has a phase difference that is less than or equal to a significant phase difference with respect to the rise or fall timing of another one gradation signal. The multi-grayscale drive circuit of the display device according to claim 11, which is synchronized by: 13. The multi-grayscale drive circuit according to claim 1, wherein the reference grayscale signal is plural, and all the reference grayscale signals have the same period. 14. The display device according to claim 13, wherein each of the reference gray-scale signals has a rising timing or a falling timing synchronized with each other with a phase difference smaller than a significant phase difference. Multi-tone drive circuit. 15. The multi-gradation driving circuit of the display device according to claim 14, wherein all of the rising timings or all of the falling timings of each of the reference gradation signals match. 16. The number of the reference gray-scale signals or the sum of the number of reference gray-scale signals and the number of signals of levels corresponding to logic 1 or logic 0 is equal to the number of image signal data. 2. The multi-gradation drive circuit for a display device according to claim ¹ , wherein the number n is set to 2 ^n-1 +1 or less with respect to the number n of bits constituting. 17. A combination of a pair of reference gray-scale signals based on a plurality of high-order bits constituting the image signal data or 1 used for each signal of a level corresponding to a logical 1 or a logical 0 2. The method according to claim 1, wherein one reference gray level signal is determined, and the other lower bits determine which signal is combined with each reference gray level signal determined by upper bits of the image signal data. Multi-gradation driver circuit for display device. 18. The rising or falling timing of the interpolation signal is synchronized with the rising or falling timing of the reference gradation signal in a state having a phase difference of a significant phase difference or less, and is synchronized with the synchronization timing. The multi-grayscale drive circuit of the display device according to claim 17, wherein a signal to be combined is determined. 19. The multi-gradation drive circuit according to claim 17, wherein the number of lower-order bits is two. 20. The reference gradation signal and each signal of a level corresponding to logic 1 or logic 0 are combined at a period ratio of 3: 1 or 1: 3, and a pair of reference gradation signals 20. The multi-gradation drive circuit of the display device according to claim 19, wherein the two-to-two combination is performed. 21. The multi-grayscale drive circuit for a display device according to claim 16, wherein the number of the reference grayscale signals is five. 22. The multi-gradation driving circuit of a display device according to claim 16 the number of bits of the lower significant bit is 2. 23. The multi-gradation driving circuit according to claim 5, wherein the plurality of interpolation signals are plural, and one interpolation signal is created by inverting another interpolation signal. 24. A new output gray scale signal is generated by combining at least a pair of reference gray scale signals at a period ratio of 1: 1, and the output gray scale signal and another reference gray scale signal are combined. 17. The multi-grayscale drive circuit for a display device according to claim 16, wherein a new grayscale signal for output is generated by combining the grayscale signal with a grayscale signal. 25. In 4-bit image signal data,
On the basis of four reference gray-scale signals composed of each signal of a level corresponding to logic 1 or logic 0 and a pair of periodic signals having respective cycle ratios of 1: 3 and 3: 1, respectively. , 16 gray scale signals are generated, and the intermediate gray scale signal is generated by combining a pair of reference gray scale signals having different period ratios at a period ratio of 1: 1. 20. The multi-gradation driving circuit of the display device according to 19. 26. The display device according to claim 24 , wherein one of the intermediate grayscale signal and another newly set reference grayscale signal is selectively used. Grayscale driving circuit. 27. The multi-display apparatus according to claim 17, wherein a gradation signal generated corresponding to the maximum gradation or the minimum gradation of the image signal data is the same as any one of the reference gradation signals. Grayscale driving circuit. 28. The multi-level display device according to claim 1, wherein the generated gray scale signal is output to the display unit via an output buffer circuit driven by a power source different from a drive power source for the display unit. Tuning drive circuit. 29. A power supply voltage on a high level side of a power supply of the output buffer circuit is selected to be equal to or less than a minimum value of a power supply voltage on a high level side of circuits other than the output buffer circuit, and a low power supply voltage of the output buffer circuit is selected. 29. The multi-grayscale drive circuit for a display device according to claim 28, wherein the power supply voltage on the level side is selected to be equal to or less than the minimum value of the power supply voltage on the low level side of circuits other than the output buffer circuit. 30. The multi-grayscale drive circuit according to claim 29, wherein a low-level power supply of the output buffer circuit is used in common with a low-level power supply voltage of a circuit other than the output buffer circuit. .