JP3011518B2 - Elevator control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an elevator control device which is digitally controlled using a computer or the like.

[0002]

2. Description of the Related Art Conventionally, in an elevator control device, as shown in FIG. 3, a speed command generator 1 outputs a speed command signal 1a of a car 2 and supplies the same to a speed control amplifier 3. Reference numeral 3 denotes a speed signal 6a obtained by converting a position signal 5a from a position detector 5 coupled to an electric motor 4 for driving the car 2 into a speed by a position / speed converter 6, and a speed command signal from the speed command generator 1. 1a, and outputs a current command 3a corresponding to the difference to supply it to the current control amplifier 7.

[0003] The current control amplifier 7 is provided with the current command 3
a, and calculates a deviation between the current signal 8a of the current detector 8 for detecting the current of the motor 4 and outputs the power control signal 7a by adding the load signal 9a from the unbalanced torque command device 9 to the deviation. Then, this signal is supplied to the power converter 10. The power converter 10 controls the power supplied to the electric motor 4 based on the power control signal 7a.

As a result, the electric motor 4 rotates the sheave 13,
As a result, the car 2 attached to the counterweight 11 at both ends of the main rope 12 wound around the sheave 13 is moved.

The car 2 has a landing device 14. The landing device 14 detects landing detection plates 15A, 15,... Provided on each floor of the elevator hoistway, and supplies a landing signal 14a to the speed command generator 1. The speed command generator 1 outputs a speed command signal 1a based on the landing signal. Further, the car 2 has a load detector 16, which supplies a load detection signal 16 a to the unbalanced torque command device 9.
The unbalanced torque command device 9 generates a signal for correcting an unbalanced torque with the counterweight 11 and supplies the signal to the current control amplifier 7.

[0006] The above elevator control device comprises a speed command generator 1, a speed control amplifier 3, a position / speed converter 6,
Although the current control amplifier 7 and the like are configured by individual circuits, digital control by the microcomputer has been widely adopted for controlling the elevator with the recent development of the microcomputer. In the following, DSPs are being adopted.

That is, the arithmetic processing of the speed control system is performed by a microcomputer, and the arithmetic processing of the current control system that requires high-speed arithmetic is performed by a DSP or the like.

[0008]

Even in a digitally controlled elevator control device using a microcomputer or a DSP, a control amount that changes every moment depending on the operation state of the elevator is digitally adjusted during elevator adjustment or maintenance. Rather, there is a demand to output in analog form and check the state. Therefore, in an elevator that is digitally controlled, each control amount is stored in a RAM or the like as a digital amount. To output this as an analog amount, a D / A converter is generally provided on a data bus of a microcomputer. And place the value of RAM in this D / A
A method of outputting through a converter is adopted. In this case, there is no problem in outputting the control amount calculated in the microcomputer. However, for example, a control amount calculated at a high speed by a DSP or the like at a much faster sampling time than the sampling time of the microcomputer is accurately output. There is a major problem with trying to do so. That is, in the above method, since the value calculated by the DSP during the sampling time of the microcomputer changes every moment, the movement of the control amount calculated by the DSP during this time cannot be accurately output in an analog manner. .

[0009] The present invention has been made in view of the above,
Its purpose is to provide a digital control type elevator control device in which a processor (for example, a DSP) that performs higher-speed operations than the higher microcomputer is arranged below the higher microcomputer, especially during the sampling time of the higher microcomputer. An object of the present invention is to provide an elevator control device capable of accurately outputting a control amount calculated by a lower processor as an analog amount.

[0010]

According to the present invention, a control amount of a motor for driving an elevator is calculated by using a high-order microcomputer and a low-speed high-speed processor, and the drive control means of the motor is controlled in accordance with the calculation result. In a control device of an elevator to be controlled, a write data buffer means for enabling transfer of data from the microcomputer to the high-speed arithmetic processor, and read data for enabling transfer of data from the high-speed arithmetic processor to the microcomputer. Buffer means, data storage buffer means capable of storing an arbitrary control amount calculated by the high-speed arithmetic processor for each sampling of the high-speed arithmetic processor, and arranged on a data bus of the microcomputer; Read data buffer means; Serial data storage device that can store the data in the data storage in the buffer means, characterized by having a D / A converting means for enabling outputting the stored data to the outside as analog quantity.

[0011]

According to the present invention, in addition to a write data buffer and a read data buffer which enable the transmission and reception of data between a normal upper microcomputer and a lower high speed processor, an arbitrary control amount operated by the lower high speed processor is provided. A data storage buffer capable of storing the data at each sampling time of the lower high-speed arithmetic processor is provided, and the control data calculated by the lower high-speed arithmetic processor is temporarily stored in this data storage buffer for each sampling. The data in the buffer is stored in the upper data storage means at each sampling time of the upper microcomputer, and the data is stored in the D / A
This is output to the outside as an analog quantity via a converter. As a result, the control amount calculated by the lower high-speed arithmetic processor during the sampling time of the upper microcomputer can be accurately output as an analog amount.

[0012]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 3 shows an embodiment of a circuit in which the speed command generator 1, speed control amplifier 3, position / speed converter 6, and current control amplifier 7 of the elevator control device of FIG. Is shown.

In FIG. 1, reference numeral 20 denotes speed command calculation, position /
An upper microcomputer 21 performs a speed conversion operation and a speed control operation and outputs a current command, and 21 is a lower high-speed operation processor that performs a current control operation and outputs a power conversion signal (not shown in FIG. 1). Reference numeral 22 denotes a write data buffer for transferring a current command, a control parameter, and the like calculated by the microcomputer 20 to the lower high-speed processor 21;
Is a read data buffer for the upper microcomputer 20 to read the control data calculated by. Also 24
Is a data storage buffer for storing data for each sampling (sampling of the high-speed operation processor) of arbitrary control data calculated by the high-speed operation processor 21 specified by the microcomputer 20, and transferring the data to the upper microcomputer. . Reference numeral 25 denotes a RAM connected to the data bus 27 of the upper microcomputer 20, which stores and stores control data and the like calculated by the microcomputer 20 and the high-speed processor 21. Reference numeral 26 denotes a D / A converter connected to the data bus 27 for outputting the control data stored in the RAM 25 as an analog amount to the outside. Reference numeral 28 denotes a data bus of the high-speed operation processor 21. Next, the operation of the control device having the above configuration will be described.

The microcomputer 20 performs a speed command calculation, a position / speed conversion calculation, and a speed control calculation of the elevator at a fixed sampling interval to calculate a current command value. The microcomputer 20 converts the current command data and data such as control parameters necessary for the current control operation performed by the lower high-speed operation processor 21 into each sampling time (sampling time of the microcomputer 20).
Is transferred to the write data buffer 22 every time . The lower high-speed arithmetic processor 21 synchronizes these data with the sampling time of the high-speed arithmetic processor 21, reads the data from the write data buffer 22, and performs high-speed current control arithmetic and the like. The high-speed operation processor 21 transfers main data among the control data stored in the high-speed operation processor 21 to the read data buffer 23 in synchronization with the sampling time of the high-speed operation processor 21 based on the operation result. Further, the high-speed arithmetic processor 21 samples arbitrary control data specified by the upper microcomputer 20 (actually specified via the write data buffer 22) among the control data to be arithmetically processed (sampling of the high-speed arithmetic processor). ) Is transferred to the data storage buffer 24 every time. Here, the difference between the read data buffer 23 and the data storage buffer 24 is that one buffer is assigned to one control data in the read data buffer 23, and in the data storage buffer 24, the lowest microcomputer is assigned to one control data. And a buffer corresponding to the ratio of the sampling time of the low-speed high-speed arithmetic processor. That is, assuming that the sampling time of the microcomputer is 1 [msec] and the sampling time of the high-speed operation processor is 200 [msec], at least five (1000/200 =
5).

The microcomputer 20 transfers the data stored in the buffers 23 and 24 to the RAM 25 at every sampling time (microcomputer sampling time). Further, the microcomputer outputs the value stored in the RAM to the outside via the D / A converter 26 as an analog amount. In this case, the data stored in the RAM 25 via the buffer 24 is the data for each sampling time of the high-speed arithmetic processor, but the data is stored in the sampling time of the microcomputer 20 in the same manner as the data stored in the RAM 25 via the buffer 23. If the data is output to the D / A converter every time, the waveform becomes as if the time axis is enlarged as shown in FIG.

As described above, the transfer of data between the upper microcomputer 20 and the lower high-speed arithmetic processor 21 is not performed by directly connecting the microcomputer 20 and the high-speed arithmetic processor 21 because of the high speed of the high-speed arithmetic processor. This is because the microcomputer cannot follow the characteristics and the load on the microcomputer for the interface increases.

Therefore, in the present invention, in order to solve this problem, a buffer in which an address is assigned to each data is provided so that the upper microcomputer can access any data at any timing.

In FIG. 1, buffers 22 to 24 (shown by dotted lines in FIG. 1) can be relatively easily and inexpensively realized as one semiconductor chip by using recent integrated circuit technology.

[0019]

According to the present invention, even in a control device in which a high-speed operation processor that performs higher-speed operation than the higher-order microcomputer is arranged below the upper-order microcomputer, the lower-order high-speed operation can be performed during the sampling time of the upper-order microcomputer. Since the control amount calculated by the processor can be accurately output as an analog amount, it is very effective for the adjustment of the elevator, maintenance, and analysis of the cause when a failure occurs, such as a failure.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an elevator control device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of control data in the embodiment of FIG.

FIG. 3 is a block diagram showing a configuration of a conventional elevator control device.

[Explanation of symbols]

 20 ... Microcomputer 21 ... High-speed arithmetic processor 22 ... Write data buffer 23 ... Read data buffer 24 ... Data storage buffer 25 ... RAM 26 ... D / A converter 27 ... Data bus 28 ... Data bus

Claims (1)

(57) [Claims] An elevator control apparatus for calculating a control amount of an electric motor for driving an elevator by using a microcomputer and a high-speed arithmetic processor below the microcomputer and controlling the electric motor in accordance with a calculation result. Write data buffer means for enabling transfer of data to the high-speed arithmetic processor; read data buffer means for enabling data transfer from the high-speed arithmetic processor to the microcomputer;
A data storage buffer capable of storing an arbitrary control amount calculated by the high-speed arithmetic processor for each sampling of the high-speed arithmetic processor; and a read data buffer arranged on a data bus of the microcomputer. A data storage unit capable of storing each data in the data storage buffer unit; and a D / A conversion unit capable of outputting the stored data to the outside as an analog amount. Elevator control device.