JP3012045B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3012045B2 JP3012045B2 JP3239529A JP23952991A JP3012045B2 JP 3012045 B2 JP3012045 B2 JP 3012045B2 JP 3239529 A JP3239529 A JP 3239529A JP 23952991 A JP23952991 A JP 23952991A JP 3012045 B2 JP3012045 B2 JP 3012045B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- semiconductor
- support substrate
- molten solder
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/011—Apparatus therefor
- H10W72/0113—Apparatus for manufacturing die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
- H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/331—Shapes of die-attach connectors
- H10W72/334—Cross-sectional shape, i.e. in side view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】この発明は、高出力半導体素子の
製造方法に係わり、半田を用いて半導体チップを半導体
支持基板に接着する半導体チップの接着方法に係る半導
体装置の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a high-power semiconductor device, and more particularly to a semiconductor device bonding method for bonding a semiconductor chip to a semiconductor support substrate using solder . It relates to a manufacturing method.
【０００２】[0002]
【従来の技術】高出力半導体素子はチップ接着材料とし
て半田が多用されている。以下従来のダイスボンド方法
について説明する。図４は従来の半導体チップの接着方
法を示す側面図である。図４(a) に示す半導体支持基板
７上に、半田箔５を載置する（図４(b) ）。このとき半
田箔５を載置するかわりに溶融半田を滴下してもよい。
その後、図４(c) に示すように半導体チップ６を圧着又
は、加圧摺動することによりチップ接着を行っている。2. Description of the Related Art High-power semiconductor devices often use solder as a chip bonding material. Hereinafter, a conventional die bonding method will be described. FIG. 4 is a side view showing a conventional semiconductor chip bonding method. The solder foil 5 is placed on the semiconductor support substrate 7 shown in FIG. 4A (FIG. 4B). At this time, molten solder may be dropped instead of placing the solder foil 5.
Thereafter, as shown in FIG. 4C, the semiconductor chip 6 is pressed or slid under pressure to perform chip bonding.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら上記従来
の方法によれば、図４(d) に示すように、半導体チップ
６と半導体支持基板７間の半田に気泡８が生じたり、半
田の厚みのバラツキが発生しやすい。その結果、図５に
示すように、放熱特性を阻害し極端な場合には半導体素
子の安全動作領域を狭くする不都合を有している。な
お、図５は半導体チップ６と半導体支持基板７をＰｂ／
３Ｓｎの半田を使用して接着した際の半田厚みに対する
ΔＶBE特性（ベース・エミッタ間順方向電圧の温度依存
性〔２ｍＶ／℃〕を利用して半導体素子の熱抵抗を表す
特性）および半田ボイド（気泡）の大きさを示す図であ
る。However, according to the above-mentioned conventional method, as shown in FIG. 4D, bubbles 8 are generated in the solder between the semiconductor chip 6 and the semiconductor support substrate 7, or the thickness of the solder is reduced. Variation is easy to occur. As a result, as shown in FIG. 5, there is an inconvenience that the heat dissipation characteristics are hindered, and in extreme cases, the safe operation area of the semiconductor element is narrowed. FIG. 5 shows that the semiconductor chip 6 and the semiconductor support substrate 7 are formed of Pb /
ΔV BE characteristics (characteristics representing the thermal resistance of a semiconductor element using the temperature dependency of the forward voltage between the base and the emitter [2 mV / ° C.]) and the solder voids when soldering with 3Sn solder It is a figure which shows the magnitude | size of (bubble).
【０００４】この発明の目的は、半導体チップと半導体
支持基板間の半田を所望の均一な厚さに形成でき、また
さらには半田内に気泡が発生するのを抑制することがで
きる半導体装置の製造方法を提供することである。An object of the present invention can form a solder between the semiconductor chip and the semiconductor support substrate to a desired uniform thickness, also
It is still another object of the present invention to provide a method for manufacturing a semiconductor device which can suppress generation of bubbles in solder.
【０００５】[0005]
【課題を解決するための手段】請求項１記載の半導体装
置の製造方法は、半導体支持基板の表面上に溶融半田を
滴下する工程と、溶融半田を半田拡張治具で加圧成形す
る工程と、加圧成形された溶融半田上に半導体チップを
載置する工程とを含んでいる。請求項２記載の半導体装
置の製造方法は、請求項１記載の半導体装置の製造方法
において、半田拡張治具は、その加圧面に突起部を設け
たことを特徴とする。請求項３記載の半導体装置の製造
方法は、請求項２記載の半導体装置の製造方法におい
て、半田拡張治具の突起部の高さは所望される半田厚さ
と同程度であることを特徴とする。請求項４記載の半導
体装置の製造方法は、請求項１，２または３記載の半導
体装置の製造方法において、半導体支持基板は、溶融半
田を滴下する表面に溝を形成したことを特徴とする。 Means for Solving the Problems] The method according to claim 1, wherein includes the step of dropping the molten solder on the front surface of the semi-conductor support substrate, to pressure molding the molten solder in the solder extended jig And mounting a semiconductor chip on the pressure-molded molten solder. According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect , wherein the solder expanding jig is provided with a projection on a pressing surface thereof. According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect , the height of the protrusion of the solder expanding jig is substantially equal to a desired solder thickness. . The semiconductor according to claim 4.
A method for manufacturing a body device, comprising the steps of:
In the method for manufacturing a semiconductor device, the semiconductor
A groove is formed on the surface on which the rice is dropped.
【０００６】[0006]
【作用】この発明によれば、半導体支持基板に溶融半田
を滴下し、この溶融半田を半田拡張治具により加圧成形
したとき、溶融半田は半導体支持基板上で拡がる。この
とき、半導体支持基板の表面に溝を形成しておけば、そ
の溝に沿って溶融半田が拡がる。また、半田拡張治具の
加圧面に突起部を設けてあれば、溶融半田の厚みは半田
拡張治具の突起部の高さと同程度に形成されるため、所
望される半田厚さと同程度の高さを有する突起部を半田
拡張治具の加圧面に設けておくことが好ましい。その
後、半導体チップを成形した溶融半田上に載置すること
により、溶融半田は半導体チップの外側に拡がり、所望
の均一な半田の厚みが得られる。このとき半導体支持基
板の表面に溝を形成してあれば、半導体支持基板の表面
積を増す役目を果たし、溶融半田が半導体支持基板側に
引き寄せられ半導体チップ下の半田の厚みを増すことを
防止し、半導体チップと半導体支持基板間に気泡が発生
するのを抑制することができる。SUMMARY OF] According to the present invention, was added dropwise a molten solder in a semi-conductor support substrate, when molded under pressure by the molten solder solder expansion jig, spreads in the molten solder semiconductor support substrate. At this time , if grooves are formed on the surface of the semiconductor support substrate,
The molten solder spreads along the grooves. In addition, if a projection is provided on the pressing surface of the solder expansion jig, the thickness of the molten solder is formed to be approximately the same as the height of the projection of the solder expansion jig, and therefore, is approximately the same as the desired solder thickness. It is preferable that a projection having a height is provided on the pressing surface of the solder expanding jig. Thereafter, by placing on the molten solder was molded semiconductor chip, the molten solder spread outside the semi-conductor chip, desired uniform solder thickness is obtained. At this time, if a groove is formed on the surface of the semiconductor support substrate, it serves to increase the surface area of the semiconductor support substrate, and prevents the molten solder from being drawn to the semiconductor support substrate side and increasing the thickness of the solder under the semiconductor chip. In addition, generation of bubbles between the semiconductor chip and the semiconductor support substrate can be suppressed.
【０００７】[0007]
【実施例】以下この発明の一実施例を図を用いて説明す
る。図１はこの発明の一実施例の半導体チップの接着方
法を示す側面図である。図１(a) に示す半導体支持基板
１の中央に溶融半田５を滴下し（図１(b) ）、溶融半田
５の表面を半田拡張治具３により加圧成形する（図１
(c) ）。図２は半導体支持基板１の平面図であり、半導
体支持基板１の表面に、深さ１００μｍ，巾１０〜２０
０μｍの溝２を、横方向（図２(a) ），縦横方向（図２
(b) ）または斜め方向（図２(c) ）に形成してある。ま
た、図３(a) ，(b) はそれぞれ半田拡張治具３の側面
図，底面図であり、半田拡張治具３は底面（加圧面）の
端部４ヵ所に３０μｍの突起部４を形成してある。この
ため、半田拡張治具３で加圧したとき、溶融半田５は半
導体支持基板１上に形成した溝２に沿って拡がり、溶融
半田５の厚みは半田拡張治具３の突起部４の高さと同程
度に形成される。溶融半田５の量が過剰の場合には、半
田拡張治具３の突起部４の間から過剰分の溶融半田５が
逃される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a side view showing a semiconductor chip bonding method according to one embodiment of the present invention. The molten solder 5 is dropped at the center of the semiconductor support substrate 1 shown in FIG. 1A (FIG. 1B), and the surface of the molten solder 5 is pressure-formed by a solder expanding jig 3 (FIG. 1).
(c)). FIG. 2 is a plan view of the semiconductor supporting substrate 1. The surface of the semiconductor supporting substrate 1 has a depth of 100 μm and a width of 10 to 20 μm.
The groove 2 of 0 μm is inserted in the horizontal direction (FIG. 2 (a)) and the vertical and horizontal directions (FIG.
(b)) or in an oblique direction (FIG. 2 (c)). 3 (a) and 3 (b) are a side view and a bottom view, respectively, of the solder extension jig 3. The solder extension jig 3 has 30 μm protrusions 4 at four end portions of the bottom surface (pressure surface). It is formed. For this reason, when pressurized by the solder extension jig 3, the molten solder 5 spreads along the groove 2 formed on the semiconductor support substrate 1, and the thickness of the molten solder 5 is higher than the height of the protrusion 4 of the solder extension jig 3. It is formed to the same degree. If the amount of the molten solder 5 is excessive, the excessive amount of the molten solder 5 escapes from between the protrusions 4 of the solder expansion jig 3.
【０００８】その後、半導体チップ６を成形した溶融半
田５の上部より圧着する（図１(d)）ことにより、溶融
半田５は半導体支持基板１上に形成した溝２に沿って半
導体チップ６の外側に拡がり、半導体チップ６と半導体
支持基板１との間の半田の厚みは、所望の３０μｍ程度
となる。このとき半導体支持基板１の表面に形成された
溝２は、半導体支持基板１の表面積を増す役目を果た
し、溶融半田５が半導体支持基板１側に引き寄せられ半
導体チップ６下の半田の厚みを増すことを防止し、半導
体チップ６と半導体支持基板１間に気泡が発生するのを
抑制することができる（図１(e) ）。[0008] Thereafter, the semiconductor chip 6 is pressed from above the formed molten solder 5 (FIG. 1D), whereby the molten solder 5 is formed along the groove 2 formed on the semiconductor support substrate 1. The thickness of the solder that spreads outward and is between the semiconductor chip 6 and the semiconductor support substrate 1 is about 30 μm as desired. At this time, the groove 2 formed on the surface of the semiconductor support substrate 1 serves to increase the surface area of the semiconductor support substrate 1, and the molten solder 5 is drawn toward the semiconductor support substrate 1 to increase the thickness of the solder under the semiconductor chip 6. This prevents bubbles from being generated between the semiconductor chip 6 and the semiconductor support substrate 1 (FIG. 1 (e)).
【０００９】なお、表１に半導体チップ６と半導体支持
基板１間の半田の厚みに対する半田ボイド（気泡）の発
生率およびΔＶBE特性の不良率を示す。ここで、ΔＶBE
特性の不良率とは、ベース・エミッタ間順方向電圧の温
度依存性〔２ｍＶ／℃〕を利用して半導体素子の熱抵抗
を表す特性の不良率のことである。表１より、最適な半
田の厚みは、２０〜５０μｍであることがわかる。これ
は、半田内に気泡が多いと放熱性が悪くなり、半田の厚
みが薄すぎると放熱特性は良好となるがチップ割れが発
生しやすいためである。Table 1 shows the occurrence rate of solder voids (bubbles) and the defective rate of the ΔV BE characteristic with respect to the thickness of the solder between the semiconductor chip 6 and the semiconductor support substrate 1. Where ΔV BE
The failure rate of the characteristic is a failure rate of the characteristic representing the thermal resistance of the semiconductor element using the temperature dependency [2 mV / ° C.] of the forward voltage between the base and the emitter. From Table 1, it can be seen that the optimum thickness of the solder is 20 to 50 μm. This is because if there are many bubbles in the solder, the heat dissipation will be poor, and if the thickness of the solder is too thin, the heat dissipation characteristics will be good, but chip cracks are likely to occur.
【００１０】[0010]
【表１】 [Table 1]
【００１１】以上のようにこの実施例によれば、溝２を
形成した半導体支持基板１に溶融半田５を滴下し、突起
部４を有する半田拡張治具３で溶融半田５を加圧成形し
た後で、半導体チップ６を圧着することにより、半導体
チップ６と半導体支持基板１間の半田を所望の均一な厚
さに形成できるとともに、半田内に気泡が発生するのを
抑制することができる。As described above, according to this embodiment, the molten solder 5 is dropped on the semiconductor support substrate 1 in which the groove 2 is formed, and the molten solder 5 is pressure-formed by the solder expanding jig 3 having the projection 4. Later, by crimping the semiconductor chip 6, the solder between the semiconductor chip 6 and the semiconductor support substrate 1 can be formed to a desired uniform thickness, and the generation of bubbles in the solder can be suppressed.
【００１２】なおこの実施例では、半田拡張治具３の突
起部４の高さを３０μｍとしたが、１０〜５０μｍの範
囲内であればよい。また、半導体支持基板１の表面に形
成した溝２の深さを１００μｍとしたが、１０〜１００
μｍの深さであればよい。In this embodiment, the height of the projecting portion 4 of the solder expanding jig 3 is set to 30 μm, but may be set within a range of 10 to 50 μm. The depth of the groove 2 formed on the surface of the semiconductor support substrate 1 was set to 100 μm,
The depth may be μm.
【００１３】[0013]
【発明の効果】この発明によれば、半導体支持基板に溶
融半田を滴下し、この溶融半田を半田拡張治具により加
圧成形したとき、溶融半田は半導体支持基板上で拡が
る。このとき半田拡張治具の加圧面に突起部を設けてあ
れば、溶融半田の厚みは半田拡張治具の突起部の高さと
同程度に形成されるため、所望される半田厚さと同程度
の高さを有する突起部を半田拡張治具の加圧面に設けて
おくことが好ましい。その後、半導体チップを成形した
溶融半田上に載置することにより、溶融半田は半導体チ
ップの外側に拡がり、所望の均一な半田の厚みが得られ
る。このとき半導体支持基板の表面に溝を形成してあれ
ば、半導体支持基板の表面積を増す役目を果たし、溶融
半田が半導体支持基板側に引き寄せられ半導体チップ下
の半田の厚みを増すことを防止し、半導体チップと半導
体支持基板間の半田内に気泡が発生するのを抑制するこ
とができる。Effects of the Invention According to the present invention, was added dropwise a molten solder in a semi-conductor support substrate, when molded under pressure by the molten solder solder expansion jig, melt solder Hiroga semiconductor support substrate <br / > At this time, if a protrusion is provided on the pressing surface of the solder expansion jig, the thickness of the molten solder is formed to be substantially the same as the height of the protrusion of the solder expansion jig, and thus the same as the desired solder thickness. It is preferable that a projection having a height is provided on the pressing surface of the solder expanding jig. Thereafter, by placing on the molten solder was molded semiconductor chip, the molten solder spread outside the semi-conductor chip, desired uniform solder thickness is obtained. At this time, make a groove on the surface of the semiconductor support substrate.
Plays a role in increasing the surface area of the semiconductor support substrate,
Solder is drawn to the semiconductor support board side and under the semiconductor chip
Prevents the thickness of the solder from increasing and prevents the semiconductor chip
The generation of bubbles in the solder between the body support substrates can be suppressed.
【図１】この発明の一実施例の半導体チップの接着方法
を示す側面図である。FIG. 1 is a side view showing a method of bonding a semiconductor chip according to an embodiment of the present invention.
【図２】同実施例における半導体支持基板の平面図であ
る。FIG. 2 is a plan view of the semiconductor supporting substrate in the same embodiment.
【図３】(a) は同実施例における半田拡張治具の側面
図、(b) はその底面図である。FIG. 3A is a side view of the solder expanding jig in the embodiment, and FIG. 3B is a bottom view thereof.
【図４】従来の半導体チップの接着方法を示す側面図で
ある。FIG. 4 is a side view showing a conventional semiconductor chip bonding method.
【図５】従来例における半田厚みに対するΔＶBE特性お
よび半田ボイドとの関係を示す図である。FIG. 5 is a diagram showing a relationship between a ΔV BE characteristic with respect to a solder thickness and a solder void in a conventional example.
１ 半導体支持基板 ２ 溝 ３ 半田拡張治具 ４ 突起部 ５ 溶融半田 ６ 半導体チップ DESCRIPTION OF SYMBOLS 1 Semiconductor support substrate 2 Groove 3 Solder expansion jig 4 Projection part 5 Melted solder 6 Semiconductor chip
フロントページの続き (56)参考文献 特開 昭58−23447（ＪＰ，Ａ) 実開 昭54−76669（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/52 H01L 21/58 Continuation of the front page (56) References JP-A-58-23447 (JP, A) JP-A-54-76669 (JP, U) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21 / 52 H01L 21/58
Claims (4)
下する工程と、前記溶融半田を半田拡張治具で加圧成形
する工程と、加圧成形された溶融半田上に半導体チップ
を載置する工程とを含む半導体装置の製造方法。(1) A step of dropping the molten solder to the semiconductor support substrate table surface, a step of pressure molding the molten solder in the solder extended jig, and a step of placing the semiconductor chip on the press molded molten solder above And a method for manufacturing a semiconductor device.
設けたことを特徴とする請求項１記載の半導体装置の製
造方法。2. The method for manufacturing a semiconductor device according to claim 1 , wherein the solder expanding jig has a projection on a pressing surface thereof.
る半田厚さと同程度であることを特徴とする請求項２記
載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 2 , wherein the height of the protrusion of the solder expanding jig is substantially equal to a desired solder thickness.
表面に溝を形成したことを特徴とする請求項１，２またA groove is formed on the surface, wherein the groove is formed.
は３記載の半導体装置の製造方法。4. The method for manufacturing a semiconductor device according to item 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3239529A JP3012045B2 (en) | 1991-09-19 | 1991-09-19 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3239529A JP3012045B2 (en) | 1991-09-19 | 1991-09-19 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0582568A JPH0582568A (en) | 1993-04-02 |
| JP3012045B2 true JP3012045B2 (en) | 2000-02-21 |
Family
ID=17046161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3239529A Expired - Fee Related JP3012045B2 (en) | 1991-09-19 | 1991-09-19 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3012045B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200340929Y1 (en) * | 2003-10-16 | 2004-02-11 | 이건옥 | Puzzle for learning |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4727850B2 (en) * | 2001-06-21 | 2011-07-20 | ローム株式会社 | Semiconductor electronic parts |
| JP2011171766A (en) * | 2011-05-27 | 2011-09-01 | Seiko Instruments Inc | Semiconductor device |
| WO2020195847A1 (en) * | 2019-03-26 | 2020-10-01 | ローム株式会社 | Electronic device and method for manufacturing electronic device |
| CN112992691B (en) * | 2021-04-23 | 2021-09-03 | 度亘激光技术（苏州）有限公司 | Semiconductor device and soldering method thereof |
| JP7653882B2 (en) * | 2021-09-22 | 2025-03-31 | 株式会社東芝 | Semiconductor Device |
-
1991
- 1991-09-19 JP JP3239529A patent/JP3012045B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200340929Y1 (en) * | 2003-10-16 | 2004-02-11 | 이건옥 | Puzzle for learning |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0582568A (en) | 1993-04-02 |
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