JP3012562B2 - Reference voltage generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit, and more particularly, to a CMOS (complementary) circuit.
metal-Oxide semiconductor
The present invention relates to a reference voltage generation circuit that is mounted on a semiconductor integrated circuit of a transistor type and that outputs a predetermined reference voltage quickly when power is turned on in the semiconductor integrated circuit.

[0002]

2. Description of the Related Art As such a conventional circuit, there is a "constant voltage circuit" disclosed in Japanese Patent Laid-Open No. 5-204479.

FIG. 6 is a circuit diagram showing an example of a conventional reference voltage generating circuit.

As shown in FIG. 6, a high-potential power supply terminal Vdd
Are connected to the respective source terminals of the PMOS transistors P1, P2 and P3. Each PMOS transistor P
The gate terminals of 1, P2 and P3 are commonly connected. The drain terminal of the first PMOS transistor P1 is connected to the first
Is connected to the drain terminal of the NMOS transistor N1. The drain terminal of the second P-type transistor P2 is connected to the drain terminal of the second NMOS transistor N2. The gate terminals of the NMOS transistors N1 and N2 are connected to the drain terminal of the first PMOS transistor P1.
The gate terminals of 1, P2 and P3 are connected to the drain terminal of the second N-type transistor N2.

The source terminal of the first NMOS transistor N1 is connected to the anode terminal of the second diode D1, and the source terminal of the second NMOS transistor N2 is connected to the second terminal via the first resistor R. It is connected to the anode terminal of the diode D2. The junction area ratio between the first diode D1 and the second diode D2 is set to 1: N. First diode D1 and second diode D2
Are connected to a low potential power supply terminal Vss. The drain terminal of the third PMOS transistor P3 is connected to the anode terminal of the diode D3 via the second resistor R2, and the cathode terminal of the diode D3 is connected to the low potential Vss. A voltage VO at a connection point between the drain terminal of the third PMOS transistor P3 and the second resistor R2 is output to the output terminal as an output voltage.

A power-on reset circuit C is connected between the high potential power supply terminal Vdd and the low potential power supply terminal Vss. The source terminal of the fourth PMOS transistor P4 is connected to the high-potential power supply terminal Vdd, the gate terminal is connected to the high-potential power supply terminal Vdd via the resistor R1,
The source terminal is connected to a low-potential power supply terminal Vss via a resistor R2.
It is connected to the. The connection point between the gate terminal of the fourth PMOS transistor P4 and the resistor R1 is a diode array D
a is connected to the anode terminal. The cathode terminal of the diode array Da is connected to a low potential power supply terminal Vss. The drain terminal of the PMOS transistor P4 is the output of the power-on reset circuit C. The cathode terminal of the fourth diode D4 is connected to the output RB of the power-on reset circuit C.

The anode terminal of the fourth diode D4 is
It is connected to the gate terminals of the PMOS transistors P1, P2, P3.

The input terminal of the inverter circuit H is connected to the output RB of the power-on reset circuit C. The output terminal of the inverter circuit H has a fifth diode D5
Anode terminal is connected. Fifth diode D
5 is connected to each of the NMOS transistors N1, N
2 gate terminals.

The operation at the time of start-up of the conventional embodiment will be described below.

At power-on, when the potential of the high-potential power supply terminal Vdd is smaller than the voltage drop of the diode array Da, it is in a non-conductive state, so there is no voltage drop due to the resistor R1, and the gate terminal of the PMOS transistor P4 is At the same potential as the source terminal, the PMOS transistor P4 is turned off. Therefore, there is no voltage drop in the resistor R2, and the power-on reset output RB has the low potential of the power supply terminal Vss. Thereafter, when the potential of the high-potential power supply terminal Vdd becomes larger than the voltage drop of the diode array Da, the diode array Da becomes conductive, so that a voltage drop occurs due to the resistor R1, and the gate terminal of the PMOS transistor P4 is connected to the source terminal. Becomes low potential, and when the potential difference exceeds the threshold voltage of the PMOS transistor P4, the PMOS transistor P4 is turned on.

As a result, a voltage drop occurs due to the resistor R2, and the power-on output RB becomes the high potential of the power supply terminal Vdd.

Next, referring to FIG. 7 showing the voltage / time characteristics, the output RB of the power-on reset circuit C becomes Vss immediately after the power is turned on, and the inverter circuit H and the fifth diode The voltage Vdd is applied to the gate terminals of the NMOS transistors N1 and N2 via D5, and the voltage Vss via the fourth diode D4 to the gate terminals of the PMOS transistors P1, P2 and P3.
Is applied, and the respective NMOS transistors N1, N
The voltage Vdd is applied to the gate terminal 2 and the voltage Vss is applied to the gate terminals of the PMOS transistors P1, P2 and P3 via the fourth diode D4, and the gate potential of each MOS transistor is determined. As a result, the output VO of the reference voltage generation circuit at the time of start-up is quickly activated, follows the high-potential power supply, and increases.

Thereafter, at ta, the power-on reset circuit C
Of the PMOS transistors P1, P2, and V4 via the fourth and fifth diodes D4 and D5.
By stopping the application of the voltage to the gate terminals of the P3 and the NMOS transistors N1 and N2, the start-up is released and a predetermined output voltage Vref is obtained.

[0014]

In the conventional circuit example, the start-up is canceled when the potential of the power supply terminal Vdd becomes larger than the voltage drop of the diode array Da, so that the PMOS transistor P4 becomes conductive and the power is turned off. This is completely performed when the potential of the ON output RB becomes equal to the potential of the power supply terminal Vdd. That is, the PMOS transistor P
Even when 3 becomes conductive, the start-up release may not be performed, and the output voltage VO may exceed the predetermined output voltage Vref as shown in FIG. [Object of the Invention] An object of the present invention is to provide a reference voltage generating circuit in which an output voltage after power-on follows a high-potential power supply and becomes large and does not exceed a predetermined output voltage.

[0015]

The present invention has the following circuit as means for solving the above-mentioned problems.

The source terminals of the first, second, third, fourth, fifth, and sixth first conductivity type MOS transistors are connected to the first power supply terminal. The gate terminals of the first, second, third, and fourth first conductivity type MOS transistors are commonly connected, and the drain terminal of the first first conductivity type MOS transistor is connected to the first second MOS transistor. Conductive MOS
The drain terminal of the second first conductivity type MOS transistor is connected to the drain terminal of the transistor, and the drain terminal of the second first conductivity type MOS transistor is connected to the drain terminal of the second second conductivity type MOS transistor. A gate terminal is connected to a gate terminal of the second second conductivity type MOS transistor, and a gate terminal of each of the first and second second conductivity type MOS transistors is connected to the first and fifth fifth MOS transistors. A gate terminal of each of the first, second, third, and fourth first conductivity type MOS transistors is connected to a drain terminal of the one conductivity type MOS transistor. A first second conductivity type MOS connected to a drain terminal of a MOS transistor;
The source terminal of the transistor is connected to one terminal of the first diode, and the second second conductivity type MOS transistor is connected to the first diode.
The source terminal of the transistor is connected to the second terminal via the first resistor.
Are connected to one terminal of a diode. The other terminals of the first diode and the second diode are connected to a second power supply terminal, and the drain terminal of the third first conductivity type MOS transistor is connected to the sixth first conductivity type MO transistor.
Connected to the drain terminal of the S transistor, connected through a second resistor to one terminal of a third diode, the other terminal of the third diode is connected to the second power supply terminal, The drain terminal of the fourth first conductivity type MOS transistor is connected to one end of a first capacitive element C1, the gate terminal of the fifth first conductivity type MOS transistor, and the gate of the sixth first conductivity type MOS transistor. The other end of the first capacitance element is connected to the second power supply terminal, and the drain terminal of the third first conductivity type MOS transistor is connected to the sixth first conductivity type MOS transistor.
A reference voltage generation circuit for outputting a voltage at a connection point between a drain terminal of a transistor and the second resistor as an output voltage.

Further, according to the present invention, the third first conductivity type M
Adding a third second conductivity type MOS transistor between the drain terminal of the OS transistor and the second resistor;
A gate terminal of the third second conductivity type MOS transistor is connected to one end of the first capacitance element, and a drain terminal of the third second conductivity type MOS transistor is connected to the third first conductivity type MOS transistor.
A drain terminal of the third conductivity type MOS transistor; a source terminal of the third second conductivity type MOS transistor connected to one end of the second resistor;
The drain terminal of the OS transistor, the drain terminal of the sixth first conductivity type MOS transistor, and the third second
A reference voltage generating circuit for outputting, as an output voltage, a voltage at a connection point of a conductive type MOS transistor with a drain terminal.

The present invention also relates to the fourth first conductivity type MO.
The drain terminal of the S transistor is connected to the second power supply terminal via a third resistance element R3, and the drain terminal of the third first conductivity type MOS transistor is connected to the drain terminal of the sixth first conductivity type MOS transistor. Drain terminal and the third
A reference voltage generating circuit for outputting, as an output voltage, a voltage at a connection point with the drain terminal of the second conductivity type MOS transistor.

[Operation] According to the present invention, a reference voltage generating circuit can be realized in which the output voltage after power-on follows a high-potential power supply and increases and does not exceed a predetermined output voltage.

The present invention is characterized in that the output terminal (Vref) is pulled up to the power supply voltage side by using the signal of the start-up circuit, and the current path is cut off to the GND side.

As shown in FIG. 1, after the power is turned on, the gate of P6 is grounded via the capacitor C1 to be turned on, thereby outputting the output VO.
At the same time, the gate of P5 is grounded via the capacitor C1 to be turned on, thereby starting the reference voltage generating circuit.

Thereafter, the capacitor C1 is charged by the drain current of P4 forming a current mirror with P2 to turn off P6 to release the pull-up, and simultaneously release P5 to release the activation.

[0023]

【Example】

[First Embodiment] FIG. 1 is a circuit diagram showing an example of a reference voltage generating circuit according to the present invention.

As shown in FIG. 1, a high potential power supply terminal Vdd
Include PMOS transistors P1, P2, P3, P4
The source terminals of P5 and P6 are connected. Each PMO
The gate terminals of the S transistors P1, P2, P3, and P4 are commonly connected. First PMOS transistor P1
Is connected to the drain terminal of the first NMOS transistor N1. The drain terminal of the second P-type transistor P2 is connected to the drain terminal of the second NMOS transistor N2. First NMOS
The gate terminals of the transistor N1 and the second NMOS transistor are commonly connected. The gate terminal of each NMOS transistor N1, N2 is connected to each PMOS transistor P
1, P5 connected to the drain terminal
The gate terminals of the transistors P1, P2, P3, P4 are:
It is connected to the drain terminal of the second N-type transistor N2.

The source terminal of the first NMOS transistor N1 is connected to the anode terminal of the first diode D1, and the source terminal of the second NMOS transistor N2 is connected to the second terminal via the first resistance element R1. Diode D
2 anode terminals. The junction area ratio between the first diode D1 and the second diode D2 is set to 1: N. Each cathode terminal of the first diode D1 and the second diode D2 is connected to a low potential power supply terminal Vss. The drain terminal of the third PMOS transistor P3 is connected to the drain terminal of the sixth PMOS transistor P6, and is connected to the anode terminal of the third diode D3 via the second resistor R2.
The cathode terminal of the third diode D3 is connected to the low potential power supply terminal Vss.

The drain terminal of the fourth PMOS transistor P4 is connected to one end of the first capacitive element C1 and the fifth PMOS transistor P4.
The gate terminal of the transistor P5 is connected to the gate terminal of the sixth PMOS transistor P6.

The output terminal includes the drain terminal of the third PMOS transistor P3, the second resistor R2, and the sixth PMOS transistor P2.
Voltage V at the connection point with the drain terminal of S transistor P6
O is output as an output voltage.

In the reference voltage generation circuit having the above configuration, for example, the PMOS transistors P1, P2 and P
3. Make the gate length and gate width of 3 the same size,
If the gate length and gate width of the NMOS transistors N1 and N2 are set to the same size, a predetermined output voltage Vr
ef is obtained from the following equation.

Vref = M · (k · T / q) · 1nN + VF (D3) (1) where: M; (resistance value of R2) / (resistance value of R1) N; (joint area of D2) / (Junction area of D1) q: charge amount of electron, k: Boltzmann constant, T: absolute temperature VF (D3); forward voltage of D3 Next, the voltage / time characteristics of the operation at start-up are shown. This will be described with reference to FIG.

At t0 immediately after the power is turned on, the gate of the PMOS transistor P6 is grounded via the capacitive element C1, the PMOS transistor P6 is turned on, and the output voltage VO is pulled up by the PMOS transistor P6. It follows the high power supply potential Vdd and increases. At t0 immediately after the power is turned on, the gate of the PMOS transistor P5 is also grounded via the capacitive element C1, so that the PMOS transistor P5 is turned on, and the NMOS transistors N1 and N2 are also turned on. The generator is activated.

Thereafter, the capacitance element C1 is charged by the drain current of the PMOS transistor P4 forming a mirror with the PMOS transistor P2, and the gates of the PMOS transistors P5 and P6 become the same potential as the power supply potential Vdd. A non-conductive state is established, and activation and pull-up release are performed.

Therefore, the start-up release is performed in response to the start of the reference voltage generating circuit.
It is possible to provide a reference voltage generating circuit that does not exceed the predetermined output voltage Vref shown in the equation (1).

[Second Embodiment] Referring to FIG. 4 showing a second embodiment of the present invention, the difference from the first embodiment is as follows.
The gate terminal is connected between the output terminal and the second resistor R2 by PMO.
Third N connected to the drain terminal of S transistor P4
That is, the MOS transistor N3 is added. The other components are the same, and the same components are denoted by the same reference numerals and description thereof will be omitted.

In the circuit configuration of the first embodiment of the present invention, as shown in FIG. 3, when the rising speed of the power supply potential Vdd after the power is turned on is steep, an evaluation result is obtained that the output voltage VO rises with a slight delay. Have been.

In the second embodiment, even if the rising speed of the power supply potential Vdd after the power is turned on is steep, the NMOS transistor N3 is added so that this N
Since the low power supply potential Vss is applied to the gate of the MOS transistor N3 via the capacitance element C1, the output of the reference voltage generation circuit is disconnected from the low power supply potential.
The output voltage VO after power-on follows the high-potential power supply Vdd and increases.

Thereafter, the capacitance element C1 is charged by the drain current of the PMOS transistor P4 forming a mirror with the PMOS transistor P2, becomes the same potential as the gate power supply potential Vdd of N3, and the NMOS transistor N3 becomes conductive. It is possible to provide a reference voltage generating circuit that does not exceed the predetermined output voltage Vref shown in the expression (2).

[Third Embodiment] Referring to FIG. 5 showing a third embodiment of the present invention, the difference from the second embodiment is that
This means that the drain terminal of the MOS transistor P4 is grounded via the third resistance element R3. The other components are the same, and the same components are denoted by the same reference numerals and description thereof will be omitted.

In this embodiment, once (1)
When the predetermined output voltage Vref shown in the equation is output, the power supply is cut off, and the power supply is immediately turned on again, the electric charge once accumulated in the capacitance element C1 is transferred to the resistance element R1.
By removing the charge in step 3, the output voltage after turning on the power again
It is possible to provide a reference voltage generating circuit which increases following the high-potential power supply and does not exceed the predetermined output voltage Vref shown in the equation (1).

[0039]

As described above, according to the present invention, it is possible to realize a reference voltage generating circuit in which the output voltage after power-on follows a high-potential power supply and increases, and does not exceed a predetermined output voltage. effective.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing a voltage / time characteristic of the first embodiment of the present invention.

FIG. 3 is a characteristic diagram showing the voltage / time characteristics of the first embodiment of the present invention, particularly when the power supply potential rises sharply.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a first conventional example.

FIG. 7 is a characteristic diagram showing a voltage / time characteristic of the first conventional example.

[Explanation of symbols]

 P1 to P6 P-type MOS transistor N1 to N3 N-type MOS transistor R1 to R3 Resistance element D1 to D3 Diode C1 Capacitance element C Power-on reset circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-9-179646 (JP, A) JP-A-9-81252 (JP, A) JP-A-2-214911 (JP, A) JP-A-3-3 288217 (JP, A) JP-A-3-242715 (JP, A) Japanese Utility Model Application Sho 62-154519 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G05F 3/30 G05F 3 /twenty four

Claims (3)

(57) [Claims] A first, a second, a third, a fourth, a fifth and a sixth
One end of each first conductivity type MOS transistor is connected to a first power supply terminal, the other end of the first first conductivity type MOS transistor is connected to the other end of the first second conductivity type MOS transistor, The other end of the second first conductivity type MOS transistor is connected to the other end of the second second conductivity type MOS transistor, and the gates of the first and second second conductivity type MOS transistors are commonly connected. Connected to the other ends of the first and fifth first conductivity type MOS transistors,
A gate of each of the first, second, third, and fourth first conductivity type MOS transistors is connected to the other end of the second second conductivity type MOS transistor, and the first second conductivity type MOS transistor is connected to the first second conductivity type MOS transistor.
One end of the S transistor is connected to the anode side of the first diode, one end of the second second conductivity type MOS transistor is connected to one end of the first resistor, and the other end of the first resistor is connected to the second end. And the cathodes of the first and second diodes are connected to a second
And the other end of the third first-conductivity-type MOS transistor is connected to the other end of the sixth first-conductivity-type MOS transistor and to one end of a second resistor. The other end of the second resistor is connected to the anode side of the third diode, the cathode side of the third diode is connected to the second power supply terminal, and the other end of the fourth first conductivity type MOS transistor is connected. Is connected to one end of a first capacitance element, the gate of the fifth first conductivity type MOS transistor and the gate of the sixth first conductivity type MOS transistor, and the other end of the first capacitance element is connected to the first 2 and the other end of the third first conductivity type MOS transistor and the sixth
A reference voltage generating circuit, wherein a connection point between the other end of the first conductivity type MOS transistor and one end of the second resistor is used as an output terminal. 2. A third second MOS transistor, which is connected between the other end of the third first conductivity type MOS transistor and one end of the second resistor.
A conductivity type MOS transistor is added, the gate of the third second conductivity type MOS transistor is connected to one end of the first capacitance element, and the other end is connected to the other end of the third first conductivity type MOS transistor. And one end is connected to one end of the second resistor, and the other end of the third first conductivity type MOS transistor, the other end of the sixth first conductivity type MOS transistor, and the third second 2. The reference voltage generation circuit according to claim 1, wherein a connection point with the other end of the conductivity type MOS transistor is used as an output terminal. 3. The other terminal of the fourth first conductivity type MOS transistor is connected to one end of a third resistor, and the other end of the third resistor is connected to the second power supply terminal. And the other end of the sixth first conductivity type MOS transistor, the other end of the sixth first conductivity type MOS transistor, and the third second conductivity type MO transistor.
2. The reference voltage generating circuit according to claim 1, wherein a connection point with the other end of the S transistor is used as an output terminal.