JP3017240B2 - Synchronous circuit of image scanning device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit for an image scanning apparatus, and more particularly to an image scanning apparatus for scanning a laser beam by a rotary deflection unit used in a laser printer or the like. The present invention relates to a synchronization circuit for achieving synchronization.

[Conventional technology]

As a synchronizing circuit of a conventional image scanning apparatus, Japanese Patent Laid-Open No.
There is one disclosed in Japanese Patent No. 243910.

Referring to FIG. 16, the optical system of the image scanning apparatus to which the prior art is applied will be described.
The output beam from 01 becomes parallel light by a collimator lens 1602, is deflected by a rotary deflector 1603 composed of a rotating polygon mirror, and is imaged as a scanning spot on a photosensitive body 1605 which is an object to be scanned by an fθ lens 1604. . The laser beam is modulated by a recording signal, and the surface of the photoconductor 1605 is main-scanned by the rotary deflector 1603 to form an electrostatic latent image thereon. The sub-scan is executed by rotating the photoconductor 1605 around its axis.

The optical sensor 1606 is a light detection element such as a photodiode provided outside the image recording area on the main scanning line, and detects a laser beam from the rotary deflector 1603 to detect a light detection signal DETP.
Is output.

The electrical control system of the image scanning device will be described with reference to FIG.

The synchronization circuit 1701 functions as an image scanning clock generation circuit, and when a light detection signal DETP is input from the light sensor 1606,
An image scanning clock WCLK synchronized therewith is supplied to the image control circuit 17.
Output to 02.

As described above, since the optical sensor 1606 is provided outside the image recording area, the image control circuit 1702 counts WCLK until the light beam reaches the image recording area or until a predetermined space is taken. , Starts sending a control signal to the character generator 1703.

The character generator 1703 outputs an image information signal synchronized with WCLK for each main scanning line according to the control signal, and the image information signal is sent to the light source driving circuit 1704 via the image control circuit 1702.

The light source driving circuit 1704 determines the 16th light source according to the image information signal.
The semiconductor laser 1601 shown in the figure is modulated (flickered) to form an electrostatic latent image for one line on the photoconductor 1605.

In some cases, when the optical sensor 1606 detects a light beam, the image control circuit 1702 outputs a synchronization circuit 17 for each line.
A reset signal LSYC can also be sent to 01.

Although an example in which a semiconductor laser is used as a light source has been described, a gas laser, for example, a He-Ne laser is used as a light source, and an optical modulation element such as an acousto-optic element driven by a light source driving circuit 1704 instead of the collimator lens 1602 is used. Elements may be arranged to modulate the laser beam.

FIG. 18 is a block diagram showing a configuration of a conventional synchronous circuit 1801.

The synchronization circuit 1801 includes a reference clock oscillator 1802, a delay circuit 1803, a latch circuit 1804, a clock selection circuit 1805, and a delay clock management circuit 1806 provided between the delay circuit 1803 and the latch circuit 1804.

The reference clock oscillator 1802 oscillates and outputs a reference clock signal (hereinafter, referred to as “reference clock”) CK1 having the same frequency as the image scanning clock WCLK.

The delay circuit 1803 receives the reference clock CK1 (n−
1) Clock signal groups CK2, CK3... CK whose output terminals have the same frequency and waveform as the reference clock CK1 and whose phases are delayed by approximately 1 / n of the cycle (hereinafter referred to as "clock groups").
n is output (in the figure, an example in the case of n = 7 is shown).

The latch circuit 1804 receives the light detection signal DE from the light sensor 1807.
The n inputs are latched by the rise of TP, and the latch signals Q1 to Qn and Is output.

The clock selection circuit 1805 outputs the latch signals Q1 to Qn and Of the clock groups CK1 to CKn, the clock having the highest phase of the light detection signal DETP is selected and output as the image scanning clock WCLK.

As shown in FIG. 3, the delayed clock management circuit 1806 generates p clock groups CK (n-p + 1) to CKn (CK5 to CK in the illustrated example) of the clock groups CK1 to CKn having a relatively long delay time.
7) is input and passed as it is or locked to "1" or "0" depending on the phase delay from the reference clock CK1, and the signals G (n-p + 1) to Gn are output.

The clock selection circuit 1805 includes, for example, as shown in FIG. 2, n AND circuits 201 to 207 (seven in the figure) and one OR circuit 208 to which each output is input.

Then, the input Dk and ▲ are input to the k-th AND circuit.
▼, that is, latch signals Qk and ▲ ▼ and clock CK (k + 1) are input,
The gate of the clock CK (k + 1) is formed by Qk. However, k = n, that is, only at the last stage, the latch signal Qn, ▼, and the clock CK1 are input.

Note that, here, for simplicity of explanation, the clock CK
(K + 1) is gated, but actually, the delayed clock management circuit 1806, the latch circuit 1804, and the AND circuit 201
Since the gates open and close due to the overlap of the operation delays of to 207, they are often combined with a clock delayed about an anti-period to ensure the operation.

The delay circuit 1803 includes a delay line using an inductor, and may include an IC for shaping an output waveform from the delay line. These delay circuits vary in delay time due to variations in individual characteristics and changes in temperature characteristics, and the delay clock management circuit 1806 stabilizes the operation of the synchronous circuit with respect to the variations and changes. Here, if the delay time varies or changes to a smaller one and the timing is as shown in FIG. 19, the clocks CK1 to CK7 having the same period of 1 and 0, that is, 50% duty, are output from the delay circuit 1803. First, assuming that CK7 has the timing shown by the solid line, CK7 is 1 at the rise of CK1, and G5 to G7 are all 1, so each period t _{a to} t of one cycle of the clock. Light detection signal at _{f '}
When DETP is input, the clock marked with ● is selected, and the logical value at that time is as shown in FIG. That is
In the period t _a, k = 1 of logic value 1 becomes CK2 is selected, CK6 in period t _f (k = 6 1), each of CK1 (k = 7 is 1) during a period of t f _' Selected. Also, if CK7 has the timing as shown by the broken line, when CK1 rises, C
Since K7 is 0, G5 and G6 are 1 and G7 is 0, and a clock marked with a circle is selected in each period, and T
_In the period _{A '} , the logical values as shown in FIG. 21 are obtained, that is, the logical values of K = 1 and K = 6 become 1, CK2 and CK7 are selected at the same time, and as shown at the bottom of FIG. Is output as a scanning clock. Generally, the image control circuit 1808 uses one of the rising edge and the falling edge of the clock for timing control, so that a slight change in duty does not matter. During the period t _F is the same as t _f, also other periods is the same logical value as FIG. 20, the correct operation is performed in any period.

[Problems to be solved by the invention]

However, in the above-described conventional technology, the delay circuit 1803 generally uses a delay line such as an inductor, and the rising and falling waveforms of the output waveform with respect to the input waveform have individual characteristics variations. , 22nd
As shown in the figure, when a clock with a long duty of 1 period is output, CK7 is 1 when CK1 rises.
G5~G7 is 1, the logical value in the period of t _d and t _{d 'is} the
23, that is, during the period of t _d , the logical value of k = 4 becomes 1 and CK5 is selected, but during the period of t _{d ′} , k = 4
Since the logical values of 4 and k = 7 become 1 and CK5 and CK1 are selected at the same time, the output of the OR circuit 208 is a clock as shown at the bottom of FIG. This clock has a very small waveform in the period of 0, and the image control circuit
In 1808, for example, when a counter or the like for timing control is operated, there is a high possibility that a count error occurs, and there is a problem that normal image scanning cannot be satisfied.

The present invention has been made in view of the above, and has been made in view of the above, and has a clock selection error caused by a variation in delay characteristics of a delay circuit, a variation in delay characteristics due to a variation in temperature conditions, and a variation in operation characteristics of each constituent element. The purpose of the present invention is to prevent the malfunction of the image control circuit due to the above and to always select the clock correctly under all the above conditions.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a reference clock and clock generating means for generating a plurality of clocks having the same frequency as the reference clock and having sequentially delayed phases, Duty changing means for making the duty of the delayed clock different from the duty of the reference clock; clock selecting means for selecting at least one clock from the plurality of clocks by inputting a synchronization signal prior to image scanning; A clock managing unit that determines the plurality of clocks that have passed through the duty changing unit and manages a clock delayed by a predetermined amount or more from the reference clock so as not to be selected; and an image scanning clock based on the selected clock. Image scanning clock generating means for generating It is intended to provide a circuit.

A clock generating means for generating a reference clock and a plurality of clocks having the same frequency as the reference clock and having sequentially delayed phases; and at least one of the plurality of clocks by inputting a synchronization signal prior to image scanning.
Clock selecting means for selecting a clock, clock managing means for determining the plurality of clocks and managing a clock delayed by one or more cycles from the reference clock so as not to be selected, and based on the selected clock. An image scanning clock generating means for generating an image scanning clock, wherein the clock generating means provides a synchronous circuit of an image scanning apparatus for generating a plurality of clocks including a clock having a phase delayed by one cycle or more from the reference clock. Things.

A clock generating means for generating a reference clock and a plurality of clocks having the same frequency as the reference clock and sequentially delaying phases; and setting a duty of the clock having the most delayed phase among the plurality of clocks to the duty of the reference clock. Duty changing means for making the duty different from the duty, clock selecting means for selecting at least one clock from a plurality of clocks passed through the duty changing means by input of a synchronization signal prior to image scanning, and discriminating the plurality of clocks A clock management unit that manages a clock delayed by a predetermined amount or more from the reference clock so as not to be selected; and an image scanning clock generation unit that generates an image scanning clock based on the selected clock. The clock selecting means, based on the input of the synchronization signal, At least one clock having the closest rising or falling phase is selected from among the plurality of clocks that have passed through the duty changing unit, and the clock management unit determines that the clock selection unit has started up from among the plurality of clocks. The clock selected by the phase is a falling phase, and the clock selected by the clock selecting means is a rising phase. The clock is controlled so that a clock delayed by a predetermined amount or more from the reference clock is not selected. A synchronous circuit of an image scanning device is provided.

[Action]

In the synchronization circuit of the image scanning apparatus according to the present invention, the clock to be managed by the clock management circuit under all conditions including the variation of the delay characteristic and the change of the delay characteristic due to the change of the temperature condition. Is made larger or smaller than the duty of the reference clock.

Further, the clock generation means generates a plurality of clocks including a clock whose phase is delayed by one cycle or more from the reference clock.

Further, the clock selecting means selects at least one clock having the closest rising or falling phase from among the plurality of clocks by inputting the synchronization signal.
When the clock management means selects the plurality of clocks from the plurality of clocks with the rising phase, the clock selection means selects the falling phase with the falling phase, and the clock selection means selects the plurality of clocks with the falling phase with the rising phase. Management is performed so that a clock delayed by a predetermined period or more from the same phase of the clock is not selected.

[Embodiment] Hereinafter, a first embodiment of a synchronization circuit of an image scanning device according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a synchronizing circuit of an image scanning apparatus according to the present invention. Among the inputs of a latch circuit 101, a terminating resistor 102 is provided at an input stage of a clock CK7 having the most delayed phase, so that a reference clock can be used. On the other hand, a clock having a small duty in one period of the clock waveform is used.
, The delay circuit 105, the clock management circuit 106, and the latch circuit 101 perform the same operation as the above-described conventional example of FIG.

The delayed clock management circuit 106 generates the p clock groups CK (n−p +
1) A signal G that locks CKn to “1” or “0” depending on whether or not the phase delay from the reference clock CK1 is within one cycle.
(N-p + 1) to Gn (n = 7, p =
3 is shown).

The clock selection circuit 107 includes, for example, seven AND circuits 201 to 207, as shown in FIG.
The processing of a group of clocks constituted by the OR circuits 208 and not managed by the delay clock management circuit 106 is performed by the logical product Qk and the same as the clock selection circuit 1805 shown in FIG. Each of the managed clock groups is AND circuit 201 by the logical product Qk, ▲ ▼, and Gk.
To 207 are configured to open and close.

FIG. 3 shows an example of the delay clock management circuit 106, which is composed of three D-FFs 301 which latch the input clocks CK5 to CK7 at the rise of the reference clock CK1.

As described in the delay clock management circuit 106 shown in FIG. 3, when each D-FF 301 latches the D input at the rise of the reference clock CK1, the clock CKk as the D input becomes “1” (delay time If it is less than one cycle), the output Gk is locked to "1", and if it is "0", the output Gk is locked to "0".

The operation of the above configuration will be described. The case where the rising phase of CK7 is a delay of one cycle or less (solid line) with respect to the rising of CK1 as shown in FIG.

Input waveform of the delayed clock management circuitry 106 is as shown in FIG. 5, i.e., with respect to V _H1 of the reference clock CK1, CK7
Low as V _H7 by the termination resistor 102, when viewed in decision reference level V _TH of 1 and 0 in the delay clock management circuit 106, CK7 to time t ₁ which CK1 is determined to 1, and t ₇ It becomes shorter, in other words, the duty becomes smaller. The same applies to the latch circuit 101. During the period in which the light detection signal DETP from the optical sensor 109 is determined to be 1 when CK7 is shorter than CK1.

Here, first, when the rising phase of CK7 is within one cycle of the rising edge of CK1 (solid line), the light detection signal DETP is input during each of the periods t _{a to} t _{f ′.} , The clocks marked with ○ are selected. That is, since CK7 is 1 at the rise of CK1, G5
~G7 is 1, in the period t _a, as shown in Figure 6,
When k = 1, the logical value becomes 1, and CK2 is selected.

Also, during the period of t _d (t _{d ′} ) where there was a problem in the conventional example, CK7 is 0 because the duty of CK7 is smaller than that of CK1 as described above. Absent. In any other period, one clock is always selected. For example, in the period of tf _' , the logical value of k = 7 becomes 1, CK1 is selected, and the scan clock is output correctly.

Next, when the rising phase of CK7 is one cycle or more behind the rising of CK1 (broken line), since CK7 is 0 at the rising of CK1, G5 and G6 are 1 and G7 is 0. When the light detection signal DEPT is input in each period,
Clocks marked with ● are selected. That is, during the period of tA _' , the logical values of k = 1 and k = 6 become 1 as shown in FIG. 6, so that CK2 and CK7 are simultaneously selected, and the output of the OR circuit 208 is shown in FIG. The waveform has a slightly increased duty as shown at the bottom of the figure, but is not enough to cause the image control circuit 108 to malfunction.
Further, in the period t _F, the logical value becomes 1 of k = 6 from Figure 6, CK7 is selected, in other periods, any one clock is selected, t was a bug in the conventional example _In the period _d , since G7 is 0, k = 7.
Is 0, and therefore CK1 is not selected, so that an image scanning clock that causes the image control circuit 108 to malfunction does not occur.

In the embodiment, the clocks CK5 to CK5 to be managed by the delay clock management circuit 106 are controlled by the terminating resistor 102.
Although the duty of CK7 is reduced, for example, elements having different threshold levels can be used in the input stages of CK1 and CK7 of the delay clock management circuit 106 and the latch circuit 101.

In the embodiment, the duty of CK7 is described as being reduced. However, in the circuit configuration in which the latch circuit 101 and the delay clock management circuit 106 each determine the phase of the falling edge of the clock, the duty of CK7 may be increased. Obviously the same effect can be achieved by

 Next, a second embodiment of the present invention will be described.

FIG. 7 is a block diagram of a synchronous circuit according to the present invention, in which a delay clock management circuit 703 is provided between a delay circuit 701 and a clock selection circuit 702.

In the delay circuit 701, the clock at the final stage (CK8 in the example of FIG. 7) must be at least one cycle longer than the reference clock CK1 among all conditions including variations in delay characteristics and changes in delay time due to changes in temperature. It is configured to have a phase lag.

In this synchronous circuit 704, a reference clock oscillator 705 and a latch circuit 706 perform exactly the same operation as the conventional example shown in FIG.

The delay clock management circuit 703 generates the p clock groups CK (n-p +
1) A signal G that locks CKn to “1” or “0” depending on whether or not the phase delay from the reference clock CK1 is within one cycle.
(N-p + 1) to Gn are output (in the figure, n = 8, p =
4 is shown).

The clock selection circuit 702 includes, for example, eight AND circuits 801 to 809 as shown in FIG.
The processing of a group of clocks that is constituted by the OR circuits 810 and is not managed by the delay clock management circuit 703 is performed by the logical product Qk and the same as the clock selection circuit 1805 shown in FIG. Each of the managed clock groups is AND circuit 801 by the logical product Qk, ▲ ▼, and Gk.
807 is configured to open and close.

FIG. 9 shows an example of the delay clock management circuit 703, which is composed of four D-FFs 901 which respectively latch the input clocks CK5 to CK8 at the rise of the reference clock CK1.

As described in the delay clock management circuit 703 shown in FIG. 9, when each D-FF 901 latches the D input at the rise of the reference clock CK1, the clock CKk as the D input becomes “1” (delay time If it is less than one cycle), the output Gk is locked to "1", and if it is "0", the output Gk is locked to "0".

As the duty of the output clock of the delay circuit 701 were those found the following 1 period greater than the period of 0, will be described with respect to the operation of the present embodiment, is like the Figure 10, t _a ~
In each period of tf _' , the clocks marked with a circle are selected, and the logical values at that time are as shown in FIG. That is, since CK8 is 0 at the rise of CK1, G5
~G7 is 1, G8 is 0, in the period t _a, k = 1 and k
= 7 becomes the logical value 1 and CK2 and CK8 are selected at the same time. However, since the difference between the two phases is small, the output of the OR circuit 810 uses the clock as shown in the lower part of FIG. 10 as the image scanning clock. Is output.

Next, during the period of td _' where there was a problem in the conventional example, the logical value of k = 8 becomes 0 because G7 is 0, and CK
When 1 is not selected and only CK5 is k = 4, the logical value is 1, so that it is selected and a normal operation is performed. In addition, normal operation is performed in other periods.

In the delay clock management circuit, a clock as a reference for determination (CK1 in the above embodiment) and a synchronous circuit for reducing or increasing the duty of the clock with the most delayed phase among a plurality of clocks to be determined. In the first embodiment, an element for determining the phase of each clock in the latch circuit and an element for determining the phase of each clock in the delay clock management circuit have variations among the elements. At the phase timing as shown in FIG. 4, when the discrimination level (threshold level) of the phase discriminating element of the delay clock management circuit is higher than the discrimination level of the phase discriminating element of the latch circuit in the same clock, CK
G5G6 Since the first rise time CK7 is 0 1, G7 becomes zero, in the period t _F, if there is no difference in the discrimination level of the device, the logical value of K = 6 as in the sixth diagram 1 Becomes CK7
Will be selected.

However, if the discrimination levels of the elements have the above-described difference, the clock management circuit determines that CK7 is 0 at the rise of CK1, that is, despite the fact that G7 is locked at 0, the latch circuit determines tf _′ . When the light detection signal DETP is input during the period, the case where CK7 is determined to be 1 occurs,
As shown in FIG. 6, there is a problem that any logical value of k = 1 to 7 becomes 0 and a clock is not selected.

As described above, variations in delay circuit characteristics, fluctuations in delay characteristics due to fluctuations in temperature conditions, and elimination of scan clocks due to selection of clocks with greatly different phases due to variations in operation characteristics of each constituent element, etc. A third embodiment in which a clock is always correctly selected by preventing the clock from disappearing because no clock is selected will be described below.

FIG. 12 is a block diagram showing the configuration of a third embodiment of the present invention. Inverters for inverting input clocks between a delay circuit 1201 and a delay clock management circuit 1202, respectively.
1203 is provided, and a terminating resistor 1205 is provided at the input stage of the clock CK7 with the most delayed phase among the input clocks of the latch circuit 1204. It is getting smaller. In the synchronization circuit 1206, the reference clock oscillator 1207, the delay circuit 1201, the latch circuit 1204, and the delay clock management circuit 1202 operate exactly the same as in the conventional example.

The delay clock management circuit 1202 generates the p clock groups CK (n-p +) having the longer delay time input from the delay circuit 1201.
1) A signal G that locks CKn to “1” or “0” depending on whether or not the phase delay from the reference clock CK1 is within one cycle.
(N-p + 1) to Gn (n = 7, p =
3 is shown).

The clock selection circuit 1208 includes, for example, seven AND circuits 201 to 207 and one input for each output as shown in FIG.
The processing of a group of clocks constituted by the OR circuits 208 and not managed by the delay clock management circuit 1202 is performed by the logical product Qk and the same as the clock selection circuit 1805 shown in FIG. 18 and by the delay clock management circuit 1202. Each of the managed clock groups is AND circuit 201 by the logical product Qk, ▲ ▼, and Gk.
To 207 are configured to open and close.

FIG. 3 shows an example of the delay clock management circuit 1202. The inverted output of the input clocks CK5 to CK7 is generated by the rising of the inverted reference clock ▲ ▼ by the inverter 1203 of the reference clock CK1. Are latched by three D-FFs 110.

As described in the delay clock management circuit 1202 shown in FIG. 3, when each D-FF 301 latches the D input at the rise of the reference clock CK1, the clock CKk as the D input becomes “1” (delay time If it is less than one cycle), the output Gk is locked to "1", and if it is "0", the output Gk is locked to "0".

In the above configuration, assuming that the timing of each clock is as shown in FIG. 13, the output CK1 of the delay circuit 1201 is
In response to the rising edge of the output CK1 of the inverter 1203,
Is less than one cycle (solid line), the determination result of the delayed clock management circuit 1202 is G5
~G7 becomes 1, the optical sensor 1209 to each of the period _{t a} '~t _f
When the light detection signal DETP is input, clocks marked with a circle are selected, that is, during the period of ta _′ , the logic value becomes 1 at k = 1 and k = 6 as shown in FIG. CK2 and CK7 are selected at the same time, and a clock having a waveform with a large duty as shown at the bottom of FIG. 13 is output, but the image control circuit 1210 operates correctly without causing a malfunction.

In the period of t _d , the logical value of k = 4 becomes 1, and CK5 is selected. In the period of t _f , the logical value of k = 1 becomes the same as in the period of t _F in FIG. 15A. It becomes 1, CK7 is selected, and all operate correctly.

Next, when the delay of the rising phase of CK7 is one cycle or more with respect to the rising of CK1 (broken line), G5, G6
Is 1 and G7 is 0, and in each period, the clocks marked with ● in FIG. 13 are selected. That is, in the period of tA _' , the logic value becomes 1 at k = 1 and k = 6 as shown in FIG. 15B, and CK2 and CK7 are selected at the same time, but there is no problem as described above. Further, in the period t D _', k = 1 of logic value becomes 1, CK5 is selected, in other periods,
Each clock is selected and works properly. That is, the clock is managed at the falling phase of the reference clock CK1, and the duty of the clock CK7 having the slowest phase is reduced, so that the falling phase of CK7 is lower than the falling phase of CK1. Even when the delay is one cycle or more, there is no problem that no clock is selected because the delay of the falling phase of CK7 does not fall within one cycle with respect to the rising phase of CK1.

In this embodiment, the phase of the rising edge of each clock is determined by the clock selection circuit, and the phase of the falling edge (although it is inverted because it is inverted in the solid line) is determined by the clock management circuit. Obviously, the same effect can be obtained even if each is reversed.

Further, the clock having the latest phase (in the embodiment,
Explaining the duty selection of CK7), the relative difference between the rising phase difference and the falling phase difference with respect to the phase of the reference clock depends on the operating characteristics and wiring of the elements of the latch circuit and the delay clock management circuit. Should be larger than the variation of the delay time due to the above.

〔The invention's effect〕

As described above, according to the synchronization circuit of the image scanning device according to the present invention, the clock management circuit manages the synchronization target even under all conditions including variations in delay characteristics and changes in delay characteristics due to changes in temperature conditions. In order to make the duty of the clock to be larger or smaller than the duty of the reference clock, fluctuations in the delay characteristics of the delay circuit, fluctuations in the delay characteristics due to fluctuations in the temperature conditions, and fluctuations in the operating characteristics of each component element, etc. It is possible to prevent a malfunction of the image control circuit due to a clock selection error caused, and to always select a clock correctly under all the above conditions.

Also, under all conditions including variations in delay characteristics and changes in delay characteristics due to changes in temperature conditions, a delay circuit for generating a clock whose phase is delayed by one cycle or more from a reference clock, and managing these phases. By having the delay clock management circuit and the clock selection circuit, even if the duty of the clock generated from the delay circuit is not 50%, it is relatively easy to select and output an image clock that does not hinder image scanning. It can be realized by the configuration.

Further, the phase (rising and falling) determined by the delay clock management circuit and the phase (rising and falling) determined by the latch circuit are reversed, and the phase of the most determined phase to be determined by the clock selection circuit is determined. By making the duty of the delayed clock smaller or larger, variations in delay characteristics of the delay circuit, variations in delay characteristics due to variations in temperature conditions, and variations in operation characteristics of the phase determination elements of the latch circuit and the delay clock management circuit are reduced. Under all the conditions included, a correct clock selection operation can always be executed with a simple configuration.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a synchronization circuit of an image scanning apparatus according to the present invention (first embodiment), and FIG. 2 is a block diagram showing a configuration of a clock selection circuit shown in FIG. FIG. 3 is a circuit diagram showing the configuration of the delay clock management circuit shown in FIG. 1, FIG. 4 is a dimming chart showing the operation of the present embodiment, and FIG. 5 is an input waveform of the clock management circuit. FIG. 6 is a table showing logical values of the present embodiment, FIG. 7 is a block diagram showing a configuration of a synchronization circuit of the image scanning apparatus according to the present invention (second embodiment), and FIG. FIG. 9 is a circuit diagram showing the configuration of the clock selection circuit shown in FIG. 7, FIG. 9 is a circuit diagram showing the configuration of the delay clock management circuit shown in FIG. 7, and FIG. 10 is dimming showing the operation of this embodiment. Chart, FIG. 11 is a table showing logical values of the present embodiment, and FIG. 12 is an image scanning apparatus according to the present invention. 13 is a block diagram showing the configuration of the synchronous circuit (third embodiment), FIG. 13 is a circuit diagram showing the configuration of the clock selection circuit shown in FIG. 12, and FIGS. Table showing logical values of an example, FIG. 16 is a perspective view showing a configuration of an optical system in an image scanning device according to the present invention, and FIG. 17 shows an electric control system in the image scanning device according to the present invention. Block diagram, FIG. 18 is a block diagram showing a configuration of a synchronous circuit of a conventional image scanning apparatus, FIGS. 19 and 22 are timing charts showing operations of the conventional synchronous circuit, FIGS. 20, 21 and FIG. 23 is a table showing the logic values of the congestion synchronization circuit. Reference numerals 101,706,1204 ... Latch circuits 102,1205 ... Terminal resistors 103,704,1206 ... Synchronous circuits 104,705,1207 ... Reference clock oscillators 105,701,1201 ... Delay circuits 106,703,1202 ... Delay clock management circuits 107,704, 1208 Clock selection circuit 108,1210 Image control circuit 109,1209 Photosensor 201-207,801-809 AND circuit 208,810 OR circuit 301,901 D-FF 1203 Inverter

Claims (3)

(57) [Claims] A clock generating means for generating a reference clock and a plurality of clocks having the same frequency as the reference clock and sequentially delaying in phase; and determining the duty of the clock having the most delayed phase among the plurality of clocks. Duty changing means for making the duty different from the duty of the reference clock; clock selecting means for selecting at least one clock from among the plurality of clocks by inputting a synchronization signal prior to image scanning; and A clock management means for determining a plurality of clocks and managing a clock delayed by a predetermined amount or more from the reference clock so as not to be selected; and an image scanning clock generator for generating an image scanning clock based on the selected clock. Means for synchronizing the image scanning device, comprising: Road. 2. A clock generating means for generating a reference clock and a plurality of clocks which are equal in frequency to the reference clock and which are sequentially delayed in phase, and wherein the plurality of clocks are inputted by inputting a synchronization signal prior to image scanning. A clock selecting means for selecting at least one clock from the plurality of clocks;
A clock management unit that manages a clock delayed in phase by a period or more so as not to be selected; and an image scanning clock generation unit that generates an image scanning clock based on the selected clock. A synchronizing circuit for an image scanning apparatus, wherein a plurality of clocks including a clock whose phase is delayed by one cycle or more than a clock are generated. 3. A clock generating means for generating a reference clock and a plurality of clocks which are equal in frequency to the reference clock and which are sequentially delayed in phase, wherein the duty of the clock having the most delayed phase among the plurality of clocks is Duty changing means for making the duty different from the duty of the reference clock; clock selecting means for selecting at least one clock from a plurality of clocks passed through the duty changing means by input of a synchronization signal prior to image scanning; A clock management unit that determines a clock and manages a clock delayed by a predetermined amount or more from the reference clock so as not to be selected; and an image scanning clock generation unit that generates an image scanning clock based on the selected clock. Wherein the clock selection means receives the synchronization signal. More,
At least one clock having the closest rising or falling phase is selected from among the plurality of clocks that have passed through the duty changing unit, and the clock management unit determines that the clock selection unit is one of the plurality of clocks. The clock selected by the rising phase is the falling phase, and the clock selected by the clock selecting means is the falling phase so that a clock delayed by a predetermined amount or more from the reference clock is not selected. A synchronization circuit for an image scanning device, wherein the synchronization circuit is managed.