JP3017421B2 - Photovoltaic element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photovoltaic device.
More specifically, by controlling the impurity concentration that determines the conductivity type of the first semiconductor layer or the grain size of the crystal that forms the first semiconductor layer, a partial short circuit occurs in the semiconductor layer during long-term use. Also, the present invention relates to a photovoltaic element in which a significant decrease in characteristics does not occur. In particular, the photovoltaic element of the present invention includes, for example, a solar cell.

[0002]

2. Description of the Related Art In recent years, thin-film solar cells using a silicon-based non-single-crystal semiconductor, which is one of photovoltaic elements, have been compared with solar cells using single-crystal and polycrystalline semiconductors in glass and metal sheets. Widespread use of photovoltaic power generation, which has the advantage of being able to form a large area on a relatively inexpensive substrate such as a thin film, and having a thin film thickness, enabling cost reduction and large area, and providing clean energy. From the viewpoint of attention.

[0003] When a solar cell is used, for example, for supplying power to ordinary households, an output of about 3 kW is required. At this time, if the conversion efficiency of the solar cell is 10%, a solar cell having a large area of 30 m ² is required.

However, in a solar cell made of a silicon-based non-single-crystal semiconductor, the thickness of the semiconductor layer is at most several hundred nm.
And thin. Therefore, in a semiconductor manufacturing process, it is extremely difficult to manufacture a solar cell having no defect due to pinholes or inclusions in the semiconductor layer over such a large area. It is known that the influence of dust during the formation of the semiconductor layer, the formation of pinholes in the semiconductor layer due to scratches and protrusions on the substrate, and the inclusion of conductive dust and other inclusions can cause short-circuiting of the upper and lower electrodes of the semiconductor layer. ing. In particular, when a metal sheet such as stainless steel whose surface is not mirror-polished is used as the substrate, or when the surface of the substrate is made uneven in order to increase the generated current, a short circuit occurs in a large-area solar cell. It was easy.

As a result, the lower electrode and the upper electrode of the solar cell come into direct contact with each other at pinholes in the semiconductor layer, the upper and lower electrodes are connected by conductive dust in the semiconductor layer, and spikes on the substrate are caused. When a short-shaped portion having a low resistance is formed due to the contact of the projections with the upper electrode or the like, the current generated by light flows into the low-resistance portion of the short-circuited portion, and the output voltage or the output current sharply increases. Degradation occurs, and the characteristics rapidly decrease.

Conventionally, the following technique is known as a method for the above-mentioned short circuit. A method of cleaning the inside of a semiconductor forming apparatus so that pinholes and inclusions are not generated in a semiconductor layer, and suppressing generation of dust that causes pinholes and inclusions. U.S. Pat. No. 4,451,970 and U.S. Pat.
No. 70, etc., a method of selectively covering a short-circuit portion with an insulator after forming a semiconductor layer, or increasing the resistance by chemical means. U.S. Pat. No. 4,598,306 discloses that a light-transmitting barrier layer having a higher resistance than an electrode is provided between an electrode and a semiconductor layer to prevent a large short-circuit current from flowing even if there is a short-circuit portion. how to.

[0007] However, the above prior art has the following problems. In the method (1), as described above, it is extremely difficult to make the semiconductor layer having a large area free from defects due to pinholes or inclusions, and there is a limit. In the method of (2), in which the short portion is insulated immediately after the formation of the semiconductor layer, it is impossible to cope with the case where the short portion occurs due to mechanical damage, intrusion of moisture, etc. during a long period of use of the solar cell after removing the short portion. .

For this reason, in a solar cell which is used outdoors for a long period of time, in order to prevent a sharp decrease in characteristics due to the occurrence of a short circuit and to improve long-term reliability, a method of forming a short-circuit portion generated in a manufacturing stage is required. It is necessary to take countermeasures such as to prevent a large short-circuit current from flowing even if a short-circuit occurs during a long-term use period, and to suddenly reduce the characteristics. is there.

[0009] US Patent No. 4,598,306, shown above.
In In, Sn, Cd, Z as a light-transmitting barrier layer having a higher resistance than an electrode provided between an electrode and a semiconductor layer.
Layers of oxides, nitrides, carbides and the like such as n, Sb, Si, Cr, and stainless steel substrates are mentioned.

However, in order to provide such a barrier layer other than the semiconductor layer and the electrode, a forming apparatus for forming a new barrier layer is required, and the problem that the manufacturing process becomes complicated is to be improved. Had become.

[0011] Among these materials, I.P. is widely used in a photovoltaic device using a non-single-crystal silicon semiconductor.
nO _x , SnO _x , ZnO _x , SiC, SiN, SiO
In order to obtain a film that is transparent and has an appropriate resistance range for this purpose, it is necessary to finely adjust impurities, and it is difficult to obtain a barrier layer of the same quality with good reproducibility. Had become. That is, InO _x ,
SnO _x , ZnO _{x, and the} like are generally low resistance films generally used as transparent conductive films, and include SiC, SiN, SiO
Is an extremely high-resistance film that is generally used as an insulating film, so it is an intermediate film between the conductive film and the insulating film provided for the purpose of suppressing the flow of a large short-circuit current when a short-circuit occurs. In order to control the resistance in a wide range, it is necessary to adjust the doping amount of the impurity considerably finely.

Further, for the purpose of increasing the light absorptivity in the semiconductor layer to increase the output current, Ag or A provided on the substrate surface is used.
For the purpose of suppressing the diffusion of the high-reflectance metal layer such as l into the semiconductor layer, forming the unevenness by the crystal structure, increasing the optical path length of the incident light and increasing the output current, In general, a transparent conductive film is formed.

In such a case, the transparent conductive film is made of InO.
_{By using x} , SnO _x , ZnO _x, etc., and controlling these resistances to a higher level, the configuration shown in the aforementioned US Pat. No. 4,598,306 can be obtained. At this time, the optical path length is increased by the crystal structure, and a short circuit is generated. The film forming conditions for forming an appropriate uneven shape so as not to be formed are different from the film forming conditions for controlling the resistance value within an appropriate range, and it is extremely difficult to satisfy both at the same time.

[0014]

SUMMARY OF THE INVENTION According to the present invention, even if a partial short circuit occurs in a semiconductor layer during a long-term use period, the characteristics are not greatly reduced, the long-term reliability is excellent, and the manufacturing process is improved. It is an object of the present invention to provide a photovoltaic element that can be easily achieved without making it complicated.

[0015]

The photovoltaic device of the present invention has at least a conductive substrate / first semiconductor layer having a first conductivity type / substantially intrinsic second semiconductor layer /
A third semiconductor layer / transparent electrode having a conductivity type opposite to the first conductivity type, wherein the first to third semiconductor layers are made of a silicon-based non-single-crystal semiconductor, and light is incident from the transparent electrode side In the photovoltaic element having a structure for performing, the impurity concentration that determines the conductivity type of the first semiconductor layer has a distribution that is lower on the conductive substrate side than on the second semiconductor layer side. This is the gist of 1.

Further, in the photovoltaic element of the present invention, at least the layer constitution is a conductive substrate / a first conductive type having the first conductivity type.
Semiconductor layer / substantially intrinsic second semiconductor layer / third semiconductor layer having a conductivity type opposite to the first conductivity type / the first semiconductor layer
A fourth semiconductor layer having the following conductivity type / a substantially intrinsic fifth semiconductor layer / a sixth semiconductor layer having a conductivity type opposite to the first conductivity type / transparent electrode; The semiconductor layer is made of a silicon-based non-single-crystal semiconductor, and has a structure in which light enters from the transparent electrode side. In the photovoltaic element, the impurity concentration that determines the conductivity type of the first semiconductor layer is the second semiconductor. A second gist is to have a distribution that is lower on the conductive substrate side than on the layer side.

Further, in the photovoltaic element of the present invention, at least the layer configuration is a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second semiconductor layer / the first semiconductor layer. Third semiconductor layer having conductivity type opposite to conductivity type / fourth semiconductor layer having first conductivity type / substantially intrinsic fifth
A semiconductor layer / a sixth semiconductor layer having a conductivity type opposite to the first conductivity type / a seventh semiconductor layer having the first conductivity type / a substantially intrinsic eighth semiconductor layer / the first conductivity type A ninth semiconductor layer / transparent electrode having a conductivity type opposite to the mold type,
The first to ninth semiconductor layers are made of a silicon-based non-single-crystal semiconductor, and in a photovoltaic element having a structure in which light enters from the transparent electrode side, an impurity concentration that determines a conductivity type of the first semiconductor layer. It is a third gist that the distribution has a distribution that is lower on the conductive substrate side than on the second semiconductor layer side.

Still further, in the photovoltaic element of the present invention, at least the layer configuration is a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second semiconductor layer / the first semiconductor layer. A third semiconductor layer / transparent electrode having a conductivity type opposite to the conductivity type described above, wherein the first to third semiconductor layers are made of a silicon-based non-single-crystal semiconductor, and receive light from the transparent electrode side. In a photovoltaic device having a fourth gist, a crystal grain constituting the first semiconductor layer has a distribution in which the grain size is smaller on the conductive substrate side than on the second semiconductor layer side. I do.

Still further, in the photovoltaic device of the present invention, at least the layer configuration is a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second semiconductor layer / the first semiconductor layer. Third semiconductor layer having a conductivity type opposite to the first conductivity type / fourth semiconductor layer having the first conductivity type / substantially intrinsic fifth semiconductor layer / a conductivity opposite to the first conductivity type A sixth semiconductor layer having a mold / transparent electrode, wherein the first to sixth
The semiconductor layer is made of a silicon-based non-single-crystal semiconductor, and in a photovoltaic device having a structure in which light enters from the transparent electrode side, a crystal grain size of the first semiconductor layer is
A fifth gist is that the distribution has a distribution that is smaller on the conductive substrate side than on the second semiconductor layer side.

Still further, in the photovoltaic element of the present invention, at least the layer configuration is a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second semiconductor layer / the first semiconductor layer. Third semiconductor layer having a conductivity type opposite to the first conductivity type / fourth semiconductor layer having the first conductivity type / substantially intrinsic fifth semiconductor layer / a conductivity opposite to the first conductivity type A sixth semiconductor layer having a type / a seventh semiconductor layer having the first conductivity type / a substantially intrinsic eighth semiconductor layer / a ninth semiconductor layer having a conductivity type opposite to the first conductivity type / The first to ninth semiconductor layers are transparent electrodes, and the first to ninth semiconductor layers are made of a silicon-based non-single-crystal semiconductor, and constitute the first semiconductor layer in a photovoltaic element having a structure in which light enters from the transparent electrode side. The crystal grain size is smaller on the conductive substrate side than on the second semiconductor layer side. To have a fence made distribution and sixth gist of the.

[0021]

According to the first to third aspects of the present invention, the impurity concentration that determines the conductivity type of the first semiconductor layer has a distribution that is lower on the conductive substrate side than on the second semiconductor layer side. One semiconductor layer can form a high-resistance region near the interface with the conductive substrate. As a result, it is possible to prevent an excessive short-circuit current from flowing even if there is a partial short-circuit portion in the semiconductor layer without increasing the number of forming devices (semiconductor film-forming chambers). Thus, a photovoltaic element having the same effect as described above can be obtained.

In the invention according to claims 4 to 6, since the grain size of the crystal constituting the first semiconductor layer has a distribution that is smaller on the conductive substrate side than on the second semiconductor layer side, The semiconductor layer can form a high-resistance region near the interface with the conductive substrate. As a result, it is possible to prevent an excessive short-circuit current from flowing even if there is a partial short-circuit portion in the semiconductor layer without increasing the number of forming devices (semiconductor film-forming chambers). Thus, a photovoltaic element having the same effect as described above can be obtained.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a photovoltaic device according to the present invention will be described below with reference to the drawings. (Single-type photovoltaic element) As the single-type photovoltaic element according to claims 1 and 4 of the present invention, there is a schematic sectional view illustrated in FIG.

Referring to FIG. 1, the photovoltaic element of the present invention comprises:
An n (or p) type first semiconductor layer 102 and a substantially intrinsic (i type) second semiconductor layer 10 are formed on a conductive substrate 101.
3, p (or n) type third semiconductor layer 104, transparent electrode 1
05 are stacked in this order, a current collecting electrode 106 is provided on the transparent electrode 105, and incident light 107 is emitted from the transparent electrode 105 side.

The conductive substrate 1 in the first semiconductor layer 102
In the region 108 near the interface on the 01 side, the first semiconductor layer 102
The impurity concentration that determines the conductivity type is lower than that of the second semiconductor layer 103, or the grain size of the crystal forming the first semiconductor layer 102 is smaller than that of the second semiconductor layer 103. .

(Two-Layer Tandem-Type Photovoltaic Element) As the two-layer tandem-type photovoltaic element according to claims 2 and 5 of the present invention, there is a schematic cross-sectional view illustrated in FIG.

In FIG. 2, the photovoltaic element of the present invention
An n (or p) type first semiconductor layer 202 and a substantially intrinsic (i type) second semiconductor layer 20 are formed on a conductive substrate 201.
3, p (or n) third semiconductor layer 204, n (or p) fourth semiconductor layer 209, substantially intrinsic (i-type) fifth semiconductor layer 210, p (or n) type The sixth semiconductor layer 211 and the transparent electrode 205 are stacked in this order. A current collecting electrode 206 is provided on the transparent electrode 205, and incident light 207 is irradiated from the transparent electrode 205 side.

The conductive substrate 2 in the first semiconductor layer 202
In the region 208 near the interface on the 01 side, the first semiconductor layer 202
Is lower than the second semiconductor layer 203 side, or the grain size of the crystal forming the first semiconductor layer 202 is smaller than the second semiconductor layer 203 side. .

(Three-Layer Tandem-Type Photovoltaic Element) As a three-layer tandem-type photovoltaic element according to claims 3 and 6 of the present invention, there is a schematic cross-sectional view illustrated in FIG.

Referring to FIG. 3, the photovoltaic element of the present invention comprises:
An n (or p) type first semiconductor layer 302 and a substantially intrinsic (i type) second semiconductor layer 30 are formed on a conductive substrate 301.
3, p (or n) third semiconductor layer 304, n (or p) fourth semiconductor layer 309, substantially intrinsic (i-type) fifth semiconductor layer 310, p (or n) type Sixth semiconductor layer 311, n (or p) type fourth semiconductor layer 312, substantially intrinsic (i-type) fifth semiconductor layer 313, p (or n) type sixth semiconductor layer 314, transparent Electrodes 305 are stacked in this order, and a collecting electrode 306 is provided on the transparent electrode 305.
Is provided, and the incident light 307 is irradiated from the transparent electrode 305 side.

The conductive substrate 3 in the first semiconductor layer 302
In the region 308 near the interface on the 01 side, the first semiconductor layer 302
Is lower than that of the second semiconductor layer 303, or the grain size of the crystal forming the first semiconductor layer 302 is smaller than that of the second semiconductor layer 303. .

In the following, the process of inventing the structure of the photovoltaic element described above will be described in detail.

Conventionally, to change the impurity concentration of the impurity-doped layer or to change the crystal grain size, it is necessary to increase the impurity concentration at the electrode interface side.
Japanese Patent Application Laid-Open No. 63-258078 discloses that the crystal grain size is reduced in the interface region of the i-type semiconductor layer, but the distribution shape is completely opposite to that of the present invention. If it is provided, it is considered that the region near the interface of the impurity-doped layer on the conductive substrate side has a high impurity concentration or high crystallinity and therefore has a lower resistance than other regions of the layer. However, the purpose of the present invention to increase the resistance of the region near the interface on the conductive substrate side of the impurity-doped layer closest to the conductive substrate cannot be achieved. In addition, it affects the basic semiconductor junction (p / i junction, i / n junction, etc.) of the photovoltaic element.

The present invention has been completed by further studies based on the following findings obtained as a result of the experiments by the inventors.

(1) The inventor of the present invention provided a semiconductor layer between a conductive substrate 401 and a semiconductor layer 402 on the opposite side of light incidence of a nip (or pin) structure photovoltaic element made of non-single-crystal silicon. Conductive semiconductor layer 41 having a polarity opposite to that of 402
5 into which a photovoltaic element having a pnip (or npin) structure shown in FIG. 4 is manufactured. The voltage-current characteristics of the reverse junction between the single elements of the tandem-type stacked element are determined by the reverse junction. It has been investigated how it changes depending on the characteristics of the impurity-doped layer to be formed. Further, a so-called roll-to-roll type manufacturing apparatus shown in FIG. 5 was used for manufacturing the semiconductor layer of the photovoltaic element.

In FIG. 5, 504, 501, 502,
Reference numeral 503 denotes p, n, i, p by a high-frequency plasma CVD method.
(Or n, p, i, n) type film forming chambers 505 and 506
Denotes a supply chamber and a take-up chamber for a strip-shaped conductive substrate. The vacuum chambers of the respective film forming chambers are connected by a gas gate 507 for preventing a gas from intermixing between the film forming chambers by flowing a purge gas such as hydrogen into a narrow gap. Reference numeral 508 denotes a conductive strip-like substrate such as a stainless sheet having a thickness of 0.13 mm and a width of 36 cm, which is unwound from the supply chamber 505 and is continuously transported.
01, 502, and 503, and while being wound into the winding chamber 506, four layers of pnip (or np)
A semiconductor laminated film of non-single-crystal silicon for a photovoltaic element having an in) structure is formed.

Reference numeral 509 denotes a belt-like sheet made of a heat-resistant nonwoven fabric, which is wound when the belt-like substrate is wound, thereby preventing the surface of the belt-like substrate from being damaged.

In each of the film forming chambers 504, 501, 502 and 503, a heater 510 for heating the substrate to a predetermined temperature is provided.
A source gas introduction pipe 511 for introducing a source gas for semiconductor formation from each gas supply unit (not shown) into each deposition chamber, an exhaust pipe 512 for exhausting the deposition chamber to a predetermined pressure by an exhaust means (not shown), A discharge electrode 513 for generating glow discharge is provided between the substrate and the grounded substrate by supplying high-frequency power from the illustrated high-frequency power supply to the gas in the film formation chamber.
At 501, 502, and 503, p, n, i,
A p (or n, p, i, n) type silicon non-single-crystal semiconductor layer is deposited by a plasma CVD method.

The inventor of the present invention used the semiconductor film manufacturing apparatus having the above structure shown in FIG. 5 to obtain the highest level of surface quality among stainless steel sheets which can be generally obtained in large quantities without special mirror polishing. Thickness 0.13mm, width 3 with smoothness
A non-single-crystal silicon laminated film having a pnip structure is deposited on a substrate made of a cold-rolled stainless steel strip (SUS430BA) having a 6 cm bright heat treatment finish, and an ITO transparent electrode having a thickness of 70 nm is formed thereon using a known vacuum deposition apparatus. Laminated,
Further, a silver paste is screen-printed thereon to a width of 0.1 mm.
A current collecting electrode having a size of 5 mm and a pitch of 3 mm was formed, and a photovoltaic element was manufactured.

The size of one photovoltaic element is 30 cm ×
30 cm, one turn of about 50 m from a strip-shaped substrate at a time
Zero photovoltaic elements (sample 1) were produced.

At this time, the p-type semiconductor layer closest to the conductive substrate has a resistivity of 1 × 10 ⁴ Ωcm and a layer thickness of 15 nm.
The resistivity of the n-type semiconductor layer thereon was 1 Ωcm, and the film thickness was 20 nm. The thickness of the i-type semiconductor layer is 3
The thickness of the p-type semiconductor layer on the light incident side was 10 nm.

As a comparative sample, the semiconductor film manufacturing apparatus shown in FIG. 5 was used, and 100 ni were formed in exactly the same manner except that the fourth semiconductor layer was not formed in the film forming chamber 504.
A photovoltaic device (sample 2) made of p-type non-single-crystal silicon was manufactured.

The present inventor has found the following results by comparing the characteristics of the photovoltaic elements of Sample 1 and Sample 2.

Without post-processing for increasing the resistance of the short-circuited portion, the simulated sunlight of the air mass (AM1.5, 100 mW / cm ² ) was passed through an ND filter having a transmittance of 1% under low illuminance light (AM1. 5, 1 mW / cm ² )
The open-circuit voltage of 100 photovoltaic elements (sample 2) having a nip structure of cm × 30 cm was measured. 1cm x 1c with no pinholes or shorts due to defects
The open-circuit voltage of sample 2 was significantly reduced on average to about 1/8 of the open-circuit voltage under low illuminance obtained by the photovoltaic element having the same nip structure as m (sample 3).

The voltage-current characteristics of the fabricated 30 cm × 30 cm nip structure photovoltaic device (sample 2) in a dark state were examined by a curve tracer. As a result, the voltage-current curve was immediately separated from the voltage axis near 0 V. It was found that a partial short-circuit occurred in the element. It has been found that the open-circuit voltage is greatly reduced because the generated current flows into the short-circuited portion that is partially generated, and the effect is particularly significant when the irradiation light amount is small and the generated current is small.

On the other hand, the prepared pn of 30 cm × 30 cm
The open-circuit voltage under low illuminance light (AM1.5, 1 mW / cm ² ) of 100 photovoltaic elements (sample 1) having an ip structure was measured. Compared with the open voltage under low illuminance of a 1 cm × 1 cm nip structure photovoltaic element (sample 3) having no pinholes or shorts due to defects, the open voltage of sample 1 is about 3/4 on average. It was found that the voltage drop was reduced.

(2) Regarding the phenomenon (1), the inventor of the present invention has found that, in Sample 1, the total thickness of the semiconductor film is increased by further laminating a p-type semiconductor layer, and the underlying substrate is more completely covered. I thought that the number of shorts had been reduced. In order to verify this idea, the thickness of the underlying n-type semiconductor layer or i-type semiconductor layer was made the same except that the thickness of the p-type semiconductor layer provided last in Sample 1 was increased by 15 nm. Thus, 100 photovoltaic devices (samples 4 and 5) each made of non-single-crystal silicon having a nip structure were manufactured.

Under low illuminance light (AM 1.5, 1 mW / c
m ² ), the open-circuit voltage of 100 photovoltaic elements (samples 4, 5) having a nip structure of 30 cm × 30 cm were measured.

However, compared to the open voltage under low illuminance of the 1 cm × 1 cm nip structure photovoltaic element (sample 3), which has no pinholes or shorts due to defects, which were prepared separately, the sample 4 and the sample 5 had a lower voltage. The open circuit voltage is about 1 each
/ 8.

From the above experimental results, the fact that the adverse effect due to the partial short-circuit portion was suppressed in the photovoltaic element having the pnip structure manufactured by the present inventors is not merely because the thickness of the semiconductor layer is increased. There was found.

Further, the conditions such as the apparatus for manufacturing the semiconductor layer and the substrate used were not changed at all, and it was clear that these were not the causes.

(3) Further, the present inventor considers that the above-mentioned (1) may be caused by the fact that the semiconductor layer on the conductive substrate side is of p-type conductivity, and n is changed without changing the film thickness of each layer. , I, p
The stacking order of the type semiconductor layers is reversed from nip to pin to 3
100 photovoltaic elements (sample 6) having a pin structure of 0 cm × 30 cm were manufactured. However, the open-circuit voltage of the sample 6 under the low illuminance was 1/8 of the open-circuit voltage of the sample 3 on average.
Had fallen. From this result, it was found that the cause was not that the semiconductor layer on the conductive substrate side was of p-type conductivity.

(4) Therefore, the inventor of the present invention has proposed that the resistance (ρ = 1 × 10 ⁴ Ωcm) of the semiconductor layer in contact with the conductive substrate is reduced by the resistance (ρ = 6 × 10 ⁻⁵ Ωcm) of the conductive substrate. Considering that the reason is that the resistance is much higher than the resistance (ρ = 1Ωcm) of the n-type semiconductor layer, the manufacturing conditions of the semiconductor layer in contact with the conductive substrate were changed, and the impurity concentration was increased without changing the film thickness. By increasing the crystal grain size and setting the resistivity of the p-type semiconductor layer to the same resistance value (ρ = 1Ωcm) as that of the n-type semiconductor layer thereon, 100 photovoltaic elements (30 cm × 30 cm) having a pnip structure of 30 cm × 30 cm ( Sample 7) was produced.

However, the open-circuit voltage of sample 7 is lower than the open-circuit voltage under low illuminance of a 1 cm × 1 cm nip structure photovoltaic element (sample 3) having no pinholes or shorts due to defects. The average was reduced to about 1/8.

From this experimental result, it is found that the resistance (ρ = 1 × 10 ⁴ Ωcm) of the semiconductor layer in contact with the conductive substrate is equal to the resistance (ρ = 6 × 10 ⁻⁵ Ωcm) of the conductive substrate and the n-type layer thereon. The fact that the resistance was much higher than the resistance of the semiconductor layer (ρ = 1 Ωcm) is the reason that the influence of the partial short-circuited portion was suppressed in the pnip structure photovoltaic element manufactured by the present inventors. Do you get it.

That is, by providing a high-resistance layer between the nip structure photovoltaic element and the conductive substrate within a range where the series resistance of the photovoltaic element does not increase, the characteristics of the photovoltaic element can be improved. It is considered that a large short-circuit current could be suppressed from flowing in a partially short-circuited portion without lowering the current.

(5) The inventor of the present invention uses a roll-to-roll type film forming apparatus as shown in FIG. 5 on a SUS430BA substrate to form a nip having a total semiconductor film thickness of about 200 to 400 nm.
When a photovoltaic element having a structure was formed and observed with an electron microscope, a short-circuited portion penetrating the semiconductor layer was found to be 10c.
An average of about 1 spot was generated per 100 cm ^{2 of} mx 10 cm, and it was confirmed that the effective diameter was about 5 µm on average. Therefore, 30 cm × 30 cm = 900
In a device having a relatively large area of about ² cm ² , if a short portion is left as it is, a large current flows into about 9 short portions on average, and it is considered that the characteristics of the photovoltaic device have been significantly reduced. .

However, in the photovoltaic device according to the present invention, the portion in contact with the conductive substrate has a resistivity of 1 × 10 ⁴ Ωcm and a layer thickness of 1 × 10 ⁴ Ωcm.
The uniform stacking of the high-resistance semiconductor layers of 5 nm produces a resistance of 7.5 kΩ per short-circuited portion, and the current flowing through the short-circuited portion is considerably suppressed. It is also explained that the characteristics of the photovoltaic element of 30 cm × 30 cm hardly deteriorated.

(6) When the resistivity of the semiconductor layer in contact with the conductive substrate is ρ = 1 × 10 ⁴ Ωcm and the layer thickness is 15 nm, if the pn interface is in a sufficiently ohmic junction, the layer is inserted. Increase of series resistance is 0.015Ω
cm ² , which is almost negligible compared to the series resistance of the photovoltaic element which is several to several tens Ωcm ² .

According to the circumstances described in the above (1) to (6), the present inventor has set the photovoltaic element closest to the substrate side of the photovoltaic element at a position in contact with the conductive substrate on the side opposite to the light incidence. By providing a semiconductor layer having a conductivity type opposite to that of the impurity-doped layer and having a higher resistance than the impurity-doped layer closest to the substrate of the conductive substrate and the photovoltaic element, even if there is a partial short-circuited portion, it is large. It has been found that short-circuit current can be suppressed.

In this method, as compared with the conventional method, since the same semiconductor material as the semiconductor film of the photovoltaic element body is used as the resistance layer, the resistivity can be easily controlled by the doping concentration of impurities and the crystallinity. Further, it is excellent in that the semiconductor film of the photovoltaic element body can be uniformly coated with an extremely thin film thickness of 20 nm or less without using a transparent material to increase the film thickness. .

However, since it is necessary to form a semiconductor layer of a conductivity type opposite to that of the impurity-doped layer closest to the substrate side of the photovoltaic element main body, a dedicated film is formed for each of the n, i, and p-type semiconductor layers. In a so-called three-chamber separation type film forming apparatus in which a chamber is provided and a substrate is sequentially transported, in order to produce an element having such a configuration without reversely feeding the substrate, the n, i, and p type semiconductor layer film forming chamber is required. In addition, it was necessary to add another film formation chamber for the p-type semiconductor layer.

Also in the roll-to-roll type film forming apparatus, since the impurity conductivity type is different between the impurity-doped layer closest to the substrate side of the photovoltaic element main body and the high-resistance semiconductor layer therebelow, the gas gate must be formed. It is necessary to add another film forming chamber through the intermediary, and make the apparatus configuration as shown in FIG. Therefore, the problem that the forming apparatus is required to form a new layer, which is a problem to be solved by the conventional technology, and the manufacturing process is complicated has not been solved by this method.

(7) The present invention has been found by the inventor of the present invention through further studies in order to solve the problem described in the above (6).

That is, when forming the impurity-doped layer closest to the substrate side of the photovoltaic element body, the impurity concentration is reduced in the region near the conductive substrate interface as compared with the other regions of the layer. By lowering the crystallinity as compared with other regions, a high-resistance region is formed near the interface with the conductive substrate.

As described above, by changing the resistance of the semiconductor in one impurity-doped layer and providing the high-resistance region in the region in contact with the conductive substrate, the photovoltaic device of the present invention can It is possible to suppress a large short-circuit current from flowing even if there is a partial short-circuit portion in the semiconductor layer without increasing the number of (semiconductor film-forming chambers).

Hereinafter, the “conditions for forming the impurity-doped layer closest to the substrate of the photovoltaic element body” according to the present invention will be described in more detail.

In the photovoltaic device of the present invention, the thickness d (nm) of the region in contact with the conductive substrate interface in the impurity-doped layer closest to the conductive substrate is preferably in the range of 2 <d <200. .

In the photovoltaic device of the present invention, the thickness d (nm) of the region in contact with the interface on the conductive substrate side in the impurity-doped layer closest to the conductive substrate is such that a layer that does not generate photocurrent and is not transparent is formed. There is a suitable range from the condition that the generated current is prevented from lowering due to the lowering of the substrate reflected light due to the provision, and the high resistance region is uniformly covered over the entire element region. That is, it is difficult to uniformly cover the high resistance region over the entire element region at a thickness of 2 nm or less, and at a thickness of 200 nm or more, the thickness of the region is substantially equal to that of the intrinsic semiconductor layer. Became
Light reflected from the substrate is reduced, and the output current of the element is greatly reduced.

In the photovoltaic device of the present invention, the resistivity ρ (Ωcm) of the region in contact with the interface on the conductive substrate side in the impurity-doped layer closest to the conductive substrate is 10 ² <ρ.
It is preferably in the range of <10 ⁵ .

In the photovoltaic device of the present invention, the resistivity ρ (Ωcm) of the region in contact with the conductive substrate is within the range of the thickness d (nm) of the aforementioned region, and the short-circuit portion of the photovoltaic device is partially short-circuited. It has a resistance value sufficient to suppress the flow of a large short-circuit current even if there is, and the condition that the series resistance of the photovoltaic element does not greatly increase due to the resistance in the film thickness direction of the region is preferable. Range exists.

The inventor of the present invention used a cold-rolled stainless steel strip (SUS430BA), which has the highest level of surface properties among the commonly available bright-finished heat-treated finishes, as a substrate, and used a silicon-based non-rolling device in a roll-to-roll apparatus. When a photovoltaic element made of a single crystal semiconductor is formed, a short-circuit portion penetrating the semiconductor layer is generated at an average of one place per 10 cm × 10 cm = 100 cm ² and at a maximum of 100 places, and its effective diameter is 5 μm on average. there were. Under such conditions, by setting the resistivity ρ (Ωcm) of the region to be in the range of ρ> 10 ² , even if the high-resistance region has a minimum thickness of 2 nm in a preferable range, the light resistance can be reduced. Electromotive element 1cm ²
The resistance at the short-circuit point could be set to 1 × 10 ³ Ω or more, which is the boundary level at which the element characteristics sharply decrease.

By setting the resistivity ρ (Ωcm) of the high-resistance region in contact with the conductive substrate in the range of ρ <10 ⁵ , the film thickness of the region is 200 nm, which is the upper limit of the preferred range. Also, the increase in the series resistance of the photovoltaic element due to the region could be reduced to ² Ωcm ² or less at which the element characteristics began to deteriorate.

In the photovoltaic device of the present invention, when the impurity concentration which determines the conductivity type of the impurity-doped layer in contact with the conductive substrate has a distribution in which the impurity concentration determining the conductive substrate interface side becomes lower, the impurity concentration distribution shape FIG. 6 (A)
To (C). If the impurity concentration is controlled to a lower and constant range in the region near the interface on the conductive substrate side and the above-mentioned conditions of ρ and d are satisfied, the impurity concentration can take various distribution shapes.

In order to obtain such an impurity concentration distribution in the film thickness direction, a means such as changing the supply ratio of the silicon element and the impurity element during the deposition of the impurity doped layer is used.

The valence electron control of a silicon-based non-single-crystal semiconductor
Impurities used for this purpose have p-type conductivity.
As an element to be given, an element of Group 3B of the periodic table, for example,
B, Al, Ga, In, Tl, etc .;
Examples of the element that gives a pattern include an element of Group 5B of the periodic table,
For example, N, P, As, Sb, Bi, etc. can be fisted. Especially
In particular, B, Ga, P, Sb and the like are preferable. Such a failure
As a raw material for introducing a pure element, for example, silicon
When a non-single-crystal semiconductor is formed by a plasma CVD method,
In a gaseous state at normal temperature and normal pressure, or at least under film forming conditions
What can be easily gasified is adopted. Such impure
As a substance for introducing substances, specifically, PH _Three, P
_TwoH_Four, PF_Three, PCl_Three, AsH_Three, AsF_Three, AsF_Five,
AsCl_Three, SbH_Three, SbF_Five, BiH_Three, BF_Three, BC
l_Three, BBr_Three, B_TwoH₆, B_FourH_Four, B_FiveH₉, B_FiveH₁₁, B₆
H_Ten, B₆H₁₂, AlCl_Three, B (CH_Three)_Three, Al (CH
_Three)_Three, Ga (CH_Three)_Three, As (CH_Three)_ThreeTo list
Can be. One compound containing the above impurity element is used.
Or two or more thereof may be used in combination.

In the photovoltaic element of the present invention, when the impurity-doped layer in contact with the conductive substrate has a distribution in which the silicon has a distribution in which the crystal grain size becomes smaller on the conductive substrate interface side, the distribution of the crystal grain size is reduced. As the shape, FIG.
The shape as shown in (C) can be mentioned.

Incidentally, the crystal grain size in the present invention means the cross-sectional T
The size of a silicon crystal particle observed by an EM (transmission electron microscope) is represented by the diameter of a sphere having the volume of the crystal particle. When the crystal grains have a columnar shape having a height in the film thickness direction, the crystal grain size at a certain position in the film thickness direction is defined by the diameter of a circle having a cross-sectional area at this position of the columnar crystal.

The term “non-single-crystal silicon” as used in the present invention refers to silicon from a polycrystal to a completely amorphous structure, but contains almost no microcrystalline phase and has an average crystal grain size of about 2
In comparison with the so-called narrowly-defined amorphous having a diameter of not more than nm, the average of the crystal grain diameters containing more microcrystalline phases and less amorphous phases is about 2
A so-called microcrystal of nm or more has a resistivity of 3-4.
It is known to drop by an order of magnitude. Therefore, by reducing the crystal grain size of the non-single-crystal silicon near the interface with the conductive substrate, the resistance in the region near the interface with the conductive substrate can be increased.

In order to obtain such a distribution of the crystal grain size in the film thickness direction, when forming the impurity-doped layer, for example, when depositing by the plasma CVD method, the discharge power, the hydrogen dilution ratio, the deposition temperature, etc. Means for changing the conditions affecting the crystallinity of the deposited film are used. Plasma CVD
In the method, as a method of increasing the crystal grain size of non-single-crystal silicon, a method of increasing discharge power with respect to a source gas flow rate, increasing a hydrogen dilution rate with respect to a source gas, and the like, are known. By reducing the discharge power or reducing the hydrogen dilution rate in the vicinity, the crystal grain size in the region can be reduced.

The reduction of the crystal grain size in the region near the interface of the impurity-doped layer on the conductive substrate side and the reduction of the impurity concentration in the region may be performed alone or in combination. On the conductive substrate interface side of the impurity doped layer,
The crystal grain size and the impurity concentration may have a distribution in which the impurity concentration is reduced at the same time. In this case, the distribution shape of the crystal grain size and the distribution shape of the impurity concentration need not be the same. The distribution may be a step shape in which the distribution changes abruptly in the middle, and a slope shape in which the distribution of the impurity concentration changes continuously.

Further, when non-single-crystal silicon contains P as an impurity element, the crystal grain size tends to be large, and B
Is known to tend to reduce the crystal grain size. Therefore, B as an impurity element
When the impurity concentration of the impurity-doped layer in the region near the conductive substrate interface is reduced by using the method described above, depending on the conditions, the crystal grain size increases rapidly due to the decrease in the B content concentration, and the resistance becomes low contrary to the intention. There is a risk. In order to avoid this, avoid the film formation conditions that rapidly change from the so-called narrowly-defined amorphous state to the so-called micro-crystal state, and set the film formation conditions so that the crystal structure does not change rapidly due to the decrease in the B content concentration. There is a need to.

Hereinafter, embodiments of the present invention will be described. (Conductive Substrate) As a material constituting the conductive substrate of the photovoltaic device according to the present invention, a material having little deformation and distortion and a desired strength at a temperature required for producing a semiconductor layer is preferable. Specifically, metal thin plates and composites thereof such as stainless steel, aluminum and alloys thereof, iron and alloys thereof, copper and alloys thereof, and metal thin films of different materials on their surfaces, or SiO ₂ , Si ₃ N ₂ , Al ₂
Insulating thin films such as O ₃ and AlN ₃ that have been subjected to surface coating by sputtering, vapor deposition, plating, etc. In addition, polyimide, polyamide, polyethylene terephthalate, heat-resistant resin sheets such as epoxy, or a glass fiber, carbon fiber, boron fiber, a metal simple substance or alloy on the surface of a composite with such a metal fiber,
And those obtained by subjecting a transparent conductive oxide (TCO) or the like to a conductive treatment by plating, vapor deposition, sputtering, coating, or the like.

The surface property of the conductive strip-shaped substrate may be a so-called smooth surface or a fine uneven surface. In the case where the surface is minutely uneven, the surface is spherical, conical, pyramidal, or the like, and its maximum height (R _max ) is preferably 50 nm to 500 nm. Which causes an increase in the optical path length of the reflected light on the surface.

(Electrode) In the photovoltaic element according to the present invention, an appropriate electrode is selectively used depending on the configuration of the device. Examples of such electrodes include a lower electrode, an upper electrode (transparent electrode), and a collecting electrode (however, the upper electrode referred to here is an electrode provided on the light incident side, and the lower electrode is referred to as a lower electrode). It refers to the one provided facing the upper electrode with the semiconductor layer interposed).

The constituent materials of the lower electrode preferably used in the present invention include Ag, Au, Pt, Ni, Cr, Al,
Metals such as Ti, Zn, Mo and W or alloys thereof are exemplified. The lower electrode can be formed by a film forming means such as vacuum evaporation, electron beam evaporation, and sputtering using these metals. At this time, the metal thin film formed must be considered so as not to become a resistance component with respect to the output, and the sheet resistance is preferably 50Ω or less, more preferably 10Ω or less.
It is desirable that it be Ω or less.

A buffer layer may be provided between the lower electrode and the n-type semiconductor layer (or p-type semiconductor layer) for preventing short circuit of ZnO or the like and diffusion of electrode metal. The effect of the buffer layer is not only to prevent the metal element forming the lower electrode from diffusing into the n-type semiconductor layer (or p-type semiconductor layer), but also to provide the semiconductor layer with a slight resistance value. To prevent short-circuiting caused by a defect such as a pinhole between a lower electrode and an upper (transparent) electrode provided therebetween, and to confine incident light which causes multiple interference by a thin film in a solar cell. The effect can be obtained.

As the material preferably used as the constituent material of the buffer layer, magnesium fluoride-based material, indium, tin, cadmium, zinc, antimony, silicon, chromium, silver, copper, aluminum oxide, nitride and Materials selected from carbides and mixtures thereof can be given. In particular, magnesium fluoride and zinc oxide are preferable because they can be easily formed and have an appropriate resistance value and light transmittance as a buffer layer.

The transparent electrode used in the present invention desirably has a light transmittance of 70% or more, and preferably 80% or more in order to efficiently absorb light from the sun, a white fluorescent lamp, or the like into the semiconductor layer. Is more desirable. Materials having such characteristics include SnO ₂ , In ₂ O ₃ ,
ZnO, CdO, Cd ₂ SnO ₄ , ITO (In ₂ O ₃ + S
Metal oxides such as nO ₂ ) and metal thin films formed by forming a metal such as Au, Al, and Cu in a very thin and translucent state. The transparent electrode is stacked on the p-type semiconductor layer (or n-type semiconductor layer). As a manufacturing method thereof, a resistance heating evaporation method, a sputtering method, a spray method, or the like can be used, and it is appropriately selected as desired.

In the present invention, a current collecting electrode may be provided on the transparent electrode for the purpose of reducing the sheet resistance of the transparent electrode. When forming the transparent electrode after the formation of the semiconductor layer, the substrate temperature during the formation of the transparent electrode can not be too high, the sheet resistance value of the transparent electrode must be relatively high, It is preferable to form the current collecting electrode.

The constituent materials of the current collecting electrode suitably used in the present invention include Ag, Cr, Ni, Al, Au, Ti,
A simple substance of a metal such as Pt, Cu, Mo, W or the like, an alloy thereof, or carbon may be used. Advantages of these metals or carbon (low resistance, low diffusion into semiconductor layer, robustness, easy electrode formation by printing, etc.)
Can be used in combination. Further, the shape of the semiconductor layer is uniformly spread over the light receiving surface of the solar cell, and the area thereof is preferably 15% or less, more preferably the light receiving area, so that the amount of incident light on the semiconductor layer is sufficiently secured. 1
Desirably, it is 0% or less. Further, the sheet resistance value is preferably 50Ω or less, more preferably 10Ω.
It is desirable that

(Semiconductor Layer) In the semiconductor layer of the photovoltaic element according to the present invention, the semiconductor material suitably used for forming the substantially intrinsic semiconductor layer is, for example, aS
i: H, a-Si: F, a-Si: H: F, a-Si
C: H, a-SiC: F, a-SiC: H: F, a-S
iGe: H, a-SiGe: F, a-SiGe: H:
F, polycrystalline Si: H, polycrystalline Si: F, polycrystalline S
A silicon-based non-single-crystal semiconductor material such as i: H: F may be used. Further, the semiconductor layer only needs to be substantially intrinsic and may contain a small amount of impurities.

The semiconductor material constituting the p-type or n-type semiconductor layer suitably used in the present invention is the same as that of the aforementioned i.
Can be obtained by doping the semiconductor material forming the p-type semiconductor layer with an impurity for controlling valence electrons. The use of light is better when the semiconductor material forming the p-type or n-type semiconductor layer contains a crystal layer. It is preferable because the ratio and the carrier density can be increased.

As means for forming each semiconductor layer used in the solar cell of the present invention, microwave plasma CVD,
RF plasma CVD, ion plating, sputtering and reactive sputtering, optical CVD
There can be mentioned film forming means capable of realizing a method for forming a semiconductor deposited film, such as a CVD method, a thermal CVD method, a MOCVD method, and an MBE method, and these are appropriately selected and used.

(Apparatus and method for manufacturing photovoltaic element)
In manufacturing the photovoltaic element according to the present invention, various manufacturing apparatuses and manufacturing methods can be used, but when manufacturing the single-structured photovoltaic element illustrated in FIG. For example, it can be manufactured using a manufacturing apparatus having a configuration schematically shown in FIG. The manufacturing apparatus shown in FIG. 8 is different from the manufacturing apparatus shown in FIG. 5 in that the number of film forming chambers is reduced by one, and reference numerals 801 to 813 in FIG.
To 513.

In the present invention, a high-resistance region is formed near the interface of the conductive substrate by changing the impurity concentration or the crystal grain size in the impurity-doped layer on the side of the conductive substrate opposite to the most incident light. Therefore, it is not necessary to newly add a film formation chamber for forming a high-resistance layer (region), and a manufacturing apparatus and a manufacturing process do not become complicated.

In FIG. 8, reference numerals 801, 802 and 803 denote n, i, p (or p,
The i, n) type film forming chambers 805 and 806 are a supply chamber and a winding chamber for a strip-shaped conductive substrate. The vacuum chambers of the respective film forming chambers are provided with a gas gate 807 for flowing a purge gas such as hydrogen through a narrow gap to prevent the gas from being mixed between the film forming chambers.
Connected by 808 is, for example, 0.13 m thick
m, a conductive strip-shaped substrate such as a stainless steel sheet having a width of 36 cm. While being wound around 806, a three-layered non-single-crystal silicon semiconductor laminated film for a photovoltaic element having a nip (or pin) structure is formed on the surface thereof.

Reference numeral 809 denotes a band-shaped sheet made of a heat-resistant nonwoven fabric, which is wound simultaneously with the winding of the band-shaped substrate to prevent the surface of the band-shaped substrate from being damaged.

A heater 810 for heating the substrate to a predetermined temperature is provided in each of the film forming chambers 801, 802, and 803, and a source gas for introducing a source gas for forming a semiconductor into each film forming chamber from a gas supply means (not shown). Introducing pipe 811, exhaust pipe 81 for exhausting the film forming chamber by an exhaust means (not shown) and adjusting the pressure to a predetermined pressure.
2. Discharge electrodes 813 are provided to supply high-frequency power from a high-frequency power supply (not shown) to a gas in the film formation chamber to generate glow discharge between the substrate and a grounded substrate.
2, 803, respectively, n, i, p (or p, i,
An n) type silicon non-single-crystal semiconductor layer is deposited by a plasma CVD method.

The film-forming chamber 801 of the impurity-doped layer closest to the conductive substrate has two discharge regions, each having a separate source gas introduction pipe 811 and a discharge electrode 813, and has two film-forming conditions. Can change the impurity concentration or the crystal grain size in the layer thickness direction in the layer.

The manufacturing apparatus shown in FIG. 9 is different from the above-mentioned manufacturing apparatus shown in FIG. 8 in that the discharge power in the substantially intrinsic semiconductor layer deposition chamber is changed from a high frequency to a microwave. The photovoltaic device of the present invention can be manufactured.

901 to 913 in FIG. 9 correspond to 801 to 8 in FIG.
13 is supported. In FIG. 9, reference numeral 914 denotes a waveguide for guiding microwave power from a microwave power supply (not shown) to the film formation chamber 902, and 915 denotes a microwave introduction window made of a dielectric for introducing microwave power to the film formation chamber 902. It is.
In the apparatus shown in FIG. 9, a substantially intrinsic semiconductor layer requiring a relatively large film thickness can be formed by a microwave plasma CVD method with a high film formation rate. 8 can be reduced in comparison with the apparatus of FIG.

The photovoltaic element of the present invention having a two-layer tandem structure shown in FIG. 2 can be manufactured by using, for example, a manufacturing apparatus having a structure schematically shown in FIG. The manufacturing apparatus shown in FIG. 10 is similar to the manufacturing apparatus shown in FIG.
(Or p, i, n) type semiconductor layer deposition chambers A and B
The two-layer tandem-type photovoltaic element having a nipnip (or pinpin) structure can be manufactured by using the pair. 1001 to 1008 in FIG.
8 is supported.

In the film formation chamber 1001A for the impurity-doped layer closest to the conductive substrate, two discharge regions with different conditions are provided, and a semiconductor layer having characteristics changed in the film thickness direction can be formed.

Further, the photovoltaic element of the present invention having a three-layer tandem configuration shown in FIG. 3 can be manufactured using, for example, a manufacturing apparatus having a configuration schematically shown in FIG. FIG.
1 is the same as the manufacturing apparatus shown in FIG.
The film forming chamber for the i, p (or p, i, n) type semiconductor layer is A,
A three-layer tandem-type photovoltaic element having a nipnipnip (or pinpinpin) structure can be manufactured using three sets of B and C. 1101 to 110 in FIG.
8 corresponds to 801 to 808 in FIG.

In the film formation chamber 1101A for the impurity-doped layer closest to the conductive substrate, two discharge regions with different conditions are provided, and a semiconductor layer having characteristics changed in the film thickness direction can be formed.

[0107]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the photovoltaic device of the present invention will be described below. (Example 1) In this example, the manufacturing apparatus shown in FIG.
A nip structure photovoltaic element made of amorphous silicon was continuously manufactured on a conductive substrate. Note that the impurity-doped layer on the most conductive substrate side is formed in two film formation regions so that the impurity gas concentration in the source gas is lower than that of the intrinsic semiconductor layer interface on the conductive substrate interface. The concentration of P (phosphorus), which is an impurity element of the n-type amorphous silicon layer formed in the film formation chamber 803, is distributed lower on the transparent electrode side. The manufacturing conditions are shown in Table 1.

[0108]

[Table 1]

In the following, each step will be described in accordance with the manufacturing procedure. (1) Strip-shaped stainless steel plate made of SUS430BA (width 36 cm x length 50 m x thickness 0.13 mm) 808
Is set in the supply chamber 805 in a state of being wound around a bobbin in a coil shape, and the band-shaped substrate is passed through the film forming chambers 801 to 803 through the respective gas gates 807 and is passed to the band-shaped substrate winding chamber 806 without loosening. Tensioned to a degree. In addition,
The winding chamber 806 has a sufficiently dried aramid protective film (36 cm wide × 60 m long × 0.05 m thick).
m) The wound bobbin 809 was set, and the protective film was wound along with the band-shaped substrate on which the semiconductor film was formed.

(2) After setting the belt-like substrate, each chamber 80
1 to 806 is evacuated once by a pump combining a rotary pump (not shown) and a mechanical booster pump, and He gas is introduced while continuously evacuating to about 200
The inside of each deposition chamber was heated and baked at about 350 ° C. in a He atmosphere of Pa.

(3) After heating and baking,
While evacuating 806 once and continuing to evacuate, H ₂ gas at 1000 sccm is used as a gas to prevent the film formation gas from being mixed between the film formation chambers adjacent to each gas gate 807.
Each raw material gas was introduced into each of the film forming chambers 801 to 803 at a predetermined flow rate. The internal pressure of the supply chamber 805 and the take-up chamber 806 of the strip-shaped substrate is adjusted to 125 Pa by adjusting the opening of the throttle valve provided in the exhaust pipe 812 of each chamber.
The internal pressures of the film forming chambers 801, 802, and 803 are respectively set to 1
It was set to 30 Pa.

(4) When the pressure in each chamber is stabilized, the take-up bobbin of the take-up chamber 806 for the band-shaped substrate is rotated, so that the band-shaped substrate 808 moves at a constant speed of 100 cm / min in the direction from the film formation chamber 801 to 803. To move continuously. A heating heater 810 connected to a temperature control device (not shown) provided in each of the film forming chambers 801 to 803 controls the temperature of the moving strip-shaped substrate so that the moving substrate has a predetermined temperature in the film forming space of each film forming chamber. Control was performed.

(5) When the temperature of the strip-shaped substrate becomes stable, the discharge electrodes 8 provided in the film forming chambers 801, 802 and 803 are formed.
High-frequency power of 13 to 13.56 MHz was supplied from a power supply (not shown) via a matching device. The raw material gas in each of the film forming chambers 801 to 803 is turned into plasma by inputting discharge power,
A semiconductor film was formed on the surface of the strip-shaped substrate that continuously moved in each film forming chamber, and a semiconductor film having a nip structure was continuously formed on the surface of the strip-shaped substrate. Table 1 shows film forming conditions in the film forming chambers 801 to 803.

(6) After the transfer of the belt-like substrate was started, the substrate was continuously moved for 40 minutes, during which a semiconductor film was continuously formed for 35 minutes. After forming the semiconductor laminated film over about 35 m, input of discharge power, introduction of source gas,
The heating of the band-shaped substrate and the film forming chamber was stopped, the inside of the film-forming chamber was purged, the band-shaped substrate and the inside of the apparatus were sufficiently cooled, the apparatus was opened, and the band-shaped substrate was taken out of the apparatus from the winding chamber 806. .

(7) Continuous processing device for taking out strip-shaped substrates
Is continuously processed by the
70 nm thick ITO (In)_TwoO_Three+ S
nO _Two) Form a thin film and use thin wires at regular intervals as current collecting electrodes
30cm x 30cm by forming Ag-shaped electrode
100 photovoltaic elements were continuously formed. In addition, half
After forming the conductor laminated film, after increasing the resistance of the short-circuit occurrence location
No treatment was performed. Of the layer configuration of the fabricated photovoltaic element
A schematic diagram is shown in FIG.

The characteristics of 100 photovoltaic elements (actual sample 1) measuring 30 cm × 30 cm were measured. 1cm x 1 with no shorts due to pinholes or defects
When standardized by the characteristics of the photovoltaic element (reference sample 1) manufactured at the portion of the actual sample 1 under low illuminance light (AM1.
The open-circuit voltage at 5.1 mW / cm ² ) averages 0.80
Met. Further, under the simulated sunlight of the actual sample 1 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.90 on average. Further, even before the post-processing for increasing the resistance of the short-circuited portion, the deterioration of the element characteristics was very slight.

Further, the fabricated photovoltaic element (actual sample 1)
Was measured for element distribution in the film thickness direction using a secondary ion mass spectrometer (SIMS). As a result, in the impurity-doped layer on the outermost surface in contact with the conductive substrate, the impurity element P (phosphorus) has a low distribution on the conductive substrate interface side and a substantially high distribution on the intrinsic semiconductor layer side. Was confirmed.

Comparative Example 1 This example is different from Example 1 in that the impurity concentration in the impurity-doped layer closest to the conductive substrate was fixed. That is, the impurity-doped layer closest to the conductive substrate is formed in one film formation region in the manufacturing apparatus shown in FIG. 8, and the impurity gas concentration in the source gas is adjusted to the intrinsic semiconductor layer interface side. The difference was not changed between the film region and the film formation region on the transparent electrode interface side.

The other points were the same as in the first embodiment,
One hundred photovoltaic elements having a nip structure of × 30 cm (specific sample 1) were continuously manufactured. After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed.

The characteristics were measured for 100 photovoltaic elements (comparative sample 1) measuring 30 cm × 30 cm. 1cm x 1 with no shorts due to pinholes or defects
When standardized by the characteristics of the photovoltaic element (reference sample 1) manufactured in the portion of cm.
The open circuit voltage at 5.1 mW / cm ² ) averages 0.13
Met. In addition, under simulated sunlight of the specific sample 1 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.33 on average.

Therefore, it was found that the specific sample 1 had a larger decrease in device characteristics than the actual sample 1.

When the fabricated photovoltaic element was measured for element distribution in the film thickness direction using a secondary ion mass spectrometer (SIMS), it was found that the impurity element in the impurity doped layer in contact with the conductive substrate was an impurity element. It was confirmed that P (phosphorus) did not change at the same concentration on the conductive substrate interface side and substantially on the intrinsic semiconductor layer side.

(Embodiment 2) In this embodiment, a photovoltaic element having a pin structure was fabricated instead of the nip structure.
And different. That is, when continuously manufacturing a pin structure photovoltaic element made of amorphous silicon on a conductive substrate using the manufacturing apparatus shown in FIG. 8, the impurity-doped layer closest to the conductive substrate has two As a film is formed in the film formation area,
The concentration of the impurity gas in the source gas is made lower in the film formation region on the conductive substrate interface side than in the film formation region on the intrinsic semiconductor layer interface side, and the p-type amorphous silicon layer formed in the film formation chamber 801 is formed. The concentration of B (boron), which is an impurity element, is distributed low on the transparent electrode side. The film forming conditions for each layer were as shown in Table 2.

[0124]

[Table 2]

The other points are the same as in the first embodiment.
m × 30 cm pin structure photovoltaic device (actual sample 2)
Were continuously produced.

After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed. FIG. 1 shows a schematic diagram of the layer configuration of the manufactured photovoltaic element.

The characteristics of 100 photovoltaic elements (actual sample 2) measuring 30 cm × 30 cm were measured. 1cm x 1 with no shorts due to pinholes or defects
When standardized by the characteristics of the photovoltaic element (reference sample 2) manufactured at the portion of the actual sample 2 under low illuminance light (AM1.
The open-circuit voltage at 5.1 mW / cm ² ) averages 0.80
Met. Further, under the simulated sunlight of the actual sample 1 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.90 on average. Further, even before the post-processing for increasing the resistance of the short-circuited portion, the deterioration of the element characteristics was very slight.

In addition, the fabricated photovoltaic element (actual sample 2)
Was measured for element distribution in the film thickness direction using a secondary ion mass spectrometer (SIMS). As a result, in the outermost impurity-doped layer in contact with the conductive substrate, the impurity element B (boron) has a low distribution on the conductive substrate interface side and a substantially high distribution on the intrinsic semiconductor layer side. Was confirmed.

Comparative Example 2 This example is different from Example 2 in that the impurity concentration in the impurity-doped layer closest to the conductive substrate was fixed. That is, the impurity-doped layer closest to the conductive substrate is formed in one film formation region in the manufacturing apparatus shown in FIG. 8, and the impurity gas concentration in the source gas is adjusted to the intrinsic semiconductor layer interface side. The difference was not changed between the film region and the film formation region on the transparent electrode interface side.

The other points were the same as in the second embodiment,
One hundred photovoltaic elements (specific sample 2) having a pin structure of × 30 cm were continuously manufactured. After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed.

The characteristics of 100 photovoltaic elements (specific sample 2) measuring 30 cm × 30 cm were measured. 1cm x 1 with no shorts due to pinholes or defects
When normalized by the characteristics of the photovoltaic element (reference sample 2) manufactured in the portion of cm.
The open circuit voltage at 5.1 mW / cm ² ) averages 0.15
Met. In addition, under simulated sunlight of the specific sample 2 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.35 on average.

Therefore, it was found that the specific sample 2 had a larger decrease in device characteristics than the actual sample 2.

The element distribution in the film thickness direction of the manufactured photovoltaic element was measured by using a secondary ion mass spectrometer (SIMS). It was confirmed that B (boron) did not change at the same concentration on the conductive substrate interface side and substantially on the intrinsic semiconductor layer side.

(Embodiment 3) In this embodiment, the manufacturing apparatus shown in FIG.
A photovoltaic element having an ip structure was manufactured continuously. that time,
Without changing the impurity gas concentration with respect to the Si source gas, the discharge power and the H ₂ dilution ratio of the Si source gas are made lower in the film formation region on the conductive substrate interface side than in the film formation region on the intrinsic semiconductor layer interface side, The difference from the first embodiment is that the crystal grain size of the n-type amorphous silicon layer formed in the film forming chamber 801 of FIG. 8 is distributed lower on the conductive substrate side. Table 3 shows the film forming conditions for each layer.
As shown in FIG.

[0135]

[Table 3]

The other points are the same as in the first embodiment, and
Photovoltaic device with mx30cm pin structure (actual sample 3)
Were continuously produced.

After the formation of the semiconductor multilayer film, no post-treatment for increasing the resistance of the short-circuited portion was performed. FIG. 1 shows a schematic diagram of the layer configuration of the manufactured photovoltaic element.

The characteristics of 100 photovoltaic elements (actual sample 3) measuring 30 cm × 30 cm were measured. 1cm x 1 with no shorts due to pinholes or defects
When standardized by the characteristics of the photovoltaic element (reference sample 3) manufactured at the portion of the actual sample 3 under low illuminance light (AM1.
The open-circuit voltage at 5.1 mW / cm ² ) averages 0.78
Met. Further, under the simulated sunlight of the actual sample 3 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.88 on average. Further, even before the post-processing for increasing the resistance of the short-circuited portion, the deterioration of the element characteristics was very slight.

The distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured using a cross-sectional TEM.
It was confirmed that the crystal grain size was small on the conductive substrate interface side and substantially large on the intrinsic semiconductor layer side.

Comparative Example 3 This example is different from Example 3 in that the crystal grain size in the impurity-doped layer closest to the conductive substrate was fixed. In other words, the impurity-doped layer closest to the conductive substrate is formed in one film formation region in the manufacturing apparatus shown in FIG. 8, so that the film formation region on the interface side of the intrinsic semiconductor layer and the film formation region on the conductive substrate interface side. The film size and the crystal grain size were not changed.

The other points were the same as in the third embodiment,
One hundred photovoltaic elements having a nip structure of × 30 cm (specific sample 3) were continuously manufactured. After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed.

The characteristics of 100 manufactured photovoltaic elements (comparative sample 1) of 30 cm × 30 cm were measured. 1cm x 1 with no shorts due to pinholes or defects
When normalized by the characteristics of the photovoltaic element (reference sample 3) manufactured in the portion of cm.
The open circuit voltage at 5.1 mW / cm ² ) averages 0.13
Met. In addition, under simulated sunlight of the specific sample 3 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.33 on average.

Therefore, it was found that the specific sample 3 had a large decrease in device characteristics as compared with the actual sample 3.

The distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured using a cross-sectional TEM.
It was confirmed that the crystal grain size of was substantially the same on the conductive substrate interface side and on the intrinsic semiconductor layer side.

(Embodiment 4) This embodiment is different from the embodiment 3 in that a photovoltaic element having a pin structure is manufactured instead of the nip structure.
And different. That is, when continuously manufacturing a pin structure photovoltaic element made of amorphous silicon on a conductive substrate using the manufacturing apparatus shown in FIG. 8, the impurity-doped layer closest to the conductive substrate has two As a film is formed in the film formation area,
Without changing the impurity gas concentration with respect to the Si source gas, the discharge power and the H ₂ dilution ratio of the Si source gas are made lower in the film formation region on the conductive substrate interface side than in the film formation region on the intrinsic semiconductor layer interface side, The crystal grain size of the p-type amorphous silicon layer formed in the film forming chamber 801 was set to be lower on the transparent electrode side. The film forming conditions for each layer were as shown in Table 4.

[0146]

[Table 4]

The other points are the same as in the first embodiment.
m × 30 cm pin structure photovoltaic element (actual sample 4)
Were continuously produced.

After the formation of the semiconductor multilayer film, no post-treatment for increasing the resistance of the short-circuited portion was performed. FIG. 1 shows a schematic diagram of the layer configuration of the manufactured photovoltaic element.

The characteristics of 100 photovoltaic elements (actual sample 4) measuring 30 cm × 30 cm were measured. 1cm x 1 with no shorts due to pinholes or defects
When standardized by the characteristics of the photovoltaic element (reference sample 4) manufactured in the portion of cm.
The open circuit voltage at 5.1 mW / cm ² ) averages 0.7
It was 8. Further, under the simulated sunlight of the actual sample 4 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.88 on average. Further, even before the post-processing for increasing the resistance of the short-circuited portion, the deterioration of the element characteristics was very slight.

When the distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured using a cross-sectional TEM, the impurity-doped layer in contact with the conductive substrate was
It was confirmed that the crystal grain size was small on the conductive substrate interface side and substantially large on the intrinsic semiconductor layer side.

Comparative Example 4 This example is different from Example 4 in that the crystal grain size in the impurity-doped layer closest to the conductive substrate was fixed. In other words, the impurity-doped layer closest to the conductive substrate is formed in one film formation region in the manufacturing apparatus shown in FIG. 8, so that the film formation region on the interface side of the intrinsic semiconductor layer and the film formation region on the conductive substrate interface side. The film size and the crystal grain size were not changed.

The other points were the same as in the fourth embodiment,
100 × 30 cm photovoltaic devices having a pin structure (specific sample 4) were continuously produced. After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed.

The characteristics were measured for 100 photovoltaic elements (comparative sample 4) measuring 30 cm × 30 cm. 1cm x 1 with no shorts due to pinholes or defects
When normalized by the characteristics of the photovoltaic element (reference sample 4) manufactured in the portion of cm.
The open circuit voltage at 5.1 mW / cm ² ) averages 0.13
Met. In addition, under simulated sunlight of the specific sample 3 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.33 on average.

Therefore, it was found that the specific sample 4 had a large decrease in device characteristics as compared with the actual sample 4.

When the distribution of the crystal grain size in the thickness direction of the manufactured photovoltaic element was measured using a cross-sectional TEM, the impurity-doped layer in contact with the conductive substrate was
It was confirmed that the crystal grain size of was substantially the same on the conductive substrate interface side and on the intrinsic semiconductor layer side.

(Embodiment 5) This embodiment differs from Embodiment 4 in that the impurity concentration and the crystal grain size in the impurity-doped layer closest to the conductive substrate are reduced on the conductive substrate side. That is, when a pin structure photovoltaic element made of amorphous silicon is continuously manufactured on a conductive substrate using the manufacturing apparatus shown in FIG.
The film is formed in two film formation regions, and the impurity gas concentration and discharge power with respect to the Si source gas and H _{2 of the} Si source gas
The dilution ratio is made lower in the film formation region on the conductive substrate interface side than in the film formation region on the intrinsic semiconductor layer interface side, and the impurity concentration and crystal of the P-type amorphous silicon layer formed in the film formation chamber 801 are reduced. The particle size was distributed low on the conductive substrate side. The film forming conditions for each layer were as shown in Table 5.

[0157]

[Table 5]

The other points are the same as in the first embodiment, and
m × 30 cm pin structure photovoltaic device (actual sample 5)
Were continuously produced.

After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed. FIG. 1 shows a schematic diagram of the layer configuration of the manufactured photovoltaic element.

The characteristics of 100 photovoltaic elements (actual sample 5) measuring 30 cm × 30 cm were measured. 1cm x 1 with no shorts due to pinholes or defects
When standardized by the characteristics of the photovoltaic element (reference sample 5) manufactured at the portion of the actual sample 5 under low illuminance light (AM1.
The average open circuit voltage at 5.1 mW / cm ² ) is 0.82 on average.
Met. Moreover, under simulated sunlight of the actual sample 5 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.92 on average. Further, even before the post-processing for increasing the resistance of the short-circuited portion, the deterioration of the element characteristics was very slight.

The fabricated photovoltaic element (actual sample 5)
Was measured for element distribution in the film thickness direction using a secondary ion mass spectrometer (SIMS). As a result, in the outermost impurity-doped layer in contact with the conductive substrate, the impurity element B (boron) has a low distribution on the conductive substrate interface side and a substantially high distribution on the intrinsic semiconductor layer side. Was confirmed.

Further, the distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured using a cross-sectional TEM.
It was confirmed that the crystal grain size was small on the conductive substrate interface side and substantially large on the intrinsic semiconductor layer side.

(Embodiment 6) This embodiment is different from Embodiment 4 in that the impurity concentration in the impurity-doped layer closest to the conductive substrate is lower on the conductive substrate side. That is, when a pin structure photovoltaic element made of amorphous silicon is continuously manufactured on a conductive substrate using the manufacturing apparatus shown in FIG. The film is formed in the film formation region, and the impurity gas concentration in the source gas is made lower in the film formation region on the transparent electrode interface side than in the film formation region on the intrinsic semiconductor layer interface side. N
The concentration of P (phosphorus), which is an impurity element of the type amorphous silicon layer, was distributed low on the transparent electrode side. The film forming conditions for each layer were as shown in Table 6.

[0164]

[Table 6]

The other points are the same as in the first embodiment, and
m × 30 cm pin structure photovoltaic device (actual sample 6)
Were continuously produced.

After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed. FIG. 1 shows a schematic diagram of the layer configuration of the manufactured photovoltaic element.

The characteristics of 100 photovoltaic elements (actual sample 6) measuring 30 cm × 30 cm were measured. 1cm x 1 with no shorts due to pinholes or defects
When normalized by the characteristics of the photovoltaic element (reference sample 6) manufactured in the portion of cm, the actual sample 6 under low illuminance light (AM1.
The open-circuit voltage at 5.1 mW / cm ² ) averages 0.80
Met. Moreover, under simulated sunlight of the actual sample 6 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.90 on average. Further, even before the post-processing for increasing the resistance of the short-circuited portion, the deterioration of the element characteristics was very slight.

The fabricated photovoltaic element (actual sample 6)
Was measured for element distribution in the film thickness direction using a secondary ion mass spectrometer (SIMS). As a result, in the outermost impurity-doped layer in contact with the conductive substrate, the impurity element B (boron) has a low distribution on the conductive substrate interface side and a substantially high distribution on the intrinsic semiconductor layer side. Was confirmed.

(Embodiment 7) In this embodiment, the manufacturing apparatus shown in FIG. 10 is used to continuously manufacture a nipnip structure photovoltaic element made of amorphous silicon on a conductive substrate. Different from 1. At this time, the impurity-doped layer closest to the conductive substrate is formed in two film formation regions so that the impurity gas concentration in the source gas is more conductive substrate than the film formation region on the intrinsic semiconductor layer interface side. Lower in the film formation area on the interface side,
The concentration of P (phosphorus), which is an impurity element of the n-type amorphous silicon layer formed in the film formation chamber 1001A, was distributed low on the conductive substrate side.

As a conductive substrate, a 0.13 mm thick SU was used.
A 300 nm-thick Ag layer and a 1000 nm-thick transparent and low-resistance (ρ = 1 × 10 ⁻² Ωcm) ZnO layer are laminated on S430BA by DC magnetron sputtering,
The one having a high reflectance and a fine uneven shape formed on the surface was used. The film forming conditions for each layer were as shown in Tables 7 and 8.

[0171]

[Table 7]

[0172]

[Table 8]

The other points are the same as in the first embodiment.
One hundred photovoltaic elements (actual sample 7) having a nipnip structure of mx 30 cm were manufactured continuously.

After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed. FIG. 2 shows a schematic diagram of the layer configuration of the manufactured photovoltaic element.

The characteristics of 100 photovoltaic elements (actual sample 7) measuring 30 cm × 30 cm were measured. 1cm x 1 with no shorts due to pinholes or defects
When standardized by the characteristics of the photovoltaic element (reference sample 7) manufactured at the portion of the actual sample 6 under low illuminance light (AM1.
The open-circuit voltage at 5.1 mW / cm ² ) averages 0.80
Met. Moreover, under simulated sunlight of the actual sample 6 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.90 on average. Further, even before the post-processing for increasing the resistance of the short-circuited portion, the deterioration of the element characteristics was very slight.

The fabricated photovoltaic element (actual sample 7)
Was measured for element distribution in the film thickness direction using a secondary ion mass spectrometer (SIMS). As a result, in the impurity-doped layer on the outermost surface in contact with the conductive substrate, the impurity element P (phosphorus) has a low distribution on the conductive substrate interface side and a substantially high distribution on the intrinsic semiconductor layer side. Was confirmed.

Comparative Example 7 This example is different from Example 7 in that the impurity concentration in the impurity-doped layer closest to the conductive substrate was fixed. That is, the impurity-doped layer closest to the conductive substrate is formed in one film formation region in the manufacturing apparatus shown in FIG. 8, and the impurity gas concentration in the source gas is adjusted to the intrinsic semiconductor layer interface side. The difference was not changed between the film region and the film formation region on the transparent electrode interface side.

The other points were the same as in the seventh embodiment,
100 × 30 cm photovoltaic devices having a nipnip structure (specific sample 7) were continuously produced. After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed.

The characteristics of 100 photovoltaic elements (comparative sample 7) measuring 30 cm × 30 cm were measured. 1cm x 1 with no shorts due to pinholes or defects
When standardized by the characteristics of the photovoltaic element (reference sample 7) manufactured in the portion of cm.
The open circuit voltage at 5.1 mW / cm ² ) averages 0.15
Met. In addition, the simulated sunlight of the specific sample 7 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.35 on average.

Therefore, it was found that the specific sample 7 had a larger decrease in device characteristics than the actual sample 7.

The element distribution in the film thickness direction of the fabricated photovoltaic element was measured by using a secondary ion mass spectrometer (SIMS). It was confirmed that P (phosphorus) did not change at the same concentration on the conductive substrate interface side and substantially on the intrinsic semiconductor layer side.

Example 8 In this example, a photovoltaic element having a nipnip structure made of amorphous silicon was continuously manufactured on a conductive substrate using the manufacturing apparatus shown in FIG.
At this time, the discharge power and the H ₂ dilution ratio of the Si source gas were changed in the film formation region closer to the conductive substrate interface than the film formation region closer to the intrinsic semiconductor layer interface, without changing the impurity gas concentration relative to the Si source gas. Embodiment 7 is different from Embodiment 7 in that the crystal grain size of the n-type amorphous silicon layer formed in the film forming chamber 1001A in FIG. The film forming conditions for each layer were as shown in Tables 9 and 8.

[0183]

[Table 9]

The other points are the same as in the first embodiment.
m × 30 cm pin structure photovoltaic device (actual sample 8)
Were continuously produced.

After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed. FIG. 2 shows a schematic diagram of the layer configuration of the manufactured photovoltaic element.

The characteristics of 100 photovoltaic elements (actual sample 8) measuring 30 cm × 30 cm were measured. 1cm x 1 with no shorts due to pinholes or defects
When standardized by the characteristics of the photovoltaic element (reference sample 8) manufactured at the portion of the actual sample 8 under low illuminance light (AM1.
The open-circuit voltage at 5.1 mW / cm ² ) averages 0.80
Met. Moreover, under simulated sunlight of the actual sample 8 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.90 on average. Further, even before the post-processing for increasing the resistance of the short-circuited portion, the deterioration of the element characteristics was very slight.

When the distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured by using the cross-sectional TEM, the impurity-doped layer in contact with the conductive substrate was
It was confirmed that the crystal grain size was small on the conductive substrate interface side and substantially large on the intrinsic semiconductor layer side.

Comparative Example 8 This example differs from Example 8 in that the crystal grain size in the impurity-doped layer closest to the conductive substrate was made constant. That is, the impurity-doped layer closest to the conductive substrate is formed in one film formation region in the manufacturing apparatus shown in FIG. 10, so that the film formation region on the interface side of the intrinsic semiconductor layer and the film formation region on the conductive substrate interface side. The film size and the crystal grain size were not changed.

The other points were the same as in the first embodiment and
100 × 30 cm photovoltaic devices having a nipnip structure (specific sample 8) were continuously manufactured. After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed.

The characteristics of 100 photovoltaic elements (specific sample 8) of 30 cm × 30 cm thus produced were measured. 1cm x 1 with no shorts due to pinholes or defects
When standardized by the characteristics of the photovoltaic element (reference sample 8) manufactured in the portion of cm.
The open circuit voltage at 5.1 mW / cm ² ) averages 0.15
Met. Further, the sample under the simulated sunlight (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.35 on average.

Therefore, it was found that the specific sample 8 had a larger decrease in device characteristics than the actual sample 8.

The distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured using a cross-sectional TEM.
It was confirmed that the crystal grain size of was not changed between the conductive substrate interface side and the intrinsic semiconductor layer side, and had a uniform distribution.

(Embodiment 9) In this embodiment, the manufacturing apparatus shown in FIG. 11 is used to continuously manufacture a photovoltaic element having a nipnipnip structure made of amorphous silicon on a conductive substrate. Different from 1. At this time, the impurity-doped layer closest to the conductive substrate is formed in two film formation regions so that the impurity gas concentration in the source gas is more conductive substrate than the film formation region on the intrinsic semiconductor layer interface side. The concentration of P (phosphorus), which is an impurity element of the n-type amorphous silicon layer formed in the film formation chamber 1001A, was distributed low on the conductive substrate side.

As a conductive substrate, a 0.13 mm thick SU was used.
A 300 nm-thick Ag layer and a 1000 nm-thick transparent and low-resistance (ρ = 1 × 10 ⁻² Ωcm) ZnO layer are laminated on S430BA by DC magnetron sputtering,
The one having a high reflectance and a fine uneven shape formed on the surface was used. The film forming conditions for each layer are shown in Table 10, Table 11, and Table 1.
As shown in FIG.

[0195]

[Table 10]

[0196]

[Table 11]

[0197]

[Table 12]

The other points are the same as in the first embodiment.
One hundred photovoltaic elements (actual sample 9) having a nipnipnip structure of mx 30 cm were continuously manufactured.

After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed. FIG. 3 shows a schematic diagram of the layer configuration of the manufactured photovoltaic element.

The characteristics of 100 photovoltaic elements (actual sample 9) measuring 30 cm × 30 cm were measured. 1cm x 1 with no shorts due to pinholes or defects
When standardized by the characteristics of the photovoltaic element (reference sample 9) manufactured in the portion of cm.
The open-circuit voltage at 5.1 mW / cm ² ) averages 0.80
Met. Moreover, under simulated sunlight of the actual sample 9 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.90 on average. Further, even before the post-processing for increasing the resistance of the short-circuited portion, the deterioration of the element characteristics was very slight.

Further, the fabricated photovoltaic element (actual sample 7)
Was measured for element distribution in the film thickness direction using a secondary ion mass spectrometer (SIMS). As a result, in the impurity-doped layer on the outermost surface in contact with the conductive substrate, the impurity element P (phosphorus) has a low distribution on the conductive substrate interface side and a substantially high distribution on the intrinsic semiconductor layer side. Was confirmed.

Comparative Example 9 This example is different from Example 7 in that the impurity concentration in the impurity-doped layer closest to the conductive substrate was made constant. That is, the impurity-doped layer closest to the conductive substrate is formed in one film formation region in the manufacturing apparatus shown in FIG. 11 so that the impurity gas concentration in the source gas is adjusted to the intrinsic semiconductor layer interface side. The difference was not changed between the film region and the film formation region on the transparent electrode interface side.

The other points were the same as in the ninth embodiment,
100 × 30 cm photovoltaic devices having a nipnipnip structure (specific sample 9) were continuously manufactured. After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed.

The characteristics of 100 photovoltaic elements (comparative sample 9) measuring 30 cm × 30 cm were measured. 1cm x 1 with no shorts due to pinholes or defects
When standardized by the characteristics of the photovoltaic element (reference sample 9) manufactured in the portion of cm.
The open circuit voltage at 5.1 mW / cm ² ) averages 0.15
Met. In addition, under simulated sunlight of the specific sample 9 (AM1.
The intrinsic conversion efficiency at 5,100 mW / cm ² ) was 0.35 on average.

Therefore, it was found that the specific sample 9 had a larger decrease in device characteristics than the actual sample 9.

When the produced photovoltaic element was measured for element distribution in the film thickness direction using a secondary ion mass spectrometer (SIMS), it was found that the impurity element was found to be in the impurity doped layer in contact with the conductive substrate. It was confirmed that P (phosphorus) did not change at the same concentration on the conductive substrate interface side and substantially on the intrinsic semiconductor layer side.

Example 10 In this example, a photovoltaic element having a nipnipnip structure made of amorphous silicon was continuously manufactured on a conductive substrate using the manufacturing apparatus shown in FIG. At that time, the discharge power and the H ₂ dilution rate of the Si source gas were changed without changing the impurity gas concentration with respect to the Si source gas.
The film size of the n-type amorphous silicon layer formed in the film formation chamber 1101A in FIG. 11 is made lower than that of the film formation region on the interface side of the intrinsic semiconductor layer in the film formation region on the interface side of the conductive substrate. The difference from the ninth embodiment is that the distribution is lower on the side of the conductive substrate.
The film forming conditions for each layer were as shown in Tables 13, 11, and 12.

[0208]

[Table 13]

The other points are the same as those in the first embodiment.
One hundred photovoltaic elements (actual sample 10) having a nipnipnip structure of mx 30 cm were manufactured continuously.

After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed. FIG. 3 shows a schematic diagram of the layer configuration of the manufactured photovoltaic element.

The characteristics of 100 photovoltaic elements (actual samples 10) measuring 30 cm × 30 cm were measured. 1cm × with no shorts due to pinholes or defects
Photovoltaic element fabricated in 1 cm section (reference sample 10)
When the standardization is performed by the characteristics of
The average open circuit voltage at 1.5, 1 mW / cm ² ) is 0.
80. In addition, the simulated sunlight of the actual sample 10 (AM
The intrinsic conversion efficiency at 1.5, 100 mW / cm ² ) was 0.90 on average. Further, even before the post-processing for increasing the resistance of the short-circuited portion, the deterioration of the element characteristics was very slight.

Further, the distribution of the crystal grain size in the film thickness direction of the manufactured photovoltaic element was measured by using the cross-sectional TEM.
It was confirmed that the crystal grain size was small on the conductive substrate interface side and substantially large on the intrinsic semiconductor layer side.

Comparative Example 10 This example is different from Example 10 in that the crystal grain size in the impurity-doped layer closest to the conductive substrate was made constant. That is, the impurity-doped layer closest to the conductive substrate is formed in one film formation region in the manufacturing apparatus shown in FIG. The film size and the crystal grain size were not changed.

The other points were the same as in the first embodiment,
100 × 30 cm photovoltaic devices having a nipnip structure (specific sample 10) were continuously manufactured. After the formation of the semiconductor laminated film, no post-treatment for increasing the resistance of the short-circuited portion was performed.

The characteristics of 100 photovoltaic elements (comparative sample 10) measuring 30 cm × 30 cm were measured. 1cm × with no shorts due to pinholes or defects
Photovoltaic element fabricated in 1 cm section (reference sample 10)
Is normalized under the low illuminance light (AM
The average open circuit voltage at 1.5, 1 mW / cm ² ) is 0.
It was 15. In addition, under simulated sunlight (AM
The intrinsic conversion efficiency at 1.5, 100 mW / cm ² ) was 0.35 on average.

Therefore, it was found that the specific sample 10 had a large decrease in device characteristics as compared with the actual sample 10.

Further, when the distribution of the crystal grain size in the thickness direction of the manufactured photovoltaic element was measured by using the cross-sectional TEM, the impurity-doped layer in contact with the conductive substrate was
It was confirmed that the crystal grain size of was not changed between the conductive substrate interface side and the intrinsic semiconductor layer side, and had a uniform distribution.

[0218]

As described above, according to the present invention,
Even if a partial short-circuit occurs in the semiconductor layer during a long-term use period, the silicon-based non-volatile semiconductor can be realized without significant deterioration in characteristics, excellent in long-term reliability, and without complicating the manufacturing process. A photovoltaic element made of a single crystal semiconductor is obtained.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing an example of a layer configuration of a single type photovoltaic element according to the present invention.

FIG. 2 is a schematic sectional view showing an example of a layer configuration of a two-layer tandem photovoltaic device according to the present invention.

FIG. 3 is a schematic sectional view showing an example of a layer configuration of a three-layer tandem photovoltaic device according to the present invention.

FIG. 4 is a schematic cross-sectional view illustrating a layer configuration of a photovoltaic element manufactured in a process leading to the present invention.

FIG. 5 is a schematic diagram showing a configuration of a film forming apparatus for a photovoltaic element manufactured in a process leading to the present invention.

FIG. 6 is a graph showing an example of an impurity concentration distribution in a thickness direction in an impurity-doped layer in contact with a conductive substrate of a photovoltaic device according to the present invention.

FIG. 7 is a graph showing an example of the distribution of the average crystal grain size of silicon in the thickness direction in the impurity-doped layer in contact with the conductive substrate of the photovoltaic device according to the present invention.

FIG. 8 is a schematic view showing one example of a manufacturing apparatus used for manufacturing a photovoltaic element according to the present invention.

FIG. 9 is a schematic view showing another example of the manufacturing apparatus used for manufacturing the photovoltaic element according to the present invention.

FIG. 10 is a schematic view showing another example of the manufacturing apparatus used for manufacturing the photovoltaic element according to the present invention.

FIG. 11 is a schematic view showing another example of the manufacturing apparatus used for manufacturing the photovoltaic element according to the present invention.

[Explanation of symbols]

101, 201, 301, 401 conductive substrate, 102, 202, 302, 402 first semiconductor layer, 103, 203, 303, 403 second semiconductor layer, 104, 204, 304, 404 third semiconductor layer, 105, 205 , 305, 405 Transparent electrode, 106, 206, 306, 406 Current collecting electrode, 107, 207, 307, 407 Incident light, 108, 208, 308, 408 Area near the conductive substrate interface, 209, 309, 409, 415 4th semiconductor layer, 210, 310, 410 5th semiconductor layer, 211, 311, 411 6th semiconductor layer, 312, 412 7th semiconductor layer, 313, 413 8th semiconductor layer, 314, 414 9th semiconductor layer, 501, 801, 901, 1001A, 1001B, 1
101A, 1101B, 1101C n (or p) type semiconductor layer deposition chamber, 502, 802, 902, 1002A, 1002B, 1
102A, 1102B, 1102C Substantially intrinsic semiconductor layer deposition chamber, 503, 803, 903, 1003A, 1003B, 1
103A, 1103B, 1103C P-type (or n-type) semiconductor layer deposition chamber, 504 n-type semiconductor layer deposition chamber, 505, 805, 905, 1005, 1105 Strip substrate supply chamber, 506, 806, 906, 1006 507, 807, 907, 1007, 1107 Gas gate, 508, 808, 908, 1008, 1108 Belt substrate, 509, 809, 909, 1009, 1109 Belt sheet, 510, 810, 910, 1010, 1110 Heater, 511, 811, 911, 1011, 1111 Source gas introduction pipe, 512, 812, 912, 1012, 1112 Exhaust pipe, 513, 813, 913, 1013, 1113 Discharge electrode, 914 Waveguide, 915 Microwave introduction window.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Naoshi Yoshizato 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Yuzo Koda 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Non-corporation (72) Inventor Tomoki Nishimoto 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Takahiro Yajima 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Masahiro Kanai 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (56) References JP-A-63-160282 (JP, A) JP-A-4-132269 (JP, A) JP-A-63-258078 (JP, A) JP-A-62-115785 (JP, A) JP-A-3-159179 (JP, A) JP-A-2-96380 (JP, A) JP-A-4-168770 (JP, A) (58)査the field (Int.Cl. ^7, DB name) H01L 31/04 - 31/078

Claims (6)

(57) [Claims] At least a layer structure of a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second layer
A semiconductor layer / a third semiconductor layer having a conductivity type opposite to the first conductivity type / a transparent electrode; wherein the first to third semiconductor layers are made of a silicon-based non-single-crystal semiconductor; In the photovoltaic element having a structure in which light is incident from above, the impurity concentration that determines the conductivity type of the first semiconductor layer has a distribution that is lower on the conductive substrate side than on the second semiconductor layer side. A photovoltaic element characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein the layer structure is at least a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second layer.
Semiconductor layer / third semiconductor layer having a conductivity type opposite to the first conductivity type / fourth semiconductor layer having the first conductivity type / substantially intrinsic fifth semiconductor layer / the first conductivity type A sixth semiconductor layer / transparent electrode having a conductivity type opposite to the mold type, wherein the first to sixth semiconductor layers are made of a silicon-based non-single-crystal semiconductor and have a structure in which light enters from the transparent electrode side In the photovoltaic element, the photovoltaic element has a distribution in which the impurity concentration that determines the conductivity type of the first semiconductor layer is lower on the conductive substrate side than on the second semiconductor layer side. element. 3. The semiconductor device according to claim 1, wherein the layer structure is at least a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second layer.
Semiconductor layer / third semiconductor layer having a conductivity type opposite to the first conductivity type / fourth semiconductor layer having the first conductivity type / substantially intrinsic fifth semiconductor layer / the first conductivity type A sixth semiconductor layer having a conductivity type opposite to the type / a seventh semiconductor layer having the first conductivity type / a substantially intrinsic eighth semiconductor layer /
A ninth semiconductor layer / transparent electrode having a conductivity type opposite to the first conductivity type, wherein the first to ninth semiconductor layers are made of a silicon-based non-single-crystal semiconductor, and light is incident from the transparent electrode side. Wherein the impurity concentration that determines the conductivity type of the first semiconductor layer has a distribution that is lower on the conductive substrate side than on the second semiconductor layer side. Photovoltaic element. 4. At least a layer structure of a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second layer
A semiconductor layer / a third semiconductor layer having a conductivity type opposite to the first conductivity type / a transparent electrode; wherein the first to third semiconductor layers are made of a silicon-based non-single-crystal semiconductor; In the photovoltaic element having a structure in which light is incident from above, the crystal forming the first semiconductor layer has a distribution in which the grain size of the crystal is smaller on the conductive substrate side than on the second semiconductor layer side. A photovoltaic element characterized by the above-mentioned. 5. The semiconductor device according to claim 1, wherein the layer structure is at least a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second layer.
Semiconductor layer / third semiconductor layer having a conductivity type opposite to the first conductivity type / fourth semiconductor layer having the first conductivity type / substantially intrinsic fifth semiconductor layer / the first conductivity type A sixth semiconductor layer / transparent electrode having a conductivity type opposite to the mold type, wherein the first to sixth semiconductor layers are made of a silicon-based non-single-crystal semiconductor and have a structure in which light enters from the transparent electrode side In the photovoltaic element, the particle diameter of the crystal constituting the first semiconductor layer has a distribution that is smaller on the conductive substrate side than on the second semiconductor layer side. . 6. At least a layer structure of a conductive substrate / a first semiconductor layer having a first conductivity type / a substantially intrinsic second layer
Semiconductor layer / third semiconductor layer having a conductivity type opposite to the first conductivity type / fourth semiconductor layer having the first conductivity type / substantially intrinsic fifth semiconductor layer / the first conductivity type A sixth semiconductor layer having a conductivity type opposite to the type / a seventh semiconductor layer having the first conductivity type / a substantially intrinsic eighth semiconductor layer /
A ninth semiconductor layer / transparent electrode having a conductivity type opposite to the first conductivity type, wherein the first to ninth semiconductor layers are made of a silicon-based non-single-crystal semiconductor, and light is incident from the transparent electrode side. In the photovoltaic element having a structure for performing the following, the grain size of the crystal constituting the first semiconductor layer has a distribution that is smaller on the conductive substrate side than on the second semiconductor layer side. Photovoltaic element.