JP3017737B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor region on an insulating substrate is element-isolated and a low-resistance region is provided in the semiconductor region. The present invention relates to a method for manufacturing a semiconductor device in which a low-resistance region such as a layer is formed in a semiconductor region.

[Conventional technology]

Conventionally, in a semiconductor device, a low resistance region such as a buried layer may be provided in a portion deeper than a surface of a semiconductor substrate. In such a semiconductor device having a low-resistance region provided in a deep portion of a base, in order to electrically connect the low-resistance region to electrodes and wiring constituting a semiconductor element provided on the surface of the base, It is necessary to draw out the wiring layer connected to the low resistance region to the surface of the base.

In such a semiconductor device, a take-out portion is provided for drawing out a wiring layer connected to a low-resistance region provided deep in a semiconductor substrate to the surface of the substrate. The take-out portion is provided in a semiconductor region where a semiconductor element is formed and a region separated by a field oxide film.

[Problems to be solved by the invention]

However, in the case where the extraction portion is provided in the region separated by the field oxide film, even if the semiconductor element is miniaturized, an extraction region separate from the semiconductor region is required. Further miniaturization of the device becomes difficult.

The problem to be solved by the present invention is to provide a semiconductor device having the above-described structure without using a region for separating a semiconductor region and a region where a take-out portion for drawing a low-resistance region provided at a deep part of the base to the base surface is formed. It is an object of the present invention to provide a method of manufacturing a semiconductor device which realizes further miniaturization and high integration of a semiconductor element by drawing out a wiring layer connected to a resistance region to a substrate surface.

[Means for solving the problem]

In order to solve the above-described problems, the present invention provides a method for forming a groove in a region where an element isolation region of a semiconductor substrate is formed, the groove being substantially perpendicular to the surface of the semiconductor substrate. Forming an insulating film on a simple side wall;
Forming a low-resistance region in a region of the semiconductor substrate other than the groove; and forming a wiring layer provided along a sidewall substantially perpendicular to a surface of the semiconductor substrate in the groove and connected to the low-resistance region. Forming, forming an insulating layer on the wiring layer in the groove where the wiring layer is formed, bonding the semiconductor substrate to a support from the insulating layer side, A step of polishing from the opposite side of the support to expose the wiring layer on the surface of the semiconductor substrate.

As the insulating substrate, an insulating substrate such as a glass substrate or a ceramic substrate, or a substrate obtained by forming an insulating film on the surface of a silicon substrate or another semiconductor substrate is used.

[Action]

In the present invention, the support is attached to the insulating layer side of the semiconductor substrate. As a result, the semiconductor substrate side provided with the groove portion becomes the inside of the substrate after the attachment. The wiring layer is provided along the side wall substantially perpendicular to the surface of the semiconductor substrate in the trench, and is formed in advance so as to be connected to the low-resistance region and extend on the surface of the semiconductor substrate. The connection is made to the region inside the base. Then, by polishing the semiconductor substrate from the opposite side of the support, the wiring layer,
By being exposed on the surface of the semiconductor substrate, it is drawn to the surface of the substrate.

Embodiment First, a semiconductor device manufactured according to an embodiment of the present invention will be described. As shown in FIG.
A silicon oxide film 2 is provided on a silicon substrate 1 so as to form an insulating substrate.

On the silicon oxide film 2, a semiconductor region 4 that is isolated by the element isolation region 3 is provided. Element isolation region 3
Is formed using a groove 5 formed in the base by anisotropic etching such as RIE, has a substantially rectangular cross section, is integrated with the silicon oxide film 2 at the bottom, and Surrounds the semiconductor region 4 while facing the substrate surface. As shown in FIG. 1, the element isolation region 3 is formed by providing the groove 5 substantially perpendicular to the surface of the insulating substrate, so that side walls substantially perpendicular to the surface of the insulating substrate are formed on both sides. Have been.

The semiconductor region 4 separated from the device isolation region 3 is
A buried layer 8, which is a low resistance region, is formed at the bottom. The buried layer 8 is formed of an N ⁺ type impurity diffusion region.
Below this buried layer 8, a polysilicon layer 7 as a wiring layer is formed between the buried layer 8 and the silicon oxide film 2. Therefore, the buried layer 8 is sufficiently electrically connected to the polysilicon layer 7. On the side of the semiconductor region 4, a silicon oxide film 6 is formed as an insulating film so as to surround the semiconductor region 4 with a side wall of the trench 5. Between the silicon oxide film 6 and the element isolation region 3, a polysilicon layer 7 drawn from the bottom of the buried layer 8 is interposed. That is, the polysilicon layer 7 is connected to the buried layer 8 at the bottom of the semiconductor region 4, is drawn out from the buried layer 8 to the element isolation region 3 in a plane parallel to the main surface of the substrate, and is substantially perpendicular to the element isolation region 3. It extends along the side wall to the surface of the substrate in direct contact with the element isolation region 3. In a portion extending along the substantially vertical side wall, the polysilicon layer 7 has a silicon oxide film 6 interposed between the polysilicon layer 7 and the semiconductor region 4, and the polysilicon layer 7 has the semiconductor region 4 except for the buried layer 8. Is insulated from

The semiconductor region 4 includes a base region 9 as a P-type impurity diffusion region and an emitter region as an N-type impurity diffusion region.
10 is formed. The base region 9 is a graft base region
9g and the intrinsic base region 9i. The graft base region 9g is formed in conformity by impurity diffusion from the polysilicon layer 11 formed on the substrate surface, and is formed below the polysilicon layer 11 and facing the substrate surface. The intrinsic base region 9i is formed by introducing impurities through an opening provided in the interlayer insulating film 12, and is formed in a region surrounded by the graft base region 9g. Emitter region 10 is also formed to face the substrate surface in a consistent manner through the opening. The emitter region 10 is connected to the emitter wiring electrode 15e via the thin polysilicon layer 14, and the graft base region 9g is connected to the base wiring electrode 15b via the polysilicon layer 11.
Connected to. The buried layer 8 is connected to the collector wiring electrode 15c via the polysilicon layer 7 formed along the side wall of the element isolation region 3.

The semiconductor device having such a structure is provided with a buried layer 8
Is taken out through a polysilicon layer 7 formed directly along the side wall of the element isolation region 3 and covered with a silicon oxide film 6. For this reason, the region for taking out the collector can be made sufficiently small, and miniaturization of the element can be realized. Its parasitic capacitance C _cs
The parasitic resistance r _sc can also be kept small. Further, the polysilicon layer 7 is formed between the element isolation region 3 and the silicon oxide film 6 in the base.
, And diffusion of impurities in the extracted portion can be suppressed.

An embodiment of the present invention for manufacturing a semiconductor device having the above-described structure will be described in accordance with the steps with reference to FIGS. 2A to 2E.

First, as shown in FIG. 2A, a groove 22 is formed in a region for forming an element isolation region of a silicon substrate 21 as a semiconductor substrate. The groove 22 is formed by, for example, the RIE method so as to have a side wall substantially perpendicular to the surface of the silicon substrate 21. Next, a silicon oxide film 23 as an insulating film is formed on the side walls and the bottom of the groove 22. No silicon oxide film is formed on the surface of the silicon substrate 21. This is for connection with a low resistance region to be formed next. In order to expose the silicon substrate 21 on the surface, a silicon nitride film is formed in advance on the surface of the silicon substrate 21 and selectively oxidized to form a groove.
After the silicon oxide film 23 is formed only inside the silicon oxide film 22 or the silicon oxide film 23 is formed on the entire surface, the silicon oxide film 23 other than the groove 22 is removed by filling the resist only at the groove 22. You may do it.

Next, as shown in FIG. 2b, the exposed silicon substrate
A low resistance region 24 is formed on the surface of 21. This low resistance area 24
Function as a buried layer of the collector. Next, a polysilicon layer 25 is formed over the surface of the low resistance region 24 and the inside of the silicon oxide film 23. This polysilicon layer 25
Functions as a wiring layer. Polysilicon layer 25 is formed by CV
It can be performed by the D method.

Next, as shown in FIG. 2C, a silicon oxide layer 26 as an insulating layer is formed on the entire surface including the groove 22 in which the silicon oxide film 23 and the polysilicon layer 25 are formed. The silicon oxide layer 26 functions as an element isolation region inside the groove 22. In particular, inside the trench 22, the silicon oxide layer 26 is formed on the polysilicon layer 25 as a wiring layer, and the polysilicon layer 25 is sandwiched between the silicon oxide layer 26 and the silicon oxide film 23. Further, since the silicon oxide layer 26 is formed on the entire surface, it also functions as an adhesive layer with the support. Note that the insulating layer is not limited to the silicon oxide layer 26, and may be a structure including a combination of a silicon nitride layer and a silicon oxide layer, or a structure in which the inner wall of the silicon oxide layer is filled with polysilicon. In addition, the silicon oxide layer 26 does not always need to be covered on the polysilicon layer 25 on the low-resistance region 24, and may be another layer or a structure in which the support itself is located at the time of bonding.

Next, another silicon substrate 30 is prepared, and a silicon oxide film 31 is formed on the entire surface of the silicon substrate 30. on the other hand,
The side on which the silicon oxide layer 26 is provided of the silicon substrate 21 that has been subjected to the fine processing described above is bonded to the silicon oxide film 31 of the silicon substrate 30. Then, as shown in FIG. 2D, the silicon oxide film 31 and the silicon oxide layer 26 are bonded.

Polishing is performed from the silicon substrate 21 side of the bonded substrates 21 and 30. As shown in FIG. 2e, when the polished surface reaches the silicon oxide layer 26, the polishing is stopped. Then
The region that was the silicon substrate 21 becomes a semiconductor region 27 in which the silicon oxide layer 26 has been isolated using the silicon oxide layer 26 as an element isolation region.
Further, a polysilicon layer 25 formed between the silicon oxide layer 26 and the silicon oxide film 23 is connected to the low-resistance region 24 and extends along the silicon oxide layer 26 to the substrate surface, and each element is polished. Each is separated. Therefore,
The polysilicon layer 25 is separated and functions as a wiring layer having a sufficiently small occupied area. The region where polishing is stopped may be performed when the polysilicon layer 25 is exposed. In such a case, the polysilicon layer 25 is oxidized to perform element isolation of the polysilicon layer 25 itself. Hereinafter, necessary elements such as a base region, an emitter region, and a wiring electrode are formed to complete the device.

The method of manufacturing a semiconductor device according to the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present invention.

〔The invention's effect〕

Since the semiconductor device manufactured according to the present invention has a wiring layer extending along the element isolation region from the low-resistance region to the substrate surface, the semiconductor region and the low-resistance region provided deep in the substrate are separated from the substrate surface. Electrodes can be taken out without using a region for separating a region where a lead-out portion to be drawn out is formed, and miniaturization and high integration of an element can be realized.

Since the present invention uses a wafer bonding technique, a semiconductor region formed as a result has excellent crystallinity and is suitable for three-dimensional formation. In the bonding technique, one of the substrates is turned upside down. By forming a wiring layer before that, an effective electrode can be taken out. Since the wiring layer is formed along the insulating layer functioning as an element isolation region, the area can be reduced, which is advantageous for high speed operation and the like.

In particular, according to the present invention, since the semiconductor substrate has an element isolation region having a substantially vertical wall surface formed by providing a groove substantially perpendicularly from the surface thereof, the polishing of the substrate varies and the depth of the groove varies. Even if the variation occurs, the distance between the element isolation regions can be made constant, so that the width between the semiconductor regions separated by the element isolation region can be made substantially constant, and furthermore, along the wall surface of the element isolation region. The distance between the provided wiring layers can be made substantially constant.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an essential part showing an example of a semiconductor device manufactured according to an embodiment of the present invention. FIGS. 2a to 2e illustrate an embodiment of the present invention in accordance with the steps. FIG. 21,30 silicon substrate 6,23,31 silicon oxide film 27 semiconductor region 22 trench 25 polysilicon layer 24 low resistance region

Continuation of the front page (51) Int.Cl. ⁷ identification code FI H01L 29/41 H01L 29/44 Z 29/73 29/72 (56) References JP-A-52-47686 (JP, A) JP-A-62 JP-A-244147 (JP, A) JP-A-60-144951 (JP, A) JP-A-48-100081 (JP, A) JP-B-45-25213 (JP, B1)

Claims (1)

(57) [Claims] A groove formed substantially perpendicularly from a surface of the semiconductor substrate in a region of the semiconductor substrate where an element isolation region is formed;
A step of forming an insulating film on a side wall substantially perpendicular to the surface of the semiconductor substrate in the groove; a step of forming a low-resistance region in a region of the semiconductor substrate other than the groove; a surface of the semiconductor substrate in the groove; Forming a wiring layer provided along a substantially perpendicular side wall and connected to the low-resistance region; and forming an insulating layer on the wiring layer in the groove where the wiring layer is formed. A semiconductor device comprising: a step of bonding the semiconductor substrate to the support from the insulating layer side; and a step of polishing the semiconductor substrate from the opposite side of the support to expose the wiring layer to the surface of the semiconductor substrate. Manufacturing method.