JP3018600B2 - Multi-chip semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to an integrated circuit for a large-scale logic circuit.

[0002]

2. Description of the Related Art Conventionally, in order to realize a large-scale logic circuit, there has been adopted a method in which silicon having an input / output circuit formed thereon is used as a substrate, and a plurality of integrated circuits are mounted thereon (hereinafter, referred to as "integrated circuit"). , Silicon on silicon chip).

[0003] The internal structure of this silicon-on-silicon chip is as shown in FIG. On a silicon substrate 501 having wiring formed on a silicon wafer, there are a chip 502 of a CPU (central processing unit) and a peripheral chip 503,
A plurality of memories 504 are arranged next to it. The input / output pads 505 surround the periphery of the silicon substrate.

FIG. 6 is a sectional view of a silicon-on-silicon chip. A wiring layer 602 and input / output pads 603 are formed on a silicon substrate 601. Silicon substrate 6
In FIG. 1, a bipolar input / output circuit 604 is formed, and an integrated circuit 605 such as a CPU and a memory is mounted on the wiring layer 602. The wiring layer 602 and an integrated circuit 605 such as a CPU and a memory are connected by a solder bump 606.

FIG. 7 is a flowchart showing a conventional silicon chip forming process. First, a silicon substrate is formed. An input / output circuit is formed in a bipolar input / output circuit forming step 701. In a test step 702, a test (test of a bipolar input / output circuit) as a silicon substrate is performed, and defective products are discarded. A wiring layer is formed on the remaining substrate in a wiring layer forming step 703.

Next, a silicon chip to be mounted on the substrate is formed. After forming a chip in step 704 and adding solder bumps in step 705, the chips are individually cut off in a dicing step 706.

Further, in step 707, the chip is bonded to the substrate, and a test is performed in step 708 to complete a silicon-on-silicon chip.

[0008]

The conventional silicon substrate has formed a bipolar input / output circuit corresponding to a silicon-on-silicon chip to be formed. But,
The bipolar input / output circuit is provided only for improving the driving force, and does not contribute to the improvement in the degree of integration. The mounting area on the silicon substrate is the same as the mounting area on the ceramic substrate. Therefore, with respect to the mounting area, a merit of using a silicon substrate is not so obtained.

In the case of the silicon substrate, if at least one of the plurality of bipolar input / output circuits formed on the substrate does not operate in the test step 702, the silicon substrate must be discarded. There is evil.

An object of the present invention is to provide a multi-chip semiconductor integrated circuit which solves the above-mentioned problems.

[0011]

In order to achieve the above object, a multichip semiconductor integrated circuit according to the present invention comprises a silicon substrate on which a plurality of memory elements are formed, and a silicon substrate formed on one main surface of the silicon substrate. And an integrated circuit chip connected to the wiring layer and arranged on one main surface side of the silicon substrate.

[0012]

According to the present invention, a memory wafer is used as a substrate of a multi-chip semiconductor integrated circuit.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. First, the mounting surface of the embodiment will be described with reference to FIGS.

FIG. 1 is a sectional view of a silicon-on-silicon chip of the present invention. In the present invention, a memory wafer is used as a silicon substrate. Therefore, as shown in FIG. 1, a plurality of memory elements 104 are connected to a bipolar input / output circuit (604 in FIG. 6) . Wafer
It is different from the conventional example in that it is incorporated in 101 . Other parts are the same as the conventional one. 102 is a wiring layer, 10
3 is an input / output pad, 105 is a CPU, a peripheral chip, 10
Reference numeral 6 denotes a solder bump.

FIG. 2 is an assembly view of the present invention. The memory elements 104 have already been formed on the memory wafer 101. After forming the input / output pads 103 and the wiring layer 102 thereon, the CPU and the peripheral chip 105 are mounted.

FIG. 3 is a mounting diagram of a silicon-on-silicon chip according to the present invention. A CPU and peripheral chips are mounted at predetermined positions on a silicon substrate using a memory wafer shown in the assembly diagram of FIG.

Next, the process of the embodiment will be described with reference to a flowchart showing the manufacturing process of FIG.

First, a silicon substrate is formed using a memory wafer. A memory element is formed in a memory element forming step 401 as a memory manufacturing step. Next, a test as a silicon substrate is performed in a test step 402. If there is no error in this test, a wiring layer is formed on the substrate in step 403, and the substrate and the silicon formed in steps 404 to 406 (equivalent to steps 704 to 706 of the conventional example). The chip is bonded in step 407 to form a silicon-on-silicon chip. This step is the same as the conventional example. If a failure occurs in the test step 402, only the chip part that operates normally is separated for the memory chip in the dicing step 408. It is tested in a memory chip test step 409 and used as a memory chip.

[0019]

As described above, the present invention reduces the mounting area by changing the substrate for a multichip integrated circuit from a silicon substrate on which a bipolar input / output circuit is formed to a memory wafer. Wafers can be used efficiently.

Regarding the mounting area, the conventional silicon on
The chip area is smaller than that of the silicon chip by the amount of the memory chip. For wafer utilization efficiency,
Conventionally, when there is a defect at the substrate level, all of the defects have to be discarded, but in the present invention, they can be used as ordinary memories.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of the present invention.

FIG. 2 is an assembly view showing one embodiment of the present invention.

FIG. 3 is a mounting diagram showing an embodiment of the present invention.

FIG. 4 is a flowchart showing a manufacturing process in one embodiment of the present invention.

FIG. 5 is a mounting diagram showing a conventional example.

FIG. 6 is a sectional view showing a conventional example.

FIG. 7 is a flowchart showing a manufacturing process of a conventional example.

[Description of Reference Numerals] 101 silicon substrate (memory wafer) 102 wiring layer 103 input / output pad 104 memory element 105 CPU, peripheral chip 106 solder bump

Claims (1)

(57) [Claims] 1. A silicon substrate on which a plurality of memory elements are formed; a wiring layer formed on one main surface of the silicon substrate; and a wiring layer connected to the wiring layer and disposed on one main surface side of the silicon substrate. A multi-chip semiconductor integrated circuit, comprising: an integrated circuit chip;