JP3019753B2 - Analog / digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delta-sigma modulation type analog / digital converter used in the field of PCM audio and the like.

[0002]

2. Description of the Related Art A general structure of a delta-sigma modulation type A / D converter is illustrated in FIGS. First, FIG.
The A / D converter shown in (1) performs A / D conversion by performing first-order delta-sigma modulation.
It has an integration unit 2, a quantization unit 3, and an inverse quantization unit 4. In this configuration, every fixed sampling period,
A process of quantizing the integrated value of the integrator 2 by the quantizer 3 to output a 1-bit digital signal, a feedback analog signal equivalent to the output digital signal being generated by the inverse quantizer 4, and The process of integrating the signal obtained by subtracting the feedback analog signal by the integrator 2 is sequentially executed. As a result of repeating such processing, a 1-bit digital signal pulse-modulated by the input analog signal is obtained. FIGS. 15 and 16 show an example of an A / D converter of the type that performs third-order delta-sigma modulation. As in the case of FIG. 14, a subtraction unit 1, an integration unit 2, a quantization unit 3, It is configured using an inverse quantization unit 4. In addition, 5 is an adder.

[0003]

In some cases, A / D conversion of analog signals of a plurality of channels is required in an audio device or the like. In such a case, the above-mentioned A / D converters are arranged in parallel by the number of channels, and each A / D converter is provided.
A / D conversion corresponding to each channel was performed by the converter. For this reason, there is a problem that the circuit of the signal processing system of the audio device becomes large-scale and the device becomes expensive. Further, in the case where such a circuit for performing A / D conversion of a plurality of channels is constituted by an LSI (large-scale integrated circuit), the chip area becomes large, so that the LSI itself becomes expensive. there were.

The present invention has been made in view of the above circumstances, and has as its object to provide an analog / digital converter capable of processing a plurality of channels of analog signals without increasing the circuit scale.

[0005]

The invention according to claim 1 is
An object of the present invention is to provide an analog / digital converter for sequentially converting input analog signals of a plurality of channels into digital signals by time division control. The analog / digital converter, which has the configuration shown in FIG. 1, A input
Integrating means 11 for sequentially executing an integration process corresponding to each channel by accumulating the analog signal in a capacitor
A plurality of integrated value storage means for storing, for each channel, an integrated value signal indicating the result of the integration process corresponding to each channel; and quantizing the result of the integration process corresponding to each channel. Quantization means 13 for sequentially outputting digital signals corresponding to the respective channels, inverse quantization means 14 for converting the digital signals into feedback analog signals, and digitalization of the input analog signals of the respective channels.
Each channel is converted into a signal at each sampling period.
Flannel, a. For integration processing corresponding to the channel
The integration processing previously stored in the capacitor of the integration means
Switch processing for initializing the processing result; b. The channel
The previous sampler stored in the integral value storage means corresponding to
Signal of the channel in the sampling cycle and the current sample
Input analog signal of the channel in the pulling cycle
And feedback of the channel obtained from the inverse quantization means.
Switch processing for supplying an analog signal to the integration means
And c. Current sampling period obtained from the integration means
The integral signal corresponding to the channel
And a switch unit 15 for executing a switch process to be supplied to the value storage unit .

According to this analog / digital converter,
Under the time-sharing control, the integration means 11 sequentially executes the integration processing corresponding to each channel. Here, when the integration processes corresponding to a plurality of channels are sequentially executed, the integration process corresponding to one channel is interrupted by the integration process corresponding to another channel. However, in the present invention, when the integration process corresponding to a certain channel is interrupted, the integration value signal indicating the result of the integration process is stored by the integration value storage means 12, and the integration process corresponding to the channel is restarted. In this case, the integrated value signal is supplied to the integrating means 11, so that the integration process corresponding to the channel is normally executed despite the interruption.

According to a second aspect of the present invention, in the first aspect of the invention, as shown in FIG.
Are provided with at least two capacitors 12C for storing the integrated signal. In this configuration, for each channel, the switch means 15 supplies the integration value signal corresponding to the channel to the integration means from one capacitor 12C of the integration value storage means corresponding to the channel; And supplying the integrated value signal corresponding to the channel to the other capacitor 12C corresponding to the channel.

According to the present invention, there is an advantage that A / D conversion corresponding to a plurality of channels can be performed with a small number of time slots.

According to a third aspect of the present invention, in the first aspect, as shown in FIG. 3, there are provided input switched capacitor means 16, 16,... For sampling an input analog signal for each channel, An input analog signal sampled at the same timing by each input switched capacitor means is sequentially supplied to the integrating means for each channel.

According to the present invention, there is an advantage that input analog signals of a plurality of channels can be sampled at the same timing and A / D converted.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments will be described to make the present invention easier to understand. Such an embodiment shows one aspect of the present invention, and does not limit the present invention, and can be arbitrarily changed within the scope of the present invention.

A. Configuration of Embodiment FIG. 4 shows a delta-sigma type A / according to an embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a D converter. This A / D converter performs A / D conversion of input analog signals Ain1 and Ain2 of two channels in parallel. These input analog signals are balanced signals, the input analog signal Ain1 of the first channel is composed of the positive phase signal Ain1P and the negative phase signal Ain1N, and the input analog signal Ain2 of the second channel is the positive phase signal Ain2.
P and the negative-phase signal Ain2N.

The clock circuit 80 is a means for controlling the operation timing of each unit in the A / D converter, and includes clocks a, b, d, ac, b necessary for such timing control.
d, b1, d1, b2 and d2 are output. The waveforms of these clocks are shown in the timing chart of FIG.

Input switched capacitor units 11 to 14
Are means for outputting a current corresponding to the level of the input analog signal. Of the input analog signals described above, the positive-phase signal Ain1P of the first channel is supplied to the input switched capacitor unit 11, the positive-phase signal Ain2P of the second channel is supplied to the input switched capacitor unit 12, and the negative-phase signal Ain1N of the first channel. Is the input switched capacitor unit 13
The negative-phase signal Ain2N of the second channel is supplied to the input switched capacitor unit 14. The currents output from the input switched capacitor units 11 and 12 are sequentially supplied to a common signal line LP (hereinafter, referred to as a positive-phase input line LP), and output from the input switched capacitor units 13 and 14. The supplied currents are also sequentially supplied to a common signal line LN (hereinafter, referred to as a negative-phase input line LN).

The structure of each input switched capacitor unit will be described.
1 is a capacitor C1 and four analog switches S11
1 to S114.

Here, the analog switches S111 and S113 are turned on by the clock a. When these analog switches are turned on, a signal path of analog switch S111 → capacitor C1 → analog switch S113 → reference power supply Vref is formed, and the signal Ain1P is passed through this signal path.
Is stored in the capacitor C1.

The analog switches S112 and S112
114 is rendered conductive by the output of the clock b. When these analog switches are turned on, the reference power supply Vref → analog switch S
112 → capacitor C1 → analog switch S114 →
A signal path called the positive-phase input line LP is formed, and the electric charge held in the capacitor C1 is supplied to the positive-phase input line LP through this signal path.

The clocks a and b are alternately output at fixed time intervals, as shown in FIG. For this reason,
An operation in which a charge corresponding to the level of the analog signal Ain1P is held in the capacitor C1, and the charge is transferred to the positive-phase input line LP
Is repeated at regular time intervals, whereby a current corresponding to the level of the analog signal Ain1P is output to the positive-phase input line LP.

Other input sample hold circuits 12 to 14
Has the same configuration as that of the input sample and hold circuit 11, and has capacitors C11, C5, and C15 for holding electric charges corresponding to the level of the input analog signal. Also, each of the input sample hold circuits 12 to 14 is
It has four analog switches for forming a signal path for applying an input analog signal to a capacitor and a signal path for outputting a charge held in the capacitor to a positive-phase input line or a negative-phase input line. However, the two analog switches for forming the latter signal path in the input sample hold circuits 12 and 14 are made conductive by the clock d instead of the clock b.

The integrator 40 comprises a differential amplifier 41, integrating capacitors C4 and C8, and analog switches S401 and S402 for initialization. Here, the non-inverting input terminal IP of the differential amplifier 41 is connected to the in-phase input line L
P, and the inverted input terminal IN is connected to the inverted phase input line LN.
It is connected to the. Integration capacitors C4 and C8
Indicates that the non-inverting input terminal IP and the inverting output terminal of the differential amplifier 41 are ON.
And between the inverting input terminal IN and the non-inverting output terminal OP. The inverted output terminal ON and the non-inverted output terminal OP of the differential amplifier 41 are connected to signal lines MP and M, respectively.
N (hereinafter, referred to as positive-phase output line MP and negative-phase output line MN).

With the above configuration, the potentials at the non-inverting input terminal IP and the inverting input terminal IN of the differential amplifier 41 are set to the reference power source Vr
The signal input from both input terminals is integrated while maintaining the level at ef, and all charges supplied via the positive-phase input line LP are accumulated in the integrating capacitor C4, and the negative-phase input line LN is The total charge supplied through the capacitor C
8 is stored. As a result, a voltage corresponding to the integrated value is output between the inverted output terminal ON and the non-inverted output terminal OP of the differential amplifier 41. The output voltage corresponding to the integrated value is separated into a signal corresponding to the positive-phase component and a signal corresponding to the negative-phase component by the positive-phase output line MP and the negative-phase output line MN and supplied to each unit.

The initialization analog switch S401
And S402 are connected in parallel to integrating capacitors C4 and C8, respectively. These initialization analog switches S401 and S402 are made conductive by the clock ac, and the integrating capacitor C
It is used as a means for short-circuiting both ends of C4 and C8 to make the integral value zero.

The integrator 40 performs the first division under time-division control.
Channel input analog signal Ain1 (= Ain1P,
Ain1N) and the second channel input analog signal Ain2 (= Ain2P, Ain2N)
And the integration process for the target is sequentially and alternately executed. In order to enable such time-sharing control of the integration processing, the following measures are taken in the present embodiment.

A. When the integration process corresponding to the first channel (second channel) is interrupted, the integration value of the integration unit 40 is initialized to 0, and the integration unit 40 performs the integration process corresponding to the second channel (first channel). hand over. The above-described initialization analog switches S401 and S402 are means for fulfilling this role.

B. When the integration processing corresponding to the first channel (second channel) is interrupted, the integrated value obtained up to the time of the interruption is stored. Then, when restarting the integration process corresponding to the first channel (second channel), the integration value is given to the integration unit 40, and the integration process is restarted from the state at the time of interruption. The means to make this possible is shown in FIG.
Are the first integrated value storage units 21 to 24 and the second integrated value storage units 31 to 34.

These integrated value storage units are means for storing a signal representing an integrated value for each integration process corresponding to each channel performed by the integrating unit 40, and include a first integrated value storage unit 21 and a second integrated value storage unit. The unit 31 outputs a positive-phase signal corresponding to the integral value of the first channel, the first integral value storage unit 22 and the second integral value storage unit 32 outputs a positive-phase signal corresponding to the integral value of the second channel, First integral value storage unit 23 and second integral value storage unit 3
3 is a signal of the opposite phase corresponding to the integrated value of the first channel, and the first integrated value storage unit 24 and the second integrated value storage unit 34
Signals of opposite phases corresponding to the integral values of the channels are stored.

The structure of each integrated value storage unit will be described. First, the first integrated value storage unit 21 is composed of a capacitor C2 and four analog switches S211 to S214, like the above-described input switched capacitor unit. I have. Here, the analog switches S211 and S21
3 is made conductive by the application of the clock b2. When these analog switches are turned on, the positive-phase output line MP → analog switch S211
A signal path of → capacitor C2 → analog switch S213 → reference power supply Vref is formed. Then, through this signal path, a charge corresponding to the positive-phase component of the signal representing the integral value is held in the capacitor C2. Further, the analog switches S212 and S214
Are made conductive by the clock b1. By turning on these analog switches, the reference power supply Vref → analog switch S212 → capacitor C
A signal path of 2 → analog switch S214 → positive-phase input line LP is formed. Through this signal path, the charge held in the capacitor C2 is supplied to the positive-phase input line LP in a state where the polarity is inverted. As described above, the sampling of the integrated value is performed by the output of the clock b2, and the charge equivalent to the integrated value is supplied to the positive-phase input line LP in a state where the polarity is inverted by the output of the clock b1. Because

The second integral value storage section 31 has exactly the same configuration as the first integral value storage section 21 and has a capacitor C3 and four analog switches S311 to S314. However, a signal path for applying a voltage corresponding to the positive phase component of the integration value to the capacitor C3 in the second integration value storage unit 31 is formed by turning on the analog switches S311 and S313 by the clock b1. You. A signal path for supplying the electric charge held in the capacitor C3 to the positive-phase input line LP is provided by the analog switches S312 and S31 by the clock b2.
4 is formed by making it conductive.

As described above, the roles of the clocks b1 and b2 are exchanged between the first integrated value storage unit 21 and the second integrated value storage unit 31. Therefore, when the clock b2 is output, the voltage on the positive-phase output line MP is applied to the capacitor C2 of the first integrated value storage unit 21 and the second time.
The charge of the integral value 31 held in the capacitor C3 is supplied to the positive-phase input line LP. When the clock b1 is output, the voltage on the positive-phase output line MP is applied to the capacitor C3 of the second integrated value storage unit 31, and at the same time, the electric charge held in the capacitor C2 of the first integrated value 21 is changed. The signal is supplied to the positive-phase input line LP.

The other integral value storage sections are exactly the same as the first integral value storage section 21 and the second integral value storage section 31, and are constituted by one capacitor and four analog switches. . The name of each capacitor and the name of the clock for controlling the conduction of each analog switch are as shown in the figure.

The 1-bit ADC section 50 is means for quantizing the integrated value obtained from the integrating section 40, and includes two capacitors C18 and C19, six analog switches S501 to S506, a comparator 51 It consists of.

Here, the analog switches S501, S5
03, S504 and S506 are made conductive by the clock bd. When these analog switches are turned on, the positive-phase output line MP → the analog switch S501 → the capacitor C18 → the analog switch S5
03 → the signal path of the reference power supply Vref and the negative-phase output line MN → the analog switch S504 → the capacitor C19 →
A signal path from the analog switch S506 to the reference power supply Vref is formed. The voltage corresponding to the positive phase component of the integral value is applied to the capacitor C18 through the former signal path, and the voltage corresponding to the negative phase component of the integral value is applied to the capacitor C19 through the latter signal path. To be applied. Then, when the clock bd falls and the analog switches S501, S503, S504, and S506 are opened, the capacitors C18 and C19 hold the applied voltage at that time.

The analog switches S502 and S502
505 is turned on when the clock ac goes high. As a result of these analog switches being turned on, a signal path of reference power supply Vref → analog switch S502 → capacitor C18 → inverting input terminal of comparator 51 and reference power supply Vref → analog switch S504 → capacitor C19 → comparator 51 A signal path called a normal rotation input terminal is formed. Then, through these signal paths, the capacitors C18 and C1
9, the respective polarities are inverted,
It is supplied to the inverting input terminal and the non-inverting input terminal of the comparator 51, respectively.

The comparator 51 is configured by combining a normal comparator and a latch. Each time the clock ac is applied, the comparator 51 compares each input voltage at the inverting input terminal and the non-inverting input terminal at that time. Then, the result is output as a 1-bit digital signal OUT. This digital signal OUT
Is supplied to the feedback clock generator 60 and a subsequent digital filter (not shown).

The feedback clock generator 60 generates a clock ac
Captures the output digital signal of the comparator 50 in synchronization with
If this digital signal is "0", the clock bd
Outputs the clock Hbd at the timing synchronized with
If it is “1”, the clock Lbd is output at a timing synchronized with the clock bd.

The 1-bit DAC section 70 is a means for generating a feedback analog signal corresponding to the digital signal OUT, and includes capacitors C9 and C10 and analog switches S701 to S710.
Here, the analog switches S702, S703, S70
4 and S706 are made conductive by the clock ac. As a result of these analog switches being turned on, both ends of capacitor C9 are connected to reference power supply Vref, and capacitor C10 is connected between reference power supply Vref and the ground line. Therefore, once the clock ac is generated, the capacitor C9 holds 0 V and the capacitor C10 holds the voltage Vref.
The analog switches S701 and S705 are turned on by the clock bd. As a result, one end of the capacitor C9 is grounded, and 0 V is output from the other end of the capacitor C9. Further, since one end of the capacitor C10 is connected to the reference power supply Vref, the capacitor C9
Outputs a voltage of 2 Vref.

The analog switches S707 to S710 are
The capacitors C9 and C10 thus output
Are supplied to the positive-phase input line LP and the negative-phase input line LN as analog feedback signals, and the clock Hbd or Lbd generated by the feedback clock generation unit 60 is provided.
Is brought into a conductive state. First, the analog switch S
707 and S710 are turned on by the clock Hbd. When these analog switches are turned on, the output voltage of the capacitor C9 (= 0V) is applied to the positive-phase input line LP to output the voltage of the capacitor C10 (= 2V).
ref) are supplied to the negative-phase input lines LN, respectively. The analog switches S708 and S709 are connected to the clock L
The conductive state is established by bd. When these analog switches are turned on, the output voltage (= 0V) of capacitor C9 is supplied to negative-phase input line LN, and the output voltage (= 2Vref) of capacitor C10 is supplied to positive-phase input line LP.

B. Operation of Embodiment Next, the operation of this embodiment will be described with reference to the timing chart of FIG. In the present embodiment, two channels of analog signals are sampled at every fixed sampling period TS, and each is converted into a digital signal. A series of processing for the A / D conversion is sequentially performed in units of time slots obtained by dividing each sampling period into four. Focusing on the content of processing performed in each time slot,
The same processing is repeated with eight consecutive time slots, that is, two periods of time 2TS converted into a sampling period as one unit. Therefore, in the following, a period consisting of two consecutive sampling periods TS _i and TS _{i + 1} is assumed, and the operation of the present embodiment performed in each of the time slots SL1 to SL8 obtained by dividing this period into eight will be sequentially described. .

[0039] (1) in the time slot SL1 of the time slots SL1 sampling period TS _i, only the clock a and ac are outputted, the other clock is not output. For this reason, the state of each analog switch is as shown in FIG.
The following operations are performed in each unit.

Input switched capacitor units 11 to 14
, The input analog signals Ain1P, Ain2
P, Ain1N, and Ain2N are sampled, and electric charges corresponding to the levels of the respective analog signals are held in the capacitors C1, C11, C5, and C15, respectively.

In the integration section 40, both ends of each of the capacitors C4 and C8 are short-circuited by the analog switch for initialization, and the integration value of the integration section 40 becomes zero.

In 1-bit ADC section 50, the holding voltage of each of capacitors C18 and C19 is applied to comparator 5
1 are input to the inverting input terminal and the non-inverting input terminal, respectively, and each input voltage is compared. The holding voltage of each of these capacitors is determined by the integration unit 40 in the sampling period TS _i-1 .
, And corresponds to the integral value corresponding to the second channel. When the clock ac is output, a digital signal OUT representing the result of the comparison is output.

Here, the integration value of the second channel obtained from the integration section 40 in the sampling period TS _i-1 is positive, a positive voltage is applied to the capacitor C18, and the capacitor C19
When the negative voltage is held in the comparator 51, the input voltage to the inverting input terminal of the comparator 51 becomes lower than the input voltage to the non-inverting input terminal. As a result, “1” (high level) is output from the comparator 51 as the digital signal OUT.
On the other hand, if the integration value corresponding to the first channel obtained from the integration unit 40 one sampling cycle before is negative, the input voltage to the inverting input terminal of the comparator 51 is higher than the input voltage to the non-inverting input terminal. Digital signal OU
“0” (low level) is output as T. The digital signal output from the comparator 51 in this manner is transmitted in a time slot SL3 two time slots later.
The clock ac is taken into the feedback clock generator 60.

Before the digital signal of the second channel is output, the digital signal of the first channel is output.
This digital signal of the first channel is represented by a time slot S
In L1, the feedback clock generator 6 is operated by the clock ac.
It is taken in 0.

In 1-bit DAC unit 70, a voltage of 0 V is held by capacitor C9, and
The voltage Vref is held by 0.

(2) Time slot SL2 In this time slot SL2, clocks b and b
Only d and b1 are output, and no other clocks are output. Therefore, the state of each analog switch is as shown in FIG. 7 by the output of the clock, and the following operations are performed in each unit.

In input switched capacitor sections 11 and 13 corresponding to the first channel, capacitors C
The charges held at 1 and C5 are supplied to the positive-phase input line LP and the negative-phase input line LN, respectively, in a state where the polarities are inverted.

The feedback clock generator 60 outputs one of the clocks Hbd and Lbd at a timing synchronized with the clock bd. Which clock is output is determined by the value of the digital signal OUT corresponding to the first channel captured in the feedback clock generator 60 in the time slot SL1, and when OUT = "0" Has a clock Hbd,
When OUT = "1", the clock Lbd is output.

In 1-bit DAC unit 70, analog switches S707 and S70 are output from capacitor C9.
9, a voltage of 0 V is output, and a voltage of 2 Vref is output from the capacitor C10 to the analog switches S708 and S710. And the sampling period T
If “0” is output as the digital signal OUT of the first channel in S _i−1 , the time slot S
The clock Hbd is output at L2. Therefore, the voltage 0V is applied to the positive-phase input line LP via the analog switch S707, and the voltage 2Vref is applied to the analog switch S707.
710 to the negative-phase input line LN. On the other hand, when “1” is output as the digital signal of the first channel in the sampling cycle TS _i−1 , the clock Lb
d is output. Accordingly, the analog switches S708 and S709 are turned on, and a voltage of 2 Vref is applied to the positive-phase input line LP and a voltage of 0 V is applied to the negative-phase input line LN.

In the first integrated value storage units 21 and 23, the electric charges held in the capacitors C2 and C6 are supplied to the positive-phase input line LP and the negative-phase input line LN. The charge held by each of these capacitors is determined by the sampling period TS
_{The value i-1} is given from the integration unit 40, and corresponds to the integration value corresponding to the first channel.

In the integrator 40, since the initialization analog switches S401 and S402 are open, the integration of the above-mentioned signals supplied through the positive-phase input line LP and the negative-phase input line LN is performed. Is performed. As a result, the _first in the sampling cycle TS _i- 1
Adds the input analog signal of the first channel taken in the integration value and the time slot SL1 corresponding to the channel, obtained by subtracting the feedback analog signal from the added result corresponding to the first channel in the current sampling period TS _i A voltage corresponding to the integrated value is output from the differential amplifier 41 to the positive-phase output line MP and the negative-phase output line MN.

In the second integrated value storage units 31 and 33, an operation of holding a voltage corresponding to the integrated value corresponding to the first channel obtained as described above is performed. That is, since a signal path from the positive-phase output line MP to the reference power supply Vref via the capacitor C3 is formed, the electric charge corresponding to the positive-phase component of the integrated value is held by the capacitor C3 via this signal path. You. Further, since a signal path from the negative-phase output line MN to the reference power supply Vref via the capacitor C7 is formed, electric charge corresponding to the negative-phase component of the integrated value is generated through the signal path.
7 will be held.

In the 1-bit ADC unit 50, the reference power supply Vr is supplied from the positive-phase output line MP via the capacitor C18.
A signal path extending from the negative-phase output line MN to the reference power supply Vref via the capacitor C19 is formed. As a result, a voltage corresponding to the positive-phase component of the integration value obtained by the integration section 40 is stored in the capacitor C18, and a voltage corresponding to the negative-phase component is stored in the capacitor C19.

(3) Time Slot SL3 In this time slot SL3, only the clock ac is output, and no other clock is output. For this reason, the state of each analog switch is as shown in FIG. 8 by the output of the clock, and the following operations are performed in each unit.

In the 1-bit ADC section 50, similarly to the above-described time slot SL1, the operation of supplying the respective voltages held in the capacitors C18 and C19 to the inverting input terminal and the non-inverting input terminal of the comparator 51 is performed. In this case, each input voltage to the comparator 51 is obtained by inverting the polarity of each voltage corresponding to the integrated value of the first channel held in each capacitor in the time slot SL2. Therefore, when the integral value of the first channel obtained in the time slot SL2 is positive, the comparator 5
A 1- to 1-bit digital signal "1" (high level) is output, and if negative, a digital signal "0" (low level) is output. The digital signal OUT of the first channel output from the comparator 51 in this manner is taken into the feedback clock generator 60 by the clock ac generated in the time slot SL5.

The digital signal of the second channel, which was output before the digital signal of the first channel was output, is taken into the feedback clock generator 60 by the clock ac.

In the integration section 40, the initialization analog switches S401 and S402 are turned on, so that the integration value becomes zero.

In the 1-bit DAC unit 70, the voltage across the capacitor C9 is set to 0 V, and
The voltage across zero is set to Vref. In the second integrated value storage units 31 and 33, all analog switches are opened. Therefore, the capacitors C3 and C7 maintain the charge given in the time slot SL2 as it is.

(4) Time slot SL4 In this time slot SL4, clocks d and b
Only d and d1 are output, and no other clocks are output. Therefore, the state of each analog switch is as shown in FIG. 9 by the output of the clock, and the following operations are performed in each unit.

In input switched capacitor sections 12 and 14 corresponding to the second channel, capacitors C
The charges held in C11 and C15 are supplied to the positive-phase input line LP and the negative-phase input line LN, respectively, with their polarities inverted.

The feedback clock generator 60 outputs either the clock Hbd or Lbd at a timing synchronized with the clock bd. That is, when the digital signal corresponding to the second channel captured in the feedback clock generator 60 in the immediately preceding time slot SL3 is “0”, the clock Hbd is output,
When it is “1”, the clock Lbd is output.

The 1-bit DAC 70 generates a feedback analog signal corresponding to the digital signal of the second channel based on the clock Hbd or Lbd.
It is provided to the positive phase input line LP and the negative phase input line LN. Note that the details of this operation are the same as those already described for the time slot SL2, and a description thereof will be omitted.

In the first integrated value storage sections 22 and 24, the electric charges held in the capacitors C12 and C16 are supplied to the positive-phase input line LP and the negative-phase input line LN, respectively, with their polarities inverted. The electric charge held in each of these capacitors corresponds to an integral value corresponding to the second channel in the sampling period TS _i-1 .

In the integrator 40, the positive-phase input line LP
The integration of each signal supplied via the negative-phase input line LN is performed. As a result, the integrated value corresponding to the second channel in the sampling period TS _i-1 is added to the input analog signal of the second channel captured in the time slot SL1, and the result obtained by subtracting the feedback analog signal from the addition result is obtained. obtained as an integral value corresponding to a second channel in the sampling period TS _i, the voltage corresponding to the integrated value is output from the differential amplifier 41 to the positive-phase output lines MP and the negative phase output line MN.

In the second integrated value storage units 32 and 34, the electric charge corresponding to the integrated value corresponding to the second channel obtained as described above is stored in the capacitors C13 and C1.
7 is performed.

The voltage corresponding to the positive-phase component and the voltage corresponding to the negative-phase component of the integral value of the second channel are supplied from the integrator 40 to the 1-bit ADC 50. These voltages are held in capacitors C18 and C19 in 1-bit ADC unit 50.

(5) Time slot SL5 In the time slot SL5 of the sampling period TS _{i + 1} , only the clocks a and ac are output and no other clocks are output, as in the time slot SL1 described above. Therefore, the state of each analog switch is as shown in FIG. 10 by the output of the clock, and the following operations are performed in each unit.

Input switched capacitor sections 11 to 14
, The input analog signals Ain1P, Ain1
2P, Ain1N, and Ain2N are sampled, and charges corresponding to the levels of the respective analog signals are held in the capacitors C1, C11, C5, and C15, respectively.

In the integrating section 40, both ends of each of the capacitors C4 and C8 are short-circuited by the analog switch for initialization, and the integrated value of the integrating section 40 becomes zero.

In the 1-bit ADC section 50, the voltages held in the capacitors C18 and C19 are input to the inverting input terminal and the non-inverting input terminal of the comparator 51, respectively, with the polarities inverted. These voltage held in each capacitor has been obtained from the integrating portion 40 in the time slot SL4 of the sampling period TS _i, which corresponds to the integral value corresponding to the second channel. Then, when the clock ac is output, the digital signal OUT of the second channel representing the result of the comparison is output from the comparator 51.

The digital signal of the first channel, which was output before the digital signal of the second channel was output, is taken into the feedback clock generator 60 by the clock ac.

In 1-bit DAC section 70, voltage 0V is held by capacitor C9, and capacitor C1
The voltage Vref is held by 0.

(6) Time Slot SL6 In this time slot SL6, clocks b and b
Only d and b2 are output, and no other clocks are output. Therefore, the state of each analog switch is as shown in FIG. 11 by the output of the clock, and the following operations are performed in each unit.

In input switched capacitor sections 11 and 13 corresponding to the first channel, capacitors C
1 and C5 are output with their polarities inverted, and the positive-phase input line LP and the negative-phase input line L
N.

The feedback clock generator 60 outputs one of the clocks Hbd and Lbd at a timing synchronized with the clock bd. Which clock is output is determined by the value of the digital signal OUT corresponding to the first channel captured in the time slot SL5. When OUT = "0", the clock Hbd is set to OUT If "1", the clock Lbd is output.

[0076] In the 1-bit DAC portion 70, based on the clock Hbd or Lbd, a feedback analog signal corresponding to the digital signal of the first channel is generated in the sampling period TS _i, the positive phase input line LP and the negative phase input Applied to line LN.

In the second integrated value storage units 31 and 33, the charges held in the capacitors C3 and C7 are inverted in polarity, respectively, so that the positive phase input line LP and the negative phase input line L
N. Electric charges held in each of these capacitors are those given from the integrating portion 40 in the sampling period TS _i, which corresponds to the integral value corresponding to the first channel in the sampling period TS _i.

In the integration section 40, since the initialization analog switches S401 and S402 are open, the signals supplied via the positive-phase input line LP and the negative-phase input line LN are integrated. . As a result, it adds the input analog signal of the first channel taken in the integration value and the time slot SL5 corresponding to the first channel in the sampling period TS _i, obtained by subtracting the feedback analog signal from the added result is the current sampling An integrated value corresponding to the first channel in the cycle TS _{i + 1} is obtained, and a voltage corresponding to this integrated value is output from the differential amplifier 41 to the positive-phase output line MN and the negative-phase output line MN.

In the first integral value storage units 21 and 23, an operation of holding a voltage corresponding to the integral value corresponding to the first channel obtained as described above is performed.

In 1-bit ADC section 50, the voltage corresponding to the positive phase component of the integrated value of the first channel obtained by integration section 40 is held in capacitor C18, and the voltage corresponding to the negative phase component is held in capacitor C19. Is done.

[0081] contents of processing in the time slot SL6 as described above, the sampling period TS _i is a processing content and substantially the same in the time slot SL2, the first integration value storage unit 21 and a 23 second integration value storage The only difference is that the roles played by the parts 31 and 33 are interchanged.

(7) Time slot SL7 In this time slot SL7, only the clock ac is output, similarly to the time slot SL3 described above.
No other clock is output. Therefore, the state of each analog switch is as shown in FIG. 12 by the output of the clock, and the following operations are performed in each unit.

In the 1-bit ADC section 50, the voltages held in the capacitors C18 and C19 are inverted in polarity and input to the inverting input terminal and the non-inverting input terminal of the comparator 51. Be compared. Each voltage held in each of these capacitors is provided from the integrator 40 in the time slot SL6, and corresponds to an integrated value of the first channel. When the clock ac is supplied, a digital signal of the first channel representing the result of the comparison is output.

The digital signal of the second channel output before the output of the digital signal of the first channel is taken into the feedback clock generator 60 by the clock ac.

In the integrating section 40, since the analog switches for initialization S401 and S402 are turned on, the integrated value becomes zero.

In the 1-bit DAC unit 70, the voltage across the capacitor C9 is set to 0 V,
The voltage across zero is set to Vref.

In the first integrated value storage units 21 and 23, all analog switches are opened.
Therefore, the capacitors C2 and C6 maintain the charge given in the time slot SL6 as it is.

(8) Time slot SL8 In this time slot SL8, clocks d and b
Only d and d2 are output, and no other clocks are output. For this reason, as shown in FIG.
The analog switch to which d or d2 is applied is made conductive, and the other analog switches are made open. As a result, the following operation is performed in each unit.

In input switched capacitor sections 12 and 14 corresponding to the second channel, capacitors C
The charges held in C11 and C15 are output with their polarities inverted, and supplied to the positive-phase input line LP and the negative-phase input line LN.

In the feedback clock generator 60, either the clock Hbd or Lbd is output at a timing synchronized with the clock bd. That is, when the digital signal corresponding to the second channel captured in the feedback clock generation unit 60 in the immediately preceding time slot SL7 is “0”, the clock Hbd is output,
When it is “1”, the clock Lbd is output.

In the 1-bit DAC unit 70, the second
A feedback analog signal corresponding to the digital signal of the channel is generated and supplied to the positive-phase input line LP and the negative-phase input line LN.

In the second integrated value storage units 32 and 34, the electric charges held in the capacitors C13 and C17 are supplied to the positive-phase input line LP and the negative-phase input line LN, respectively, with their polarities inverted. Electric charges held in each of these capacitors is equivalent to the integral value corresponding to a second channel in the sampling period TS _i.

In the integration section 40, since the initialization analog switches S401 and S402 are open, the signals supplied via the positive-phase input line LP and the negative-phase input line LN are integrated. As a result, the integral value corresponding to a second channel in the sampling period TS _i, adds the input analog signal of the second channel taken in the time slot SL5, the sampling period obtained by subtracting the feedback analog signal from the added result T
An integrated value corresponding to the second channel at S _{i + 1} is obtained, and a voltage corresponding to the integrated value is output from the differential amplifier 41 to the positive-phase output line MP and the negative-phase output line MN.

In the first integral value storage units 22 and 24, the electric charge corresponding to the integral value corresponding to the second channel obtained as described above is stored in the capacitors C12 and C1.
6 is performed.

The voltage corresponding to the positive-phase component and the voltage corresponding to the negative-phase component of the integral value of the second channel are supplied from the integrator 40 to the 1-bit ADC 50. These voltages are held in capacitors C18 and C19 in 1-bit ADC unit 50. When the sampling cycle is switched and the time slot SL1 is reached again, the held voltage is applied to the comparator 51, and the digital signal of the second channel is output.

As described above, the processing content in the time slot SL8 is substantially the same as the processing content in the time slot SL4, and the first integrated value storage units 22 and 24 and the second integrated value storage units 32 and 34 Only the roles to be fulfilled have been interchanged.

Thereafter, similarly, time slots SL1 to SL
8 are repeatedly executed, and A / D conversion of each input analog signal of the first channel and the second channel is performed.

C. Other Embodiments In addition to the above-described embodiments, various embodiments can be considered. For example:

(1) In the above embodiment, the analog signal is a balanced signal, and the integration of the analog signal is performed by the integrator constituted by the differential amplifier. You may make it integrate with an integrator.

(2) In the above embodiment, the analog signals of the first and second channels are simultaneously sampled by the input switched capacitor unit. However, the sampling timing may be shifted between the channels.

(3) It is only necessary that the integrator is configured to perform the integration process corresponding to the first channel and the integration process corresponding to the second channel in the respective defined time slots, and this operation is guaranteed. As long as there is, the input forms of the analog signals of the first channel and the second channel can be variously changed.

(4) Only one integrated value storage section is provided for each channel, and after the integration processing by the integration section is completed using the charge held in the integrated value storage section, the integrated value corresponds to a new integrated value. The charge may be held in the integrated value storage unit.
A time slot for holding the charge corresponding to the integral value must be provided separately from the time slot for performing the integration process, but there is an advantage that the number of integral value storage units can be reduced by half.

(5) In the above-described embodiment, an example in which analog signals of two channels are handled has been described. However, when analog signals of a greater number of channels are handled, an input switched capacitor unit and an integrated value corresponding to the number of channels are used. A storage unit may be provided, and time slots may be provided as needed for processing of each channel.

(6) In the above embodiment, an example in which two-channel analog signals supplied from the outside are handled has been described. However, an analog signal generated inside the A / D converter is input via the input switched capacitor unit. You may make it input. For example, the analog signal output to the positive-phase output line MP and the negative-phase output line MN by the integrator 40 is configured to be re-input via the input switched capacitor unit, and the input analog signal is integrated twice. The following delta-sigma modulation may be performed. The same applies to the case where third-order or higher delta-sigma modulation is performed.

[0105]

As described above, according to the present invention, the integration processing corresponding to a plurality of channels can be sequentially executed by one integration means under the time division control. A that can process multiple channels
There is an effect that a / D converter can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of the invention according to claim 1;

FIG. 2 is a diagram showing a configuration of the invention according to claim 2;

FIG. 3 is a diagram showing a configuration of the invention according to claim 3;

FIG. 4 is a block diagram illustrating a configuration of an A / D converter according to an embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the embodiment.

FIG. 6 is a diagram showing an operation state of the embodiment.

FIG. 7 is a diagram showing an operation state of the embodiment.

FIG. 8 is a diagram showing an operation state of the embodiment.

FIG. 9 is a diagram showing an operation state of the embodiment.

FIG. 10 is a diagram showing an operation state of the embodiment.

FIG. 11 is a diagram showing an operation state of the embodiment.

FIG. 12 is a diagram showing an operation state of the embodiment.

FIG. 13 is a diagram showing an operation state of the embodiment.

FIG. 14 is a block diagram showing a configuration of a conventional delta-sigma modulation A / D converter.

FIG. 15 is a block diagram showing a configuration of a conventional delta-sigma modulation type A / D converter.

FIG. 16 is a block diagram showing a configuration of a conventional delta-sigma modulation type A / D converter.

[Explanation of symbols]

11 integration means, 12, 12, ... integration value storage means, 13 quantization means, 14 inverse quantization means, 15
...... Switch means.

Continuation of the front page (56) References JP-A-6-13906 (JP, A) JP-A-49-79452 (JP, A) JP-A-6-209266 (JP, A) JP-A-3-60527 (JP) , A) “Oversampling A / D conversion technology”, Yukawa, 1990.12, published by Nikkei BP p. 52 (58) Fields studied (Int. Cl. ⁷ , DB name) H03M 3/02

Claims (5)

(57) [Claims] 1. An analog / digital converter for sequentially converting input analog signals of a plurality of channels into digital signals by time division control, wherein the input analog signals are stored in a capacitor.
More, an integrating means for sequentially executing the integration process corresponding to each channel, and a plurality of integral value storage means for storing the integrated value signal indicative of the result of the integration process corresponding to each channel for each channel, each channel Quantizing means for sequentially outputting digital signals corresponding to the respective channels by quantizing the result of the integration processing corresponding to the following; dequantizing means for converting the digital signals into feedback analog signals; and an input for each of the channels. Analog signal to digital signal
For each sampling cycle for conversion,
And a. Prior to the integration process corresponding to the channel,
Initialize the integration processing result stored in the capacitor of the dividing means
Switch processing, and b. Stored in the integrated value storage means corresponding to the channel
Of the channel in the previous sampling period
Value signal and the current channel
An input analog signal and a signal obtained from the inverse quantization means.
Supplying the feedback analog signal of the channel to the integration means
Switch processing to perform c. In the current sampling period obtained from the integrating means,
The integrated signal corresponding to the channel.
And a switch unit for executing a switch process for supplying to the storage unit . 2. The integrated value storage means has at least two capacitors for storing the integrated value signal, and the switch means stores, for each channel, an integrated value signal corresponding to the channel in the channel. A process of supplying from the one capacitor of the corresponding integration value storage means to the integration means, and a processing of supplying the integration value signal corresponding to the channel obtained from the integration means to the other capacitor of the integration value storage means corresponding to the channel; 2. The analog-to-digital converter according to claim 1, wherein the processing for supplying to the analog / digital converter is performed simultaneously. 3. An input switched capacitor means for sampling an input analog signal for each channel, wherein the input analog signal sampled at the same timing by each input switched capacitor means is supplied to the integration means for each channel. 2. The analog / digital converter according to claim 1, wherein the analog / digital converter is supplied sequentially. 4. An input analyzer for each of first and second channels.
Log signals are sequentially converted to digital signals by time division control
2. The digital / analog converter according to claim 1,
The input analog signals of the first and second channels
Holding the input switched capacitor means, wherein the quantizing means and the inverse quantizing means correspond to each other.
Means for holding an input signal, the input switched capacitor means,
Stage, the quantization means and the inverse quantization means,
Digital input analog signal of each of first and second channels
Divided into four sampling periods for converting
It operates in synchronization with the first to fourth time slots.
Ri, a. In a first time slot, the input switched capacitor means comprises first and second
Holding the input analog signals of the two channels, and the switch means stores the analog signals in a capacitor of the integration means.
Initialize the accumulated integration processing result, and the quantization means performs
Quantizing the integral value of the second channel of the sampling period
Outputting a digital signal of the second channel, wherein the inverse quantizing means has provided the quantizing means by that time.
The first channel in the previous sampling cycle output from
Holding the digital signal of the channel; b. In the second time slot, the inverse quantization means may perform the processing in the first time slot.
1st channel in previous sampling cycle
Inversely quantizes the digital signal of
Outputting a log signal, wherein said switch means comprises said input switched capacitor.
Input analog signal of the first channel held by the means
In the integrated value storage means corresponding to the first channel.
The product of the first channel in the remembered previous sampling period
And a first channel output from the inverse quantization means.
The feedback analog signal of the
As a result, the integrated value signal of the first channel obtained from the integrating means is obtained.
Signal to the integral value storage means corresponding to the first channel.
And the quantization means outputs the first signal output from the integration means.
Holding the integral signal of the channel of c. In a third time slot, the quantizing means may determine that the second time slot
The integrated value signal of the first channel held and quantized is
Digital signal of the first channel in the sampling period
Signal, and the inverse quantization means determines whether the quantization means
The second channel in the previous sampling cycle
Holding the digital signal of the channel, and the switch means accumulates in a capacitor of the integrating means.
Initializes the integration result obtained, d. In the fourth time slot, the dequantizing means performs the processing in the third time slot.
The second channel in the previous sampling cycle
Dequantizes the digital signal of the
Outputting an analog signal, wherein the switch means includes the input switched capacitor;
Input analog signal of the second channel held by the means
In the integrated value storage means corresponding to the second channel.
Of the second channel in the remembered previous sampling period
An integrated value signal and a second signal output from the inverse quantization means.
Supply the feedback analog signal of the channel to the integration means
As a result, the current sampling rate obtained from the integrating means is obtained.
The integration value signal of the second channel in the
The integrated value is supplied to the integrated value storage means corresponding to the channel .
Characterized by holding the integral signal of the channel
Analog / digital converter. 5. An input analyzer for each of first and second channels.
Log signals are sequentially converted to digital signals by time division control
2. The digital / analog converter according to claim 1,
The input analog signals of the first and second channels
Having an input switched capacitor means for holding, and storing the respective integral values corresponding to the first and second channels
Means each include a capacity for storing the integrated value signal.
And at least two of the quantization means and the inverse quantization means
Means for holding an input signal, the input switched capacitor means,
Stage, the quantization means and the inverse quantization means,
Digital input analog signal of each of first and second channels
Divided into four sampling periods for converting
It operates in synchronization with the first to fourth time slots.
Ri, a. In a first time slot, the input switched capacitor means comprises first and second
Holding the input analog signals of the two channels, and the switch means stores the analog signals in a capacitor of the integration means.
Initialize the accumulated integration processing result, and the quantization means performs
Quantizing the integral value of the second channel of the sampling period
Outputting a digital signal of the second channel, wherein the inverse quantizing means has provided the quantizing means by that time.
The first channel in the previous sampling cycle output from
Holding the digital signal of the channel; b. In the second time slot, the inverse quantization means may perform the processing in the first time slot.
1st channel in previous sampling cycle
Inversely quantizes the digital signal of
Outputting a log signal, wherein said switch means comprises said input switched capacitor.
Input analog signal of the first channel held by the means
And the integrated value storage means corresponding to the first channel .
Before being stored in one of the capacitors
The integrated value of the first channel in the sampling cycle
The feedback channel of the first channel output from the inverse quantization means
Supplying the analog signal to the integrating means, and
Means for obtaining a first channel integrated value signal obtained from the first means.
Each capacitor in the integral value storage means corresponding to the channel
The first channel in the previous sampling cycle
To the capacitor for which the integrated value of the channel was not stored.
And the quantization means outputs the first signal output from the integration means.
Holding the integral signal of the channel of c. In a third time slot, the quantizing means may determine that the second time slot
The integrated value signal of the first channel held and quantized is
Digital signal of the first channel in the sampling period
Signal, and the inverse quantization means determines whether the quantization means
The second channel in the previous sampling cycle
Holding the digital signal of the channel, and the switch means accumulates in a capacitor of the integrating means.
Initializes the integration result obtained, d. In the fourth time slot, the dequantizing means performs the processing in the third time slot.
The second channel in the previous sampling cycle
Dequantizes the digital signal of the
Outputting an analog signal, wherein the switch means includes the input switched capacitor;
Input analog signal of the second channel held by the means
And the integrated value storage means corresponding to the second channel.
Before being stored in one of the capacitors
Integrated value signal of second channel in sampling period
And the second channel output from the inverse quantization means.
The feedback analog signal is supplied to the integration means, and the
As a result, in the current sampling period obtained from the integrating means,
The integrated signal of the second channel to the second channel.
Corresponding one of the capacitors in the integrated value storage means.
Integration of the second channel in the previous sampling period
The value is supplied to the capacitor whose value has not been stored .
Characterized by holding the integral signal of the channel
Analog / digital converter.