JP3019864B2 - Memory controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device used for, for example, converting the speed of data using a memory between an image scanner and a host computer.

2. Description of the Related Art As shown in FIG. 4, for example, a conventional device of this type includes a write address generation circuit 2 of a memory 1, a read address generation circuit 3 of a memory 1, and a read / write operation of the memory 1. Memory control circuit 4 for controlling the
CPU5 (Central Processing Unit) and ROM6 to manage the storage area of
And a numeric keypad 7 for designating the size of data to be written in advance. The operation of writing data Din newly input from the image scanner 10 via the amplifier 11 and the AD converter 12 and the operation of writing already written data The reading speed of the image scanner 10 and the processing speed of the host computer 20 are matched by independently performing operations of reading data and outputting the data to the host computer 20 (for example, see JP-A-62-208756 and JP-A-63-136395).

In this case, in the above-described conventional apparatus, as shown in FIG. 5, if the designated size MS of the data Din to be written is smaller than the free space size ME in the memory 1, the designated size MS is immediately used. The data Din is read by the image scanner 10 and the amplifier 11 and the AD converter 12 are read.
Can be written to the memory 1 via the.

However, as shown in FIG. 6, when the size MS of the data Din to be written from now on is larger than the size ME of the free area in the memory 1, the data from the exclusive area (shaded area) in which the data has already been written. It is necessary to read only the data and wait until a free area having a size equal to or larger than the designated size MS is generated by the reading.

In FIGS. 5 and 6, MF is the size of the entire storage area of the memory 1, and MS is the data to be written.
The designated size of Din, ME indicates the size of a free area in which data Din can be newly written, and MR indicates the size of a dedicated area in which new data cannot be written because unread data has been written.

However, according to such a configuration, the use efficiency of the memory is not always high, and when the size of data to be newly written is large, the waiting time until the writing is started increases. There was a problem.

 The above problem occurs for the following reasons.

That is, if there is no free area larger than the size of the data at the time of writing data to the memory, it is necessary to wait until a free area larger than the size of the data is generated. Therefore, if the size of data to be written is large, the waiting time due to the lack of the size of the free area increases.

In order to reduce the waiting time, it is sufficient to provide a sufficient space in the memory so that a free area larger than the size of the data to be written is easily created with a high probability. Memory utilization efficiency decreases.

The present invention has been made in view of the above problems, and has as its object to improve the operability of a user by effectively using a memory.

Means for Solving the Problems In order to solve the above problems, the present invention provides a storage means for storing information, an input means for inputting the information to the storage means, and the information stored in the storage means. Output means for calculating the input time until the input of the information is completed, and calculating means for calculating the total free space of the storage means when the output means outputs the information during the input time, When the total free capacity is equal to or larger than the capacity of the information to be input, a control means for starting the input of the information by the input means is provided.

Operation The present invention calculates the input time until the input of information is completed, calculates the total free capacity of the storage means when the output means outputs the information during the input time, and calculates the total free space. If the capacity is larger than the information you enter,
Since the input of information is started, the waiting time until the input can be shortened.Also, since there is no shortage of free space after the input is started, continuous input processing is performed. Can be performed, and the utilization efficiency of the storage capacity can be improved.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a schematic configuration of a memory control device according to an embodiment of the present invention, wherein 1 is a memory for performing data rate conversion between an image scanner 10 and a host computer 20, and 2 is a memory 1 for writing data. Address generation circuit, 3
Is a read address generation circuit of the memory 1, and 4 is a memory 1
A memory control circuit for controlling the read / write operation of the memory; 50 and 60, a CPU (Central Processing Unit) and ROM for managing the storage area of the memory 1; 7, a numeric keypad for specifying in advance the size of data to be written; Reference numeral 8 denotes an operation unit that predicts and calculates a free area of the memory 1.

Here, prior to newly writing the data whose size is specified by the numeric keypad 7, the arithmetic unit 8 determines whether or not an empty area of a size required for writing the data is generated by the time the writing is completed. Is calculated. This operation unit 8
Can be constituted by a dedicated arithmetic processor or a ROM storing an arithmetic table.

The CPU 50, at the time when it is predicted that a free area of a required size will be generated by the time the writing of the data is completed as a result of the prediction calculation, regardless of the size of the free area at the time of starting the writing, A control function for starting data writing is added.

(A) and (b) of FIG. 2 are graphs each showing an example of the prediction calculation.

In this figure, the horizontal axis represents the elapsed time for the origin writing start time point of the data, and the vertical axis address memory, Yw change prediction curve of the write address, yR change prediction curve read address, t _w is written The read end predicted time and tR indicate the read end predicted time, respectively.

Whether or not a free area of the size required for writing data will be created by the time the writing is completed depends on the predicted write end time.
At tw, it can be predicted by whether the write address overtakes the read address. Write prediction end time
The write address and read address at tw can be calculated from the write address and read address at the start of writing, the write speed and read speed, the size of the write data, and the size of the read data.

In the example shown in FIG. 7A, the write address starting from L1 reaches L3 at the predicted write end time tw, during which the read address starts from L2 and exceeds L3. Therefore, the write address cannot keep up with the read address.
Thus, even when there is no free area of a size necessary for writing at the start of writing, a free area of a necessary size is secured by the time of completion of writing.

In the example shown in FIG. 9B, the write address starting from L1 reaches L3 at the predicted write end time tw, while the read address starts from L2 and reaches L4.
Therefore, the write address cannot keep up with the read address. Thus, even in this case, even when there is no free area of a size necessary for writing at the start of writing, a free area of a necessary size is secured by the time the writing is completed.

Regarding the memory control device configured as described above,
The operation will be described below.

3 (a) to 3 (d) show the transition of the storage contents of the memory 1 in a stepwise manner as data is written.

In the figure, MF is the entire storage area of the memory 1, MR is a dedicated area in which unread data is written and cannot be written, ME is a free area where data can be read and written, and MS is The size of the input data Din to be written to the memory 1 is shown below.

First, as shown in FIG. 3A, when the size MS of the data Din to be written is larger than the free area size ME, the free space of the size required for writing the data Din is written prior to writing the data Din. A prediction calculation is performed to determine whether an area will be created by the time the writing is completed. As a result of the prediction calculation, if it is predicted that an empty area of a required size will be generated by the time the writing of the data Din is completed, as shown in FIGS. Execute writing.

When the writing is executed, the operation of writing the input data Din to the free area and the operation of reading and outputting the data Dout from the exclusive area are performed in parallel as shown in FIGS. Done. The exclusive area is sequentially vacated as the data Dout is read. Data Din that cannot be completely written to the first free area is written to the free area that has been shifted from the exclusive area.

As described above, even when there is no free area of the required size at the start of writing of the input data Din, the writing can be started at the time when a free area of the required size is expected by the time the writing is completed. . As a result, large-sized data can be written to the memory with a short waiting time without lowering the use efficiency of the memory.

As is clear from the above description, even when the amount of information to be written is larger than the writable capacity, the present invention anticipates the free space at the end of writing from the free space generated by reading information, and Writing is started when it is determined that there is sufficient free space by the time of termination, so that writing can be performed even if there is not enough free space at the time of writing. For this reason, the waiting time until writing can be shortened, so that the operability of the user can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a memory control device according to an embodiment of the present invention, FIG. 2 is a graph showing an example of a prediction calculation performed in the device, and FIG. 3 is a storage state of a memory controlled by the device. FIG. 4 is a schematic configuration diagram of a conventional memory control device, FIG. 5 is a diagram showing a state in which data can be written by the device, and FIG. It is a figure which shows the waiting state which cannot be performed. 1 ... memory, 2 ... write address generation circuit, 3 ...
Read address generation circuit, 4 ... Memory control circuit, 50 ...
... CPU, 60, ROM, 7, numeric keypad, 8, arithmetic unit for predicting and calculating the occurrence of an empty area, 10, image scanner, 11
…… Amplifier, 12 …… AD converter, 20 …… Host computer, Din …… Input data written to empty area, Dout
…… Output data read from exclusive area, MS …… Size of input data, MF …… All storage area of memory 1, ME…
... size of free area, MR ... size of private area that cannot be written.

Continuation of the front page (56) References JP-A-62-176372 (JP, A) JP-A-61-200766 (JP, A) JP-A-58-139568 (JP, A) JP-A-64-13865 (JP) , A) JP-A-63-178649 (JP, A)

Claims (1)

(57) [Claims] A storage means for storing information; an input means for inputting the information to the storage means; an output means for outputting the information stored in the storage means; Calculating means for calculating an input time and calculating the total free capacity of the storage means when the output means outputs the information during the input time; and A control unit for starting the input of the information by the input unit in some cases.