JP3020577B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a column address control in the same, and is applied to, for example, a x1 type dynamic random access memory (abbreviated as DRAM). Effective technology.

[Conventional technology]

In a DRAM, when one word line is selected, all the memory cells connected thereto are selected, and the data appears on each bit line. In a normal read cycle, only one of them is selected by the column decoder, but the contents of any memory cell connected to one word line are read / stored by activating only the column decoder.
Since writing is enabled, high-speed operation is enabled.
This is called a page mode.

On the other hand, when the order of continuously read addresses is always constant and high speed is required, high-speed operation is possible without requiring address input within a 4-bit range determined by a specific address. Nibble mode is used.
In this mode, the read or write operation is
It is possible to start from an arbitrary address among the four bits, and a row and column address is input to this address as in a normal cycle. Write / read for the other three bits is performed using the column address strobe (CAS *: *
Is executed by asserting a signal to low level.

Further, in the above nibble mode, although the speed was increased by eliminating the need for the address signal in the page mode,
There is a static column mode in which the CAS * signal is unnecessary and the speed is increased. Since a memory having the static column mode employs a static circuit for column selection, once a row address is selected, reading / writing of information of a memory cell connected to the word line is performed by the static memory. It can be done quickly and easily as in

As an example of a document described in each of the above modes, there is an "LSI Handbook" issued by Ohm Co., Ltd. on November 30, 1984.

[Problems to be solved by the invention]

However, in the page mode and nibble mode above, CA
Since one operation is performed in one cycle of the S * signal, the precharge time of the CAS * signal is useless, and there is a problem in high-speed operation. The static column mode has the following problems.

That is, in the static column mode, CAS
* Since the data is continuously output in response to the column address change while the signal remains at the low level, in other words, unless the column address changes, the data related to the address designation is continuously output. Due to a delay in signal change or the like, an erroneous address, that is, data relating to an erroneous address may be erroneously taken into another module such as a processor.

An object of the present invention is to prevent data relating to an erroneous address from being erroneously taken into another module due to a delay in a change in an address signal and to be handled in one cycle as compared with a normal memory operation mode. An object of the present invention is to provide a semiconductor memory device capable of increasing the amount of data to be obtained. That is, an object of the present invention is to provide a semiconductor memory device capable of a high-speed operation mode.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

In other words, the semiconductor device includes a control unit that enables a column address to be specified in synchronization with the falling timing of the column address strobe signal waveform and enables the column address to be specified in synchronization with the rising timing of the column address strobe signal waveform. It constitutes a storage device. Further, the control unit may include a detection circuit for detecting a falling edge and a rising edge of the column address strobe signal waveform. Further, data read out by column address selection synchronized with the falling timing of the column address strobe signal waveform and data read out by column address selection synchronized with the rising timing of the column address strobe signal waveform are alternatively selected. Selection means for external transmission can be included in the data input / output system. In addition, an output system for both data can be separately provided in place of the selection means.

(Operation)

According to the means described above, under the control of the control unit, it is possible to specify a column address synchronized with the falling timing of the column address strobe signal waveform and a column address synchronized with the rising timing of the signal waveform,
This eliminates erroneous capture of data relating to the immediately preceding designated address, and increases the amount of data that can be handled in one cycle.

〔Example〕

FIG. 1 shows a D (dynamic) RAM according to an embodiment of the present invention. Although the DRAM shown in FIG. 1 is not particularly limited, it is of a type that inputs and outputs data in 1-bit units (× 1 type), and is formed on a single semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technology. Is formed.

In FIG. 1, reference numeral 24 denotes a memory cell array in which a plurality of dynamic memory cells are arranged in a matrix. The selection terminals of the memory cells are connected to word lines in each row direction.
The data input terminals of the memory cells are coupled to complementary data lines for each column direction. And each complementary data line,
These are commonly connected to a complementary common data line via a Y selection switch circuit 27 including a plurality of column selection switches coupled one-to-one.

In the DRAM of this embodiment, although not particularly limited, an address multiplex method is adopted, and row and column address input signals are taken from a common address terminal by shifting their timing. That is, the address multiplexer and X decoder 22 and the address multiplexer before the Y address latch and Y decoder 26 are provided.
The address multiplexer 21 distributes an address signal taken in through an address buffer 20 to an X address latch and X decoder 22 and a Y address latch and Y decoder 26 by an address multiplexer 21. Two types of clock signals, RAS * (* indicates low active) and CAS *, are externally supplied to facilitate such address input. Generally, in order to enable only one of read and write operations during one memory cycle (one cycle of RAS * clock), a row address is strobed at a falling timing of a row address strobe signal (referred to as RAS * clock). Is taken into the internal circuit at the falling timing of the column address strobe signal (referred to as CAS * clock). In the present embodiment, only the falling timing of the CAS * clock is controlled by the control unit 25 in this embodiment. In addition, the internal capture of the column address is enabled by the rising timing of the CAS * clock. That is, as shown in FIG.
The falling edge 51 and the rising edge 52 of the S * clock are detected by the control unit 25 in FIG. 1, and a column address is fetched based on the detection result. The edge detection of the CAS * clock is not particularly limited, but is enabled by a logical configuration as shown in FIG. In FIG.
Four N-channel MOSFETs Q1, Q2, E3, and Q4 are connected in series. CAS * clock is directly input to the gate of MOSFET Q1, and CAS * clock is input to MOSFET Q4 via inverter 49. The gate of MOSFET Q2 has an inverter 40 ~
CAS via 44, 2-input NAND gate 45 and inverter 46
The clock is input, while the CAS * clock is input to the gate of MOSFET Q3 via inverters 40 to 43, a 2-input NAND gate 47 and an inverter 48. A capacitor 50 is connected between the series connection of the inverters 40 and 41 and the ground line, so that a predetermined delay time is given to the CAS * clock. Two-input NAND gate 45,4
A signal RG indicating the end of the gate point time is input to the other input terminal 7. This signal RG
Are asserted to a high level, in other words, during a period during which a column address signal is allowed to be input, the NAND gates 45 and 47 are activated, and the MOSFETs Q2 and Q3 can be driven. The cathodes of the MOSFETs Q1 and Q4 are connected to the ground line, the series connection of the MOSFETs Q2 and Q3 is pulled up via a resistor (not shown), and an interleave control signal
The output terminal of the IC is connected to the interleave circuit 33.

According to such an edge detection circuit 35, during the period in which the signal RG indicating the end of the gate point time is asserted to the high level, the state of the interleave control signal IC is changed every time the state of the CAS * clock is changed, As a result, the falling edge and the rising edge of the CAS * clock can be detected.

In FIG. 1, by judging the state of the write enable signal WE * at the same time as the column address is taken, it is possible to judge whether the cycle is a write cycle or a read cycle. The control unit
Done by 25. That is, the write enable signal WE *
Is at a low level, a write cycle is performed, and when it is at a high level, a read cycle is performed.

The word driver 23 drives a word line to a selected level based on the X address latch and the decode output of the X decoder 22 disposed at the preceding stage. Then, the Y selection switch circuit 27 is driven based on the Y address latch and the decode output of the Y decoder 26, thereby enabling data reading or data writing from the specified memory cell.

Further, a sense amplifier 29 is coupled to the memory cell array 24, and the memory cell information is amplified by the sense amplifier.

The data selected by the Y selection switch 27 is sent to the outside via the data input / output circuit 31. The data input / output circuit 31 includes a latch circuit 32 and an interleave circuit 33. Although the present embodiment is of the x1 type, the data read out in synchronization with the fall timing of the CAS * clock and the CAS
* Since the data read out is continued in synchronization with the rising edge of the clock, the data selected by the Y selection switch 27 is latched by the latch circuit 32 and distributed by the interleave circuit 33. The timing of data distribution is controlled by an interleave control signal IS output from an edge detection circuit in the control unit 25 (see FIG. 2).

Here, in the memory cell array 24 of the x1 type DRAM, as shown in FIG. 6, in addition to the word line (for example, indicated by 53) to which the memory cell to be selected is coupled, other word lines are used. (Shown at 54) is also driven to the selected level at the same time. However, at this time, bit selection is not performed on the word lines 54 that are simultaneously driven, and only refresh is performed substantially. Therefore, in this embodiment, the bit 55 on the selected word line 53 is selected in synchronization with the falling timing of the CAS * clock, and the other word line 54 is selected in synchronization with the rising timing of the CAS * clock.
By making any of the above bits selectable, 1
The number of bits that can be selected for a cycle is increased.

Incidentally, in a DRAM of an element (referred to as a × 4 type) capable of inputting / outputting data in 4-bit units, as shown in FIG. For example, four bits indicated by i / 01, i / 02, i / 03, and i / 04 are simultaneously selected. Even in such a × 4 type DRAM, the × 1 bit is used.
The same memory access as that of the DRAM of the type is enabled.
For example, as shown in FIG. 8, other than the selected word line 57, another word line 58 (the number of word lines is equal) is driven to the selected level, and the falling timing of the CAS * clock is The bit on the word line 57 may be selected in synchronization with the above, and the bit on the other word line 58 may be selected in synchronization with the rising timing of the CAS * clock.

FIG. 4 shows the relationship between the RAS * clock and CAS * clock and column address signals Ai represented by Y1 to Y4.

In this embodiment, the second control unit 25 included in the control unit 25 shown in FIG.
Since the falling edge and the rising edge of the CAS * clock are detected by the edge detection circuit 35 in the figure and the taking in of the column address is controlled based on the detection result, as shown in FIG. , Among the column address signals Y1, Y2, Y3, Y4,... That are successively input, the signal Y1 is made valid when the CAS * clock falls,
2 is made valid when the CAS * clock rises, Y3 is made valid when the CAS * clock falls again, and Y4 is made valid when the CAS * clock rises again. In other words, in normal operation of the memory, the column address can be specified only in synchronization with the falling edge of the CAS * clock.
Column addressing is enabled at each of the falling and rising timings of the CAS * clock, thereby increasing the amount of data that can be handled in one cycle. Also,
Unlike the static column mode, data is not output continuously in response to a column address change while the CAS * clock remains at low level, but the address signal is synchronized with the CAS * clock. There is no inconvenience such that data relating to an erroneous address is erroneously taken into another module such as a processor due to a delay in change.

According to this embodiment, the following operation and effect can be obtained.

(1) Under the control of the control unit 25 in FIG. 1, the column address can be specified in synchronization with the falling timing of the CAS * clock, and the column address can be specified in synchronization with the rising timing of the CAS * clock. Therefore, the amount of data that can be handled in one cycle of the memory can be increased as compared with the normal operation of the memory. That is, a high-speed operation mode is possible.

(2) Static column mode in which column addressing is performed in synchronization with the CAS * clock, so that data related to an erroneous address is erroneously taken into another module due to a delay in the change of the address signal. Can be eliminated, and a DRAM that is easy to handle can be obtained.

(3) Since the falling edge and the rising edge of the CAS * clock can be detected by a relatively simple logical configuration as shown in FIG. 2, the DRAM of this embodiment can be easily obtained.

(4) An interleave circuit 33 is provided as selection means, and CA
Since data distribution is performed in synchronization with the falling and rising edges of the S * clock, the same external terminal must be used for data relating to the falling of the CAS * clock and data relating to the rising of the CAS * clock. They can be shared, and increase in external terminals can be prevented.

(5) When the DRAM of this embodiment is applied to a frame memory of an HDTV (high-definition television), image data for two screens can be handled at a high speed, which is advantageous when data processing is performed. Becomes

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and can be variously modified without departing from the gist thereof.

For example, in the above embodiment, the interleave circuit 33 is provided, and CA
Although the data is distributed in synchronization with the falling and rising edges of the S * clock, instead of providing the interleave circuit 33, two data input / output systems including external terminals are provided, and the CAS * clock rising edge is provided. Data input / output may be individually possible for each column address taken in synchronization with each of the down timing and the rising timing.

Further, in the above embodiment, the column address is taken in synchronization with the falling timing and the rising timing of the CAS * clock, but the operation of the address counter is controlled by synchronizing the falling timing and the rising timing of the CAS * clock. You may make it. For example, as shown in FIG. 5, "1" is counted at the falling timing of the first CAS * clock, and "2" is counted at the rising timing of the clock. Similarly, the second CA
S * clock falling timing "3" is counted,
"4" is counted at the rising timing of the clock. In this manner, the address may be designated by controlling the operation of the address counter. Other 1st edge detection
The control unit 25 shown in the figure is provided with two types of circuits, a CAS * system and a CAS system (CAS: indicates CAS clock signal high active).
* Falling and rising edges of the clock may be detected. The selection bit is determined by using the Y-address latch and Y-decoder 26 shown in FIG.
Even when the selection switch circuit 27 is continuously operated to continuously select the bits on the selected word line, the same effect as in the above embodiment can be obtained.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, under the control of the control unit, it is possible to specify a column address synchronized with the falling timing of the column address strobe signal waveform and a column address synchronized with the rising timing of the signal waveform. Such erroneous data acquisition can be eliminated, and the amount of data that can be handled in one cycle can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a DRAM according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a detailed configuration of a main part of the DRAM shown in FIG. 1. FIG. FIG. 4 is a timing chart showing the relationship between the CAS * clock and the column address, FIG. 5 is a timing chart showing the relationship between the CAS * clock and the address counter, and FIG. 6 is the DRAM of this embodiment. FIGS. 7 and 8 are explanatory diagrams of selected bits in a × 4 type DRAM. 20 ... address buffer, 21 ... address multiplexer, 22 ... X address latch and X decoder, 23 ... word driver, 24 ... memory cell array, 25 ... control unit, 26 ... Y address latch and Y decoder, 27 ... Y
Select switch circuit, 29 Sense amplifier, 31 Input / output circuit, 32 Latch circuit, 33 Interleave circuit, 35
.... Edge detection circuit.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuo Mogi 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Ultra-SII Engineering Co., Ltd. (72) Inventor Mitsunori Ota 5-20-1, Kamizuhoncho, Kodaira-shi Inside Hitachi Ultra-SII Engineering Co., Ltd. (56) References JP-A-58-115684 (JP, A) JP-A-60-136086 (JP, A) JP-A-58-91590 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/407

Claims (5)

(57) [Claims] 1. A common external terminal to which a row address signal, a first column address signal, and a second column address signal are inputted from outside, and a timing for taking in the first and second column address signals from the external terminal are determined. And a signal line for transmitting a first signal that swings between a high level and a low level to cause the first signal to change from the high level to the low level and to change from the low level to the high level. A detection circuit for detecting a rising edge to output a second signal, and a control unit for receiving the second signal and controlling the capture of the first and second column address signals. When the first and second column address signals are continuously input to the external terminal, the first column address signal falls at the falling edge of the first signal. A semiconductor memory device having a mode for taking in a dress signal and taking in the second column address signal at the rise of the first signal. 2. The semiconductor device according to claim 1, wherein said first signal is a column address strobe signal. 3. The semiconductor device according to claim 1, wherein the semiconductor device has data read by column address selection synchronized with a falling timing of the first signal and a column address synchronized with a rising timing of the first signal. A semiconductor device, further comprising a selection unit for selectively transmitting data read out by selection to the outside. 4. The semiconductor device according to claim 1, wherein the semiconductor device has data read by column address selection synchronized with a falling timing of the first signal and a column address synchronized with a rising timing of the first signal. A semiconductor device further comprising a separate external output form with data read by selection. 5. The semiconductor device according to claim 1, further comprising: a plurality of memory cells provided at intersections of a plurality of word lines and a plurality of bit lines; While one of the plurality of word lines is at a high level, data is read from one of the plurality of bit lines by the first column address signal, and the second column address is continuously read. A semiconductor device wherein data is read from another of the plurality of bit lines by a signal.