JP3022342B2 - Semiconductor integrated circuit and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit using a CMOS transistor.

[0002]

2. Description of the Related Art Conventionally, in semiconductor integrated circuits,
In order to handle a larger amount of information at a high speed, a method of increasing the degree of integration by reducing the transistor size has been considered.

However, even if the transistor size is reduced, if the power supply voltage remains the same, the gate withstand voltage will decrease when the transistor size is reduced to some extent. I will.
Under such circumstances, one buffer circuit is required for the prior art.
This will be described as one example.

FIG. 2 is a circuit diagram showing one configuration example of a conventional semiconductor integrated circuit.

In this conventional example, as shown in FIG. 2, a CMOS transistor 13 whose input is connected to the input terminal 1 and a CMOS transistor whose input is connected to the output of the CMOS transistor 13 and whose output is connected to the output terminal 2 12 and
A peripheral LSI (not shown), a CMOS transistor 12,
13 and a power supply line 3 for supplying power to the peripheral LSI, and a grounded ground line 6. The CMOS transistor 13 includes a PchMOS transistor 9 and an NchMOS transistor 11, and a CMOS transistor. Transistor 12 is a PchMO
S transistor 10 and NchMOS transistor 12
It is composed of Note that the PchMOS transistor 9, the NchMOS transistor 11, and the PchMOS
MOS transistor 10 and NchMOS transistor 1
2 are connected to each other on the respective drain sides. Further, the PchMOS transistor 9 and the PchM
The source side of the OS transistor 10 is connected to the power supply line 3, and the NchMOS transistor 11 and the NchMOS
The source side of the transistor 12 is connected to the ground line 6.

[0006] The operation of the semiconductor integrated circuit configured as described above will be described below.

When a high-level signal is input to the input terminal 1, the NchMOS transistor 11 is turned on,
The low level is transmitted to the next-stage CMOS transistor 14. Then, the PchMOS transistor 10 is turned on, and a high-level signal is output from the output terminal 2. The output level at this time has a value substantially equal to the voltage of the power supply line 3.

When a low level signal is input to the input terminal 1, the PchMOS transistor 9 is turned on, then the NchMOS transistor 12 is turned on, and a low level signal is output from the output terminal 2.

FIG. 3 is a circuit diagram showing another configuration example of a conventional semiconductor integrated circuit. In this conventional example, a NAND circuit is used as one example of a semiconductor integrated circuit.

In this conventional example, as shown in FIG. 3, the diode 7 whose anode is connected to the power supply terminal 18, the diode 8 whose cathode is connected to the ground terminal 19, and the cathode of the diode 7 and the output terminal 17 are connected. From two PchMOS transistors 20 and 21 connected in parallel between them, two NchMOS transistors 22 and 23 connected in series between the anode of the diode 8 and the output terminal 17, and a peripheral LSI (not shown). PchMO
S transistor 21 and NchMOS transistor 22
Is connected to the input terminal 15 and the inputs of the PchMOS transistor 20 and the NchMOS transistor 23 are connected to the input terminal 16 (JP-A-4-18692).
No. 1).

The operation of the semiconductor integrated circuit configured as described above will be described below.

When a high-level signal is input to the input terminals 15 and 16, both the PchMOS transistors 21 and 20 are turned off, and both the NchMOS transistors 22 and 23 are turned on. Outputs a low level signal. In this case, the potential of the output terminal 17 becomes higher than the potential of the ground terminal 19 by the forward voltage drop of the diode 8.

When a low-level signal is input to the input terminal 15 and a high-level signal is input to the input terminal 16, the PchMOS transistor 21 is turned on,
As a result, a high-level signal is output from the output terminal 17. In this case, the voltage at the output terminal 17 is
Is lower by a forward voltage drop of the diode 7 than the potential of the diode 7.

The feature of this conventional example is that the amplitude is reduced by the sum of the forward voltage drops of the diodes 7 and 8, so that the charge / discharge current can be reduced and as a result power consumption can be reduced. The point is.

[0015]

As described above, when a transistor size of a semiconductor integrated circuit is reduced in order to handle a larger amount of information at a high speed, a transistor is not provided if a power supply voltage remains unchanged. Since the gate breakdown voltage decreases when the size is reduced to some extent, it is necessary to reduce the power supply voltage used. Therefore, when using a type of LSI whose power supply voltage is lowered in consideration of the use power supply voltage of the peripheral LSI, a power supply line or a ground line dedicated to the LSI must be designed on a substrate in advance, or the power supply itself must be designed. You have to prepare two.

Therefore, when the power supply voltage to be used is changed,
In the same circuit, design and development must be performed again in accordance with the power supply voltage of the peripheral LSI, and there is a problem that the number of steps including the management of design resources increases.

When a diode connected to a power supply terminal or a ground terminal is provided, a power supply voltage exceeding the breakdown voltage level of the transistor used can be used. However, power is supplied to the transistor via the diode. Therefore, when the power supply voltage level is lowered for the purpose of reducing power consumption, there is a problem in that a necessary power supply voltage is not easily supplied to the transistor.

The present invention has been made in view of the above-mentioned problems of the prior art, and has been developed in consideration of the peripheral LSI.
It is an object of the present invention to provide a semiconductor integrated circuit capable of supplying a power supply voltage within a withstand voltage level to a CMOS transistor without redesigning a circuit even when a used power supply voltage is changed, and a driving method thereof. I do.

[0019]

Means for Solving the Problems The present invention to achieve the above object, a CMOS transistor, the CMOS tiger
The first voltage and the first voltage are formed on the same substrate as the transistor.
1 is lower than the voltage of 1 and the CMOS transistor is driven.
Drive at one of the second voltages sufficient to
And a peripheral LSI having at least the first voltage or the second voltage.
First power supply line to be used and the CMOS transistor
And a second power supply line to which the second voltage is applied.
And the first power supply line and the CMOS transistor.
The first power supply line side as an anode between the
Connected first diode and grounded first ground.
And the CMOS transistor
A second ground line, and the first ground line
The first ground between the first transistor and the CMOS transistor;
Second diode connected with line side as cathode
And the first and second diodes are connected to the first diode.
When the first power is supplied to the power line of
When the second power is supplied to the CMOS transistor
A voltage drop, wherein the peripheral LSI is connected to the first voltage.
When driving, the CMOS transistor has the first
Power supply from the power supply line through the first diode.
Supplied and the peripheral LSI is driven by the second voltage
In this case, the CMOS transistor includes the second power supply line.
And power is supplied from the second ground line.
Characterized in that the component is grounded . In addition, the first power
Voltage exceeds the breakdown voltage level of the CMOS transistor
A power supply voltage, and the second voltage is the CMOS transistor.
The power supply voltage is within the breakdown voltage level of the transistor.
I do.

In the method for driving a semiconductor integrated circuit, the power supply voltage driven by the peripheral LSI is the first voltage.
Voltage , the first power line is connected to the first power line.
And the second power supply line and the second ground line are opened to drive the peripheral LSI.
When the power supply voltage to be applied is the second voltage , the second voltage is supplied to the first and second power supply lines, and the second ground line is grounded.

(Operation) In the present invention configured as described above, the first and second power supply lines and the first ground line are respectively connected between the CMOS transistor and the first power supply line.
, And a second power supply line and a second ground line are connected between the first and second diodes and the CMOS transistor, respectively.
If the power supply voltage used in the peripheral LSI is higher than the withstand voltage level of the CMOS transistor,
CMO from the first power supply line via the first diode
When power is supplied to the S transistor, the CMOS
The transistor is supplied with a voltage lower than the power supply voltage by the voltage drop in the first and second diodes. If the power supply voltage used in the peripheral LSI is within the withstand voltage level of the CMOS transistor, the second voltage is applied. The power supply voltage is supplied from the power supply line to the CMOS transistor as it is.

As described above, when the power supply voltage used in the peripheral LSI is changed, the power supply voltage supplied to the CMOS transistor is changed to CM by merely changing the power supply method from the power supply line to the CMOS transistor.
Since the voltage is set within the withstand voltage level of the OS transistor, there is no need to redesign the circuit when the power supply voltage used in the peripheral LSI is changed.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor integrated circuit according to the present invention.

In this embodiment, as shown in FIG. 1, a CMOS transistor 13 whose input is connected to the input terminal 1 and a CMOS transistor 12 whose input is connected to the output of the CMOS transistor 13 and whose output is connected to the output terminal 2 , Peripheral LSI (not shown), and CMOS transistors 12 and 1
3 and a second power supply line 4 for supplying power to peripheral circuits, and a first ground line 6 and a second ground line connected to CMOS transistors 12, 13 and peripheral circuits. 5, a first diode 7 having an anode connected to the power supply line 3, and a second diode 8 having a cathode connected to the ground line 6.
And the CMOS transistor 13 includes:
The CMOS transistor 12 includes a PchMOS transistor 9 and an NchMO transistor 11.
And an S transistor 12. Note that Pc
hMOS transistor 9 and NchMOS transistor 1
1, PchMOS transistor 10 and NchM
The OS transistors 12 are connected to each other on the respective drain sides. The source sides of the PchMOS transistor 9 and the PchMOS transistor 10 are connected to the power supply line 4 and the cathode of the diode 7,
The source sides of the NchMOS transistor 11 and the NchMOS transistor 12 are connected to the ground line 5 and the anode of the diode 8. The ground line 6 is grounded.

The operation of the semiconductor integrated circuit configured as described above will be described below.

When a high level signal is input to the input terminal 1, the NchMOS transistor 11 is turned on,
Next, the PchMOS transistor 10 is turned on, and a high-level signal is output from the output terminal 2.

When a low level signal is input to the input terminal 1, the PchMOS transistor 9 is turned on, and a low level signal is output from the output terminal 2.

If the power supply voltage used in the peripheral LSI exceeds the withstand voltage level of the CMOS transistors 13 and 14, the power supply voltage is supplied to the power supply line 3 and the power supply line 4 and the ground line are supplied. 5 is used in the OPEN state. Thereby,
This circuit operates (outputs) at an amplitude obtained by subtracting the voltage drop of the diodes 7 and 8.

When the power supply voltage used in the peripheral LSI is within the breakdown voltage level of the CMOS transistors 13 and 14, the power supply voltage is supplied to both the power supply lines 3 and 4 and the ground line 5 is supplied. , 6
Use both with grounding.

However, as a precondition, CMOS
The transistors 13 and 14 are set under normal power supply voltage conditions, and when used at a power supply voltage exceeding the withstand voltage level,
It is necessary to design so that the voltage applied to the CMOS transistors 13 and 14 becomes equal to the normal power supply voltage due to the forward voltage drop of the diode 7.

As a result, even when the power supply voltage of the peripheral LSI is changed, the same LSI can be used only by changing the power supply method from the power supply line to the CMOS transistor.
Can be used.

[0033]

As described above, in the present invention,
First power line and first ground line and CMOS
First and second diodes are provided between the first and second diodes, respectively;
A second power supply line and a second ground line are connected to the respective transistors, and when the power supply voltage used in the peripheral LSI is higher than the withstand voltage level of the CMOS transistor, the first power supply line and the second ground line are connected via the first diode. Power is supplied from the first power supply line to the CMOS transistor, and the power supply voltage used in the peripheral LSI is CM.
When the power supply voltage is within the withstand voltage level of the OS transistor, power is supplied from the second power supply line to the CMOS transistor, so that the power supply voltage used in the peripheral LSI exceeds the withstand voltage level of the CMOS transistor. In some cases, a voltage lower than the power supply voltage is supplied to the CMOS transistor by a voltage drop in the first and second diodes, and the power supply voltage used in the peripheral LSI is within the withstand voltage level of the CMOS transistor. Can supply the power supply voltage to the CMOS transistor as it is.

As described above, since the power supply voltage supplied to the CMOS transistor can be changed only by changing the method of supplying power from the power supply line to the CMOS transistor, the power supply voltage used in the peripheral LSI is changed. In any case, without redesigning the circuit,
A power supply voltage within the breakdown voltage level can be supplied to the CMOS transistor. Thus, the number of steps involved in circuit redesign when the power supply voltage used in the peripheral LSI is changed can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a conventional semiconductor integrated circuit.

FIG. 3 is a circuit diagram showing another configuration example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Output terminal 3, 4 Power supply line 5, 6 Ground line 7, 8 Diode 9, 10 PchMOS transistor 11, 12 NchMOS transistor 13, 14 CMOS transistor

Claims (3)

(57) [Claims] 1. A and CMOS transistors, the CMOS DOO
The first voltage and the first voltage are formed on the same substrate as the transistor.
The CMOS transistor is driven lower than the first voltage
Driven by one of the second voltages sufficient to
A semiconductor integrated circuit having at least a peripheral LSI that performs the first voltage or the second voltage application.
And the second voltage connected to the power supply line and the CMOS transistor.
Between the first power supply line and the CMOS transistor.
The first power supply line side is connected as an anode
A first diode, a grounded first ground line, and a second ground connected to the CMOS transistor.
Line, the first ground line, and the CMOS transistor
The first ground line side as a cathode
And a second diode connected thereto, wherein the first and second diodes are connected to the first power supply line.
The second power supply when the first power supply is supplied to the
Voltage drop to be supplied to the CMOS transistor
The peripheral LSI is driven by the first voltage.
The CMOS transistor is located before the first power supply line.
The power is supplied through the first diode, and
When the LSI is driven by the second voltage, the CMOS
Power is supplied to the transistor from the second power supply line
And the second ground line is grounded . 2. The semiconductor integrated circuit according to claim 1, wherein
hand, The first voltage is a withstand voltage level of the CMOS transistor.
Power supply voltage exceeding The second voltage is a withstand voltage level of the CMOS transistor.
A semiconductor integrated circuit characterized by a power supply voltage within the bell
Road. 3. The method of driving a semiconductor integrated circuit according to claim 1 , wherein the power supply voltage driven by the peripheral LSI is the first voltage , the power supply voltage is applied to the first power supply line. Supplying the first voltage , opening the second power supply line and the second ground line, and when the power supply voltage driven by the peripheral LSI is the second voltage , the first and the second wherein the second power supply line the second
A method for driving a semiconductor integrated circuit, comprising supplying a voltage and grounding the second ground line.