JP3022682B2 - Memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit, and more particularly to a memory circuit having a self-test function.

[0002]

2. Description of the Related Art FIG. 5 shows a configuration of a semiconductor memory circuit having a self-test function. The RAM 1 is an asynchronous random access memory having an arbitrary word capacity (hereinafter, referred to as word depth). In order to test the memory 1, a clock signal is supplied from a clock generator 10 for testing. The test data is converted to the data generator 1 according to
1 and a test address from the address generator 12. The comparator 13 compares the data read from the RAM 1 with predetermined data.
Output as If there is no error, the error signal 8 has the logical value 1.

[0003] Generally in self-test circuit of this type of memory is marching method, and N type pattern such as checkerboard method, galloping method, but using the N ² type pattern such as walking method, memory testing technique already established Test. In these patterns, the test addresses change one by one in ascending order or descending order. Therefore, a counter circuit is generally used as the address generator 12.

Here, a case where a test is performed on a memory circuit having a word depth of 64 will be described as an example.

In this case, since the word depth 64 is 2 to the sixth power, six address signals are used. Each word of this memory circuit is converted to an address signal (000000)
2 to (111111) 2, respectively.
Four types of data can be stored individually. still,
The suffix “2” at the right end of the address signal indicates that the address is represented in binary, and the same applies to the following description and drawings.

Therefore, in this case, using a 6-bit counter circuit corresponding to 6 addresses, (00000
A memory test is performed while sequentially generating addresses from 0) 2 to (111111) 2. This counter is desirably an up / down counter capable of ascending order and descending order. However, this up / down counter is usually not advantageous in terms of hardware because both the number of cells and the size increase.

In view of this, there is a type which uses a counter of only ascending order and generates ascending and descending binary addresses with a small number of logic circuits by an exclusive logical product of the counter output and control signals for ascending and descending order control.

Next, considering a case where a test is performed on a memory circuit having a word depth of 42, six address signals are still required even if the word depth is 42, and each word has an address signal of ( 000000) 2 to (101
001) 2. That is,
By using N address signals satisfying W ≦ 2 ^N for an arbitrary word depth W, W types of data can be individually stored in the memory.

The self-test circuit of the memory circuit having a word depth of 42 also uses a 6-bit counter corresponding to the six addresses as described above. In this case, the address signal is (000000) 2 to (101001). Since there is no memory capacity corresponding to the portion exceeding (101001) 2, the self-test circuit will determine an error if the test is performed as it is.

For this purpose, the address is previously set to (10100
1) A device that does not exceed 2 is required. For example, to generate addresses in ascending order, (101001)
2 is inserted and provided, and (10100
1) When 2 is detected, there is a method of preventing the counter from counting up any further. In order to generate addresses in descending order, there is a method of using a presettable up / down counter, first presetting (101001) 2, and then counting down. Furthermore,
These methods may be combined.

In such a conventional memory circuit having a self-test function, it is necessary to use an up / down counter capable of freely presetting data as a counter for generating an address signal so as to support a memory having an arbitrary word depth. Therefore, there is a problem that the circuit scale of the self-test circuit increases. In addition, there is a problem that a logic circuit specific to an arbitrary word depth is required, so that the arbitrariness is remarkably reduced and versatility is lost.

[0012]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a memory device having an arbitrary word depth for testing a circuit. Another object of the present invention is to provide a memory circuit capable of improving versatility without increasing the number of memory cells.

[0013]

A memory circuit according to the present invention comprises: a memory;
Address generating means for sequentially generating addresses of the memory up to an address equal to or greater than the maximum address of the memory; and monitoring an output of the memory accessed by the address by the address generating means and outputting an error signal when an error occurs. Error monitoring means, and mask control for monitoring an address output from the address generation means and masking an error signal of the error monitoring means when detecting an address exceeding a preset maximum address of the memory. Means. And before
The mask control means sets the maximum address of the memory in advance.
Means for setting the maximum address to be set, and the maximum address setting
Generating the two's complement of the maximum address from the determining means
Generating means, an output of the address generating means and the complement generation
An adding means for adding the output of the means, and
An error signal of the error monitoring means according to the most significant bit
And a mask means for performing mask control of
You.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and the same parts as those in FIG. 5 are denoted by the same reference numerals. The memory under test 1 has an asynchronous R operating according to an address change.
AM. The data generator 11, the address generator 12, and the comparator 13 perform a memory test in synchronization with a test clock signal from the clock generator 10, as in the related art.

The address generator 12 is composed of a counter having only a simple ascending order and an exclusive logical AND circuit. The exclusive logical AND circuit applies a counter output to one input of the exclusive logical AND circuit and an external input to the other input. By inputting control signals for ascending order and descending order control, it is possible to generate ascending or descending binary address signals.

The comparator 13 compares a predetermined pattern with the output of the memory 1, and if there is a difference, generates and outputs a logic 0 as an error signal.

The maximum address generator 4 is for setting and registering the maximum word depth of the memory under test 1 in advance. This circuit can be realized by the number of transistor elements corresponding to the number of address signals. By controlling according to the bit pattern of the maximum address which is the maximum word depth, any word depth can be easily handled.

The two's complement generator 3 is a maximum address generator 4
Converts the maximum address signal set and registered into a 2's complement signal. The adder 2 adds the two's complement signal and the address signal generated by the address generator 12, and outputs only the most significant bit 5 of the result.

The most significant bit 5 of this addition result and the comparator 1
The error signal of No. 3 is input to the logical sum circuit 9, and the logical sum output becomes the final error signal 8.

The operation of the self test circuit for the memory having the word depth 42 will be described below. FIG. 2 shows the real address of the memory 1 having a word depth of 42. Since the address signal is composed of 6 bits, (000000) 2
The range of ~ (101001) 2 is the real address range.
Addresses in the range of (101010) 2 to (111111) 2 do not exist in the memory 1.

FIG. 3 is a diagram showing how the address signal changes in the case of a memory having a word depth of 42. In the maximum address generator 4, (101010) 2 is set and registered in advance,
This maximum address is output. This two's complement 3 converts this maximum address to (010110) 2,
This conversion output and (00000) from the address generator 12 are output.
The address groups in the range of 0) 2 to (111111) 2 are added by the adder 2, respectively.

The actual address (000000) 2-
(101001) 2 and the two's complement of the maximum address (010
The result of addition with (110) 2 is (0010110) 2-
(0111111) 2. That is, the seventh bit, which is the most significant bit of the addition result, is all “0”.

On the other hand, the data which does not exist in the memory 1 (10
1010) 2 to (111111) 2 and the maximum address 2
The result of addition with the complement (010110) 2 of (1000)
000) 2 to (1010101) 2. That is,
The seventh bit which is the most significant bit of the addition result is "1".
Becomes

Therefore, by determining whether the most significant bit of the addition result is “0” or “1”, the address generator 1
2 can easily determine whether or not the address generated corresponds to the real address of the memory under test 1.

Therefore, as shown in FIG. 1, the most significant bit 5 of the output of the adder 2 and the output of the comparator 13 are added to the OR circuit 9.
, The error signal output of the comparator 13 is
In the range beyond the real address, all become "1", indicating normal, and the error signal 8 does not indicate abnormal.

From another viewpoint, it is equivalent to masking the output of the comparator 13 in accordance with the most significant bit of the added output, and the OR circuit 9 operates as a mask circuit for that purpose. I do. Therefore, the logical configuration of the mask circuit should be appropriately changed depending on whether the error display of the output of the comparator 13 is set to “0” or “1”.

FIG. 4 is a block diagram of another embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In the present embodiment, an inverter 14 and an AND circuit 15 are added to the configuration of FIG. 1 so that when the address of the address generator 12 exceeds the real address of the memory 1, the operation clock signal to the memory 1 is transmitted. The supply is stopped.

For this purpose, the most significant bit 5 of the output of the adder 2 is inverted by the inverter 14 so that when it is out of the range of the real address, one input of the AND circuit 15 is forcibly set to "0". , The supply of the clock signal to the memory 1 is suppressed. This makes it possible to automatically avoid unnecessary tests.

[0030]

As described above, according to the present invention, a test address generator for a memory having an arbitrary word depth can be simply constructed, and it is also necessary to change a logic circuit according to the word depth. Therefore, it is easy to provide a versatile self-test circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram showing an address image of a memory having a word depth of 42.

FIG. 3 is a diagram showing a change mode of a test address of a memory having a word depth of 42;

FIG. 4 is a block diagram of another embodiment of the present invention.

FIG. 5 is a block diagram of a conventional memory circuit having a self-test function.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 RAM 2 Adder 3 2's complement generator 4 Maximum address generator 5 Most significant bit 8 Error signal 9 OR circuit 10 Clock generator 11 Data generator 12 Address generator 13 Comparator 14 Inverter 15 Logical product circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/16 G06F 11/22 G11C 29/00

Claims (4)

(57) [Claims] 1. A memory and an address of the memory,
Generated sequentially up to addresses greater than the maximum address of memory
Address generating means, and an address generated by the address generating means.
Monitoring the output of the memory accessed by the
Error monitoring means that outputs an error signal when an error occurs
And an address output from the address generating means.
Exceeds the preset maximum address of the memory
Error detected by the error monitoring means
A mask control means for performing mask control of a signal. 2. The mask control means according to claim 1, wherein
A maximum address setting means for presetting a large address;
2's complement of the maximum address from the maximum address setting means
Means for generating a complement, and output from the address generating means.
Addition means for adding the power and the output of the complement generation means
And the error monitor according to the most significant bit of the addition result.
Mask means for performing mask control of the error signal of the visual means.
The memory circuit according to claim 1, further comprising: 3. The method according to claim 2, wherein the masking means is configured to determine whether the error signal is
It has a logical sum means to output a logical sum with the most significant bit
3. The memory circuit according to claim 2 , wherein: 4. The memo according to a value of the most significant bit.
And means for stopping and controlling the operation clock of the
The memory circuit according to claim 2 or 3, wherein