JP3027482B2 - Charge transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for transferring signal charges in, for example, an image pickup device, and more particularly to a charge transfer device capable of detecting transferred signal charges.

[0002]

2. Description of the Related Art In a conventional image pickup apparatus such as an infrared image pickup apparatus, signal charges obtained by photoelectric conversion are transferred.
A charge transfer device having a function of detecting the transferred signal charge is provided.

FIG. 9 is a schematic diagram showing a configuration of a conventional charge transfer device. Semiconductor substrate 1 made of p-type Si semiconductor
Are electrically grounded. On this semiconductor substrate 1, a channel layer 2 extending in a predetermined direction is provided. The channel layer 2 is an n-type buried channel layer and is formed by ion implantation. A plurality of electrodes 3 arranged along a direction in which the channel layer 2 extends is provided on a partial region of the channel layer 2.
(Only one of the terminations is shown) is disposed via the insulating film 4.

An electrode 5 is disposed via an insulating film 4 on a region adjacent to a region of the channel layer 2 below the terminal electrode 3 and an extension side of the direction in which the electrodes 3 are arranged. A source region 6 made of an n ⁺ -type impurity layer is provided above a region of the channel layer 2 below the electrode 5 and a region adjacent to the extension direction side. This source region 6 is formed by ion implantation and functions as a floating diffusion.

A drain region 7 made of an n ⁺ -type impurity layer is provided above the region of the channel layer 2 at a predetermined distance from the source region 6 in the extension direction. This drain region 7 is formed by ion implantation. A gate electrode 8 is arranged above a region between the source region 6 and the drain region 7 with the insulating film 4 interposed therebetween.

A control signal φC composed of a clock pulse is applied to the electrode 3, and a constant DC voltage OG is applied to the electrode 5.
Is applied. A control signal φR composed of a clock pulse is applied to gate electrode 8. In the drain region 7,
A constant DC voltage VR is applied from outside.

[0007] The source follower amplifier 9 includes a driving transistor 91 and a load transistor 92. Transistor 91 and transistor 92 are connected to power supply voltage V
D is connected in series between power supply node 93 receiving D and ground node 94 receiving the ground voltage. Transistor 91
The node between transistor and transistor 92 is connected to output node 95. Output signal DO is output from output node 95. The gate of transistor 91 is connected to source region 6 via an aluminum interconnection. As a result, the potential of the source region 6 is applied to the gate. A constant DC voltage VG is applied to the gate of the transistor 92. Such a source follower amplifier 9 outputs, from an output node 95, an output signal DO obtained by amplifying the potential of the source region 6 applied to the gate of the transistor 91.

Note that a certain capacitance c1 exists between the source region 6 and the semiconductor substrate 1, and a certain capacitance c2 exists between the source region 6 and the gate electrode 8. Further, a constant capacitance c3 exists between the source region 6 and the electrode 5,
A certain capacitance c4 exists between the gate of the transistor 91 and the substrate.

Next, the operation will be described. FIG.
Channel layer 2 between electrode 3 and drain region 7 in FIG.
FIG. 4 is a potential distribution diagram showing potentials in the inside, and in this potential distribution diagram, the potential is shown to increase from top to bottom in the figure. FIG. 11 is a timing chart showing waveforms of control signals φC and φR and output signal DO. Hereinafter, the operation of the charge transfer device of FIG. 9 will be described with reference to FIG. 9, FIG. 10 and FIG.

First, as shown in FIG. 11, the control signal φC goes to the high level VHC, and at the same time, the control signal φR goes to the high level VHR. When the control signal φC is at the high level V
By becoming HC, the channel potential below the electrode 3 becomes high level ΨHC (see FIG. 10), and signal charges (electrons)
-Q is transferred into the channel below the electrode 3. When the control signal φR goes to the high level VHR, the channel potential below the gate electrode 8 goes to the high level ΔHR (see FIG. 10), and the channel is turned on. As a result, the source region 6 is charged to the potential corresponding to the voltage VR by the voltage VR applied to the drain region 7, and the level of the output signal DO becomes the potential V as shown in FIG.
The level corresponds to R.

Then, as shown in FIG. 11, the control signal φR changes to the low level VLR, and the channel potential under the gate electrode 8 changes to the low level ΔLR (see FIG. 10).
The channel is turned off. At this time, part of the potential of the source region 6 is distributed to the capacitor C2, and as a result, the potential slightly drops to VR1. As a result, as shown in FIG. 11, the level of output signal DO lowers by a level ΔV corresponding to the lowering of the potential of source region 6.

Then, as shown in FIG. 11, the control signal φC goes to the low level VLC, and the channel potential below the electrode 3 is lower than the channel potential ΔOG below the electrode 5 (see FIG. 10). Reference). Therefore, the signal charge −Q transferred into the channel below the electrode 3
Are accumulated in the source region 6 through the channel below the electrode 5. As a result, the potential of the source region 6 decreases by the potential variation ΔVFD shown in the following equation (1).

ΔVFD = −Q / CFD (1) where CFD in the equation (1) is the capacitance of the source region 6, and is the sum of the capacitances C1, C2, C3, and C4.

This potential variation ΔVFD is applied to the gate of transistor 91 of source follower amplifier 9 and output from output node 95 as output signal variation ΔVout (see FIG. 11). The relationship between ΔVFD and ΔVout is expressed by the following equation (2), where the gain of the source follower amplifier 9 is Av.

ΔVout = Av · ΔVFD = −Av · Q / CFD (2) The output variation ΔVout represents the signal charge −Q. The gain Av is generally about 0.9.

In order for the source follower amplifier 9 to function as a source follower, both the transistors 91 and 92 need to operate in a saturation region. Transistors 91 and 9
In the case where the respective thresholds of 2 are Vth, the voltage VR needs to satisfy the condition of the following equation (3) in order for the transistor 91 to operate in the saturation region.

VR ≦ VD + Vth (3) For this reason, the voltage VR and the voltage VD are generally equalized.

In order for the transistor 92 to operate in the saturation region, the potential Vmin of the output node 95 when the maximum signal charge is transferred to the source region 6 needs to satisfy the condition of the following equation (4). There is.

Vmin ≧ VG−Vth (4) In the conventional charge transfer device as described above, it is generally required to detect signal charges with high sensitivity. To satisfy this requirement, In the expression (2), the source region 6
In which the capacitance CFD is made as small as possible and the potential variation ΔVFD is increased with a small amount of signal charge.

[0020]

However, as described above, in the technique of reducing the capacitance CFD of the source region 6 in order to detect signal charges with high sensitivity, the potential of the source region 6 is reduced by the electrode 5 shown in FIG. When the potential becomes lower than the lower potential ΨOG, the signal charge flows back to the channel below the electrode 3, so that the potential variation Δ
VFD has an upper limit. The upper limit is VR1-ΨO
G. That is, the absolute value of the maximum charge amount QFDmax stored in the source region 6 is expressed by the following equation (5).

| QFDmax | = CFD × (VR1-ΨOG) (5) From the above equation (5), when the capacitance CFD is reduced, the maximum signal charge | QFDmax | decreases, and the capacitance CFD is increased in order to increase the sensitivity. When is reduced, the maximum charge amount decreases, and the dynamic range decreases. As described above, when the dynamic range decreases, the signal charges stored in the source region 6 are saturated.

Even if the signal charges do not saturate in the source region 6, the sensitivity of the source follower amplifier 9 can be increased because of the limitations on the operating conditions shown in the above equations (3) and (4). As a result, the output fluctuation amount ΔVout
Becomes larger and the potential Vmin becomes smaller, it becomes difficult to satisfy the expression (4).

In order to avoid such a decrease in the dynamic range, it is sufficient to increase each voltage of VR = VD while satisfying this condition. However, in this case, the power consumption of the source follower amplifier 9 increases. is there.

Such a problem relating to the reduction of the dynamic range becomes particularly serious when the above-described charge transfer device is used for an infrared imaging device.

The purpose of the infrared imaging device is to detect a small temperature difference between the subject and the background.
It is necessary to simultaneously handle a large amount of signal charges due to background light and minute signal charges due to a subject superimposed thereon. Therefore, if the sensitivity of signal charge detection is increased, the signal charge due to the subject and the signal charge due to the background light increase simultaneously, and a large amount of signal charges must be handled. It is required to be large.

Next, the reason why a charge transfer device having a large dynamic range is required will be described with reference to specific examples. Hereinafter, a case where the charge transfer device is used for an infrared imaging device will be described. For example, in the case of an infrared imaging device using a PtSi—Si Schottky barrier diode having an area of 200 μm ^{2 as} a photoelectric conversion unit, the amount of signal charge due to background light at room temperature of 300K is about 2 × 10 ⁵ electrons. Further, when an image of a subject having a temperature difference of 1 K from the background light is captured, the change amount of the signal charge is about 4 × 10 ³ electrons, and the change amount is only 2% of the background light.

Further, the background light is not constant at 300K, but usually fluctuates by about ± 50K. The signal charge due to background light at room temperature 350K increases to about 1 × 10 ⁶ electrons, while the signal charge due to background light at room temperature 250K decreases to 2 × 10 ⁴ electrons.

Generally, voltages VD and VR are set to around 10V, and voltage VG is set to around 2V. When such a voltage setting is made, 4 × 10
^In order to obtain an output signal of the source follower amplifier 9 as 30 mV as a detection output of ^three electrons, the capacitance CFD becomes 20 fF.
Need to be on the order. However, when the capacitance CFD is set to 20 fF
In this case, the amount of potential change of the source region 6 due to the background light at a room temperature of 350 K becomes about 8 V, and the ΨOG normally takes a value of about 5 V, so that the source region 6 is saturated. On the other hand, the amount of potential change of the source region 6 due to the background light at room temperature 250K is reduced to about 160 mV.

Therefore, a charge transfer device used in an infrared imaging device is required to have a large dynamic range.

The present invention has been made to solve such a problem, and provides a charge transfer device capable of increasing a dynamic range without increasing power consumption for signal charge detection. The purpose is to:

[0031]

SUMMARY OF THE INVENTION Charge transfer according to the present invention
The device is provided on a semiconductor substrate and
Signal charge in which a minute signal charge is superimposed on a simple background signal charge
A charge transfer layer for transferring the
A source region for receiving the signal charges transferred in the transfer layer;
The charge transfer layer is provided at a predetermined distance from the source region,
A drain region to which a predetermined voltage is applied, a source region,
A gate electrode located above the region between the drain region
When accumulating signal charges in the poles and the source region, a predetermined
Potential applying means for applying a clock pulse of
A power source of a first voltage with the potential of the stage and the source region as inputs
A source follower amplifier to which voltage is applied and a background signal
Source follower amplifier for at least part of the load
Operate in the non-linear region, and source small signal charges.
To operate the follower amplifier in the linear region, the first
A second voltage higher than the voltage of
Voltage applying means.

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

[0038]

[0039]

[0040]

[0041]

[0042]

[0043]

[0044]

According to the present invention, the second voltage applied by the voltage applying means to the drain region, higher than the first voltage supplied to the source follower amplifier, increases the power consumption of the source follower amplifier Therefore, the capacity of the source region can be increased without increasing the power consumption of the source follower amplifier, thereby increasing the dynamic range.

[0045]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

First Embodiment First, a first embodiment of the present invention will be described. FIG.
FIG. 2 is a schematic diagram illustrating a configuration of a charge transfer device according to a first embodiment.

The semiconductor substrate 1 made of a p-type Si semiconductor is
Electrically grounded. On this semiconductor substrate 1, a channel layer 2 extending in a predetermined direction is provided. This channel layer 2
Is an n-type buried channel layer, which is formed by ion implantation. On a part of the region of the channel layer 2, a plurality of electrodes 3 (only one terminal is shown) arranged along the direction in which the channel layer 2 extends are each disposed via an insulating film 4.

Further, an electrode 5 is arranged on the region of the channel layer 2 adjacent to the terminal electrode 3 via an insulating film 4.
Furthermore, in the region of the channel layer 2 adjacent below the electrode 5,
A source region 6 made of an n ⁺ -type impurity layer is provided.
This source region 6 is formed by ion implantation and functions as a floating diffusion.

A drain region 7 made of an n ⁺ -type impurity layer is provided in the region of the channel layer 2 at a predetermined distance from the source region 6 in the extending direction. This drain region 7 is formed by ion implantation. A first gate electrode 81 is arranged on the drain region side above the region between the source region 6 and the drain region 7 via the insulating film 4. Alternatively, the second gate electrode 82 is disposed on the source region side above the region between the source region 6 and the drain region 7 via the insulating film 4.

A control signal φC composed of a clock pulse is applied to the electrode 3 and a constant DC voltage OG is applied to the electrode 5.
Is applied. The first gate electrode 81 is supplied with a control signal φR1 composed of a clock pulse.
0, and a control signal φR2 composed of a clock pulse is applied to the second gate electrode 82 from the pulse signal application unit 80. The control signals φR1 and φR2 have the same high-level potential, and the low-level potential is such that the control signal φR2 is higher than the control signal φR1.
A constant DC voltage VR is externally applied to the drain region 7.

Source follower amplifier 9 includes a driving transistor 91 and a load transistor 92. Transistor 91 and transistor 92 are connected to power supply voltage V
D is connected in series between power supply node 93 receiving D and ground node 94 receiving the ground voltage. Transistor 91
Output node 95 is connected to a node between transistor and transistor 92. Output signal DO is output from output node 95.

The gate of transistor 91 is connected to source region 6 via an aluminum wiring, and the potential of source region 6 is applied to the gate. A constant DC voltage VG is applied to the gate of the transistor 92. Source follower amplifier 9 outputs from output node 95 output signal DO obtained by amplifying the potential of source region 6 applied to the gate of transistor 91.

Next, the operation will be described. FIG. 2 is a potential distribution diagram showing a potential distribution in the channel layer 2 between the electrode 3 and the drain region 7 in FIG. 1. In this potential distribution diagram, the potential is increased from the top to the bottom in the figure. Is getting higher. FIG. 3 is a timing chart showing waveforms of control signals φC, φR1, and φR2.

The operation of the charge transfer device of FIG. 1 will be described below with reference to FIGS. 1, 2 and 3.

First, as shown in FIG.
C, φR1, φR2 are simultaneously at high level VH
C, VHR1, and VHR2. When the control signal φC changes to the high level VHC, the channel potential under the electrode 3 changes to the high level ΔHC (see FIG. 2), and signal charges (electrons) are transferred into the channel under the electrode 3. The control signals φR1 and φR2 are at high levels VHR1 and VHR, respectively.
When HR2 is reached, both the channel potential under the first gate electrode 81 and the channel potential under the second gate electrode 82 become high level ΨHR (see FIG. 2), and the channel is turned on. Thereby, the drain region 7
Of the source region 6 is charged to a potential corresponding to the voltage VR.

Then, as shown in FIG.
R1 and φR2 are low level VLR1 and VLR2, respectively.
As a result, the channel potential under the first gate electrode 81 and the channel potential under the second gate electrode 82 become low levels ΨLR1 and ΨLR2, respectively (see FIG. 2), and the channel is turned off. At this time, part of the potential of the source region 6 is distributed to the capacitance existing between the source region 6 and the second electrode 82, and as a result, the channel potential slightly drops to VR1.

Then, as shown in FIG.
C becomes low level VLC, and the channel potential under the electrode 3 becomes low level ΔLC (see FIG. 2) lower than the channel potential ΨOG under the electrode 5. Therefore, the signal charges transferred into the channel below the electrode 3 are accumulated in the source region 6 through the channel below the electrode 5. As a result, the potential of the source region 6 decreases by the charge variation amount ΔVFD corresponding to the stored signal charges.

The potential variation ΔVFD is amplified by the source follower amplifier 9 and an output signal DO is output from the output node 95 as a detection result of the signal charge.

In the above charge transfer device, the low level of the control signal φR2 is higher than the low level of the control signal φR1. Thereby, the source region 6
When the signal charge is stored in the first gate electrode 82, the potential ΨLR2 below the second gate electrode 82 becomes higher than the potential ΨLR1 below the first gate electrode 81, and the channel below the second gate electrode 82 functions as a storage capacitor.

[0060] Therefore, if the charge to the source region 6 is accumulated, but only the capacitance CFD of the source region 6, the potential variation ΔVFD until VR1-ΨLR2 acts as a storage capacitor, the potential fluctuation exceeds VR1-[psi LR2 And the channel below the second gate electrode 82 functions as a storage capacitor. Assuming that the capacitance is CR, when the amount of potential fluctuation exceeds VR1-ΔLR2, the storage capacitance of the source region 6 becomes CFD + CR. Therefore, the ratio of the potential variation ΔVFD of the source region 6 to the accumulated signal charge amount is equal to the potential variation ΔV
When FD exceeds VR1-ΔLR2, it becomes smaller than when it does not exceed VR1-ΔLR2.

FIG. 4 shows such a relationship. FIG. 4 is a graph showing the relationship between the accumulated signal charge amount and the potential variation amount of the source region 6. The vertical axis represents the potential variation amount ΔVFD, and the horizontal axis represents the signal charge amount. Indicated by The dashed line in FIG. 4 shows the relationship when only the source region 6 functions as a capacitor as in the conventional case.

As shown in FIG. 4, only the capacitance CFD of the source region 6 functions as a storage capacitor until the potential variation ΔVFD becomes VR1-ΔLR2 due to accumulation of signal charges, and the signal of CFD (VR1-ΔLR2) is obtained. The amount of charge is accumulated. Then, the potential variation ΔVFD is VR1-ΨLR2.
Is exceeded, the capacitance CFD of the source region 6 and the capacitance CR below the second gate electrode 82 serve as storage capacitors, and until the potential variation ΔVFD becomes VR1-ΨOG, (CFD
+ CR) (ΨLR2-ΨOG) + CFD (VR1-ΨL)
The signal charge amount of R2) is accumulated.

As described above, the relationship between the signal charge amount and the potential change amount has a so-called knee characteristic, and the maximum signal charge amount that can be stored is increased as compared with the related art, and the dynamic range is increased.

Second Embodiment Next, a second embodiment of the present invention will be described. FIG.
FIG. 6 is a schematic diagram illustrating the configuration of a charge transfer device according to a second embodiment. In FIG. 5, components corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. Hereinafter, differences from the charge transfer device of FIG. 1 will be described.

An n ⁺ -type impurity layer 10 is formed in a part of the region between source region 6 and drain region 7 on the source region 6 side. A gate electrode 8 is arranged on a region between the source region 6 and the drain region 7 via the insulating film 4.
The gate electrode 8 is supplied with a control signal φR as a clock pulse from the pulse signal application unit 80.

Next, the operation will be described. FIG. 6 is a potential distribution diagram showing the potential in the channel layer 2 between the electrode 3 and the drain region 7 in FIG. 5. In this potential distribution diagram, the potential increases from the top to the bottom in the drawing. ing.

The operation of the charge transfer device shown in FIG. 5 will be described below with reference to FIGS. The basic operation of this charge transfer device is similar to that of the charge transfer device of FIG.

When the control signals φC and φR go high at the same time, signal charges are transferred into the channel below the electrode 3. Accordingly, the channel potential below the gate electrode 8 becomes high level, and the channel below the gate electrode 8 is turned on. Since the impurity layer 10 is formed below the gate electrode 8 as described above, when the channel is turned on, the potential ΔHR2 of the region where the impurity layer 10 is formed below the gate electrode 8 is increased Potential of the region other than 以外 H
It becomes higher than R1. Thereafter, the control signal φR is set to the low level, the channel potential below the gate electrode 8 is set to the low level, and the channel is turned off. At this time, the potential ΨLR2 of the region where the impurity layer 10 is formed also becomes higher than the potential ΨLR1 of the other region due to the influence of the impurity layer 10 due to the influence of the impurity layer 10.

After such a state, the signal charges transferred below the electrode 3 are accumulated in the source region 6 through the channel below the electrode 5.

In such a charge transfer device, when signal charges are accumulated in the source region 6, the channel potential under the gate electrode 8 is set to the potential ΨLR2 of the region where the impurity layer 10 is formed. Is higher than the potential ΨLR1, the channel on the source region 6 side under the gate electrode 8 becomes a new capacitance.

Thus, when signal charges are accumulated in source region 6, potential variation ΔVFD due to the signal charges is generated.
Is the capacitance CFD of the source region 6 until VR1-ΨLR2.
Only acts as a storage capacitor, but the potential variation ΔVFD is V
When R1-ΨLR2 is exceeded, the channel on the source region 6 side under the gate electrode 8 also functions as a storage capacitor in addition to the capacitor CFD. Therefore, the ratio of the potential variation ΔVFD of the source region 6 to the stored signal charge is smaller when the potential variation ΔVFD exceeds VR1−ΔLR2 than when it does not exceed VR1−ΔLR2.

The relationship between the signal charges stored in the charge transfer device and the amount of potential variation ΔVFD of the source region 6 is the same as the graph shown in FIG. Thus, the second
In the charge transfer device according to the embodiment, similarly to the charge transfer device according to the first embodiment, the maximum signal charge amount that can be accumulated is larger than in the related art, and the dynamic range is increased.

In the second embodiment, the impurity layer 10 is provided below the gate electrode 8 to form a capacitor.
However, the thickness of the insulating film 4 on the source region 6 side under the gate electrode 8 may be larger than the thickness of the insulating film 4 on the drain region 7 side.

Third Embodiment Next, a third embodiment of the present invention will be described. FIG.
FIG. 9 is a schematic diagram showing a configuration of a charge transfer device according to a third embodiment. In FIG. 7, components corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. Hereinafter, differences from the charge transfer device of FIG. 1 will be described.

On the region between source region 6 and drain region 7, gate electrode 8 is arranged via insulating film 4. The gate electrode 8 is supplied with a control signal φR, which is a clock pulse, from the pulse signal application unit 80. Further, a constant voltage VR1 higher than the power supply voltage VD of the source follower amplifier 9 is supplied from the voltage application unit 70 to the drain region 7.
Is applied to

Next, the operation will be described. In this charge transfer device, the basic operation is the same as that of the charge transfer devices of the first and second embodiments, except that the channel layer 2 under the gate electrode 8 does not work as a capacitor and only the source region 6 Acts as a capacitor and accumulates the transferred signal charges. The feature of this charge transfer device is that the input / output characteristics of the source follower amplifier 9 have a relationship as shown in FIG.

FIG. 8 shows the relationship (input / output characteristics) between the input potential of the source follower amplifier 9 as the gate potential of the transistor 91 and the output potential of the source follower amplifier 9 as the potential of the output signal DO at the output node 95. FIG. 4 is a graph showing the relationship between the output potential on the vertical axis and the input potential on the horizontal axis.

Transistor 9 of source follower amplifier 9
Each of the devices 1 and 92 needs to operate in a saturation region where the input / output characteristics are linear. However, when the input potential of the source follower amplifier 9 becomes equal to or higher than the sum (VD + Vth) of the power supply voltage VD and the threshold voltage Vth, the transistor 91
Operate in the linear region, and the output potential is clipped. Further, the gain coefficient of the transistor 91 is β, and the power supply current is I _D
, The input potential is VG + (2I _D / β) ^1/2
Below, the output potential becomes equal to the voltage VG and the threshold voltage Vt.
h (VG−Vth) or less. As a result, the transistor 92 operates in the linear region, the input / output characteristics of the source follower amplifier 9 become non-linear, and the gain of the source follower amplifier 9 decreases.

Therefore, when the input potential is ΔΔ in FIG.
When it is within the range of V _IN , the transistors 91 and 92 each operate in the saturation region, and the input / output characteristics of the source follower amplifier 9 become linear.

When the charge transfer device having the source follower amplifier 9 having such input / output characteristics is used for an infrared imaging device, the voltage V applied to the drain region 7 is different from that of the prior art.
Assuming that R is equal to the power supply voltage VD of the source follower amplifier, when the variation ΔV _BG of the signal charge due to the background light is large, the variation of the potential variation ΔV _S of the signal charge due to the subject superimposed on this potential variation ΔV _BG The possibility that the range of the input potential falls within the non-linear region of the input / output characteristics of the source follower amplifier 9 increases.

However, in the charge transfer device according to the third embodiment, since the voltage VR1 applied to the drain region 7 is higher than the power supply voltage VD (for example, higher than VD + Vth), the signal charge of the subject is reduced. The range of the potential variation ΔV _S falls within the linear region (ΔV _IN ) of the input / output characteristics of the source follower amplifier 9. This makes it possible to appropriately linearly amplify the potential variation ΔV _S due to the subject. In this case, the region of the potential variation [Delta] V _BG by background light is within the scope of the non-linear region of the input-output characteristics of the source follower amplifier 19, the potential variation [Delta] V _BG signal charges due to the background light, infrared imaging apparatus There is no particular problem since the signal is unnecessary for the device.

As described above, in the charge transfer device according to the third embodiment, the voltage VR1 applied to the drain region 7 is set to a voltage higher than the power supply voltage VD of the source follower amplifier 9, so that the source when signal charges are accumulated. The potential of the region 6 becomes higher than the conventional potential, and the capacity increases accordingly.
Thereby, the dynamic range can be increased without increasing the power consumption of the source follower amplifier 9.

When the charge transfer device according to the third embodiment is used for an infrared imaging device, the voltage VR1 may be constant when the background temperature is substantially constant. However, when the background temperature changes, the voltage VR1 is changed according to the background temperature. Alternatively, the voltage VR1 may be changed.

In the first to third embodiments, the charge transfer device for transferring electrons as signal charges has been described. However, the present invention is not limited to this, and holes may be transferred as signal charges. The configuration may be any. As described above, in the charge transfer device that transfers holes as signal charges, the conductivity type of each semiconductor layer in the first to third embodiments is reversed, and the potential of a signal applied to each electrode is reversed. The device having such a configuration can be realized by
The same effect as that of the device for transferring electrons as signal charges can be obtained.

The present invention is not intended to be applied to an infrared imaging apparatus, but is applicable to any imaging apparatus which has a large background signal and detects minute signal charges superimposed thereon. It can be applied to anything.

[0086]

According to the present invention, therefore, a capacitance is formed below the second gate electrode when the absolute value of the potential of the source region becomes smaller than the absolute value of the potential under the second gate electrode. . That is, the capacity for storing signal charges, which are electrons or holes, is the sum of the capacity of the source region and the capacity formed under the second gate electrode. Therefore, the dynamic range can be increased without increasing the power consumption for detecting the signal charge.

Further, according to the present invention, in a region between the source region and the drain region, the absolute value of the potential of the source region is lower than the partial region adjacent to the source region. Is formed by the potential setting means. This allows
The capacitance for accumulating signal charges, which are electrons or holes, is the sum of the capacitance of the source region and the capacitance formed under the partial region. Therefore, the dynamic range can be increased without increasing the power consumption for detecting the signal charge.

Further, according to the present invention, since the second voltage applied to the drain region by the voltage applying means is higher than the first voltage supplied to the source follower amplifier, the capacity of the source region increases, The dynamic range increases. When the dynamic range is increased in this manner, the first voltage supplied to the source follower amplifier can be kept constant, so that the dynamic range can be increased without increasing the power consumption of the source follower amplifier. . In addition, for example, when applied to an infrared imaging device that simultaneously handles a large amount of signal charge due to background light and a signal charge due to a temperature difference between the subject and the background, the dynamic range is large, so that the source follower amplifier is connected between the subject and the background. This is advantageous because it can be linearly amplified centering on the region of the amount of change in signal charge due to the temperature difference.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a configuration of a charge transfer device according to a first embodiment.

FIG. 2 is a potential distribution diagram in a channel layer of the charge transfer device according to the first embodiment.

FIG. 3 is a timing chart showing waveforms of control signals of the charge transfer device according to the first embodiment.

FIG. 4 is a graph showing the relationship between the amount of signal charge stored in the charge transfer device according to the first embodiment and the amount of potential change in the source region.

FIG. 5 is a schematic diagram illustrating a configuration of a charge transfer device according to a second embodiment.

FIG. 6 is a potential distribution diagram in a channel layer of a charge transfer device according to a second embodiment.

FIG. 7 is a schematic diagram illustrating a configuration of a charge transfer device according to a third embodiment.

FIG. 8 is a graph showing input / output characteristics of a source follower amplifier of the charge transfer device according to the third embodiment.

FIG. 9 is a schematic diagram showing a configuration of a conventional charge transfer device.

FIG. 10 is a potential distribution diagram in a channel layer in a conventional charge transfer device.

FIG. 11 is a timing chart showing waveforms of a control signal and an output signal in a conventional charge transfer device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Channel layer 6 Source region 7 Drain region 8 Gate electrode 9 Source follower amplifier 10 Impurity layer 70 Voltage application part 80 Pulse signal application part 81 First gate electrode 82 Second gate electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/762 H01L 21/339 H04N 5/335

Claims (1)

(57) [Claims] A semiconductor substrate provided on the semiconductor substrate and capable of reducing a large background signal charge;
A charge transfer layer for transferring a signal charge on which a small signal charge is superimposed ; a source region provided in the charge transfer layer, for receiving the signal charge transferred in the charge transfer layer; A drain region provided at a predetermined distance from the source region and to which a predetermined voltage is applied, and an upper part of a region between the source region and the drain region
When accumulating the signal charges in the source region and the gate electrode ,
And potential applying means for applying a clock pulse potential to the gate electrode, an input potential of the source region, the power collector of the first voltage
A source follower amplifier to which pressure is applied, and the source for at least a part of the background signal charge.
Operate the follower amplifier in the nonlinear region, and
The source follower amplifier has a linear
The second voltage higher than the first voltage so as to operate in the
Voltage applying means for applying the voltage of
A charge transfer device.