JP3028569B2 - Input buffer circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly, to a circuit configuration of an input buffer circuit.

[Conventional technology]

At present, TTL input integrated circuits are frequently used in various electronic devices.

For this reason, even with a CMOS integrated circuit whose internal operation swings fully between the power supply potential and the ground potential, the standard product
In order to maintain input level compatibility with a TTL input integrated circuit, it is common to provide an input buffer circuit in the input section and design so that TTL input is possible.

However, for TTL input, the high level of the input is set to 2
Normally, it is set to V or higher, and the low level is set to 0.8 V or lower.

For this reason, the input buffer circuit is often designed so that its logical threshold value is about 1.4 V, and generally, the operation margin with respect to the pulse amplitude is very narrow.

For this reason, in the input buffer circuit, especially in the input first stage, the internal logic is inverted by noise entering the power supply or the ground, and the integrated circuit including the input buffer circuit often malfunctions.

Note that the above-described noise is likely to occur when relatively large charges move instantaneously, such as when the output of the integrated circuit transitions.

Conventionally, an input buffer circuit of an input level compensation type has been used in order to prevent the malfunction of the integrated circuit due to the above-mentioned noise.

FIG. 5 shows an example of a conventional input level compensation type input buffer circuit (hereinafter referred to as an input buffer circuit).

As shown in FIG. 5, a conventional input buffer circuit has a CM
A PMOS transistor P ₁ and an NMOS transistor N ₁ forming an OS inverter, and PMOS transistors P ₃ and P ₂ and an NMOS connected in series between a power supply terminal 1 and a ground terminal 2.
It comprises transistors N ₂ and N ₃ and an inverter 3.

Hereinafter, the operation of the input buffer circuit will be described.

In FIG. 5, first, consider the case excluding the PMOS transistor P ₃ and P ₂ and NMOS transistor N ₂ and N _3.

In this case, the input buffer circuit is a two-stage series connection of a simple CMOS inverter, and its logical threshold V
_thM is designed with a target of about 1.4 _V as described above.

Next, consider the case where PMOS transistor P ₂ and P ₃ and NMOS transistor N ₂ and N ₃ are added.

In this case, the input A _i is the high level input to the input terminal 4, that is, when the output A _O appearing on the output terminal 5 is high, PMOS transistor P ₃ is turned off, NMOS transistor
N ₂ turns on.

Therefore, at this time, the logical threshold value determined by the inverter 3 and the pseudo inverter composed of the PMOS transistor P _{1 and the} NMOS transistors N ₁ , N ₂ and N ₃ is _larger than the logical threshold value V _thM described above. Shift lower. Hereinafter, this logical threshold is referred to as V _thL .

Conversely, a low level input A _i, i.e., when the output A _O is low level, the NMOS transistor N ₂ is turned off, PMOS transistor P ₂ is turned on, the logic threshold value of the input buffer circuit, the above-mentioned Shift to a higher _level than the logical threshold value V _thM . Hereinafter, this logical threshold is referred to as V _thH .

 FIG. 6 summarizes the above description.

That is, the conventional input buffer circuit shown in FIG.
Sixth, as shown in the figure, for the case where input A _i is shifted to the low level → high level, the logic threshold higher V
_thH next, when the input A _i is changed to the high level → low level, the logic threshold becomes lower V _thL. That is, the input / output characteristics have hysteresis.

In the conventional input buffer circuit, since the input / output characteristics have the above-described hysteresis, the operation margin for the power supply sink and the floating of the ground is widened, so that a malfunction due to noise or the like hardly occurs.

The width of the hysteresis (V _thH −V _thL ) is mainly determined by the PMOS
Transistors P ₁ and P ₂ and NMOS transistors N ₁ and N ₂
Can be determined by

[Problems to be solved by the invention]

As described above, in the conventional input buffer circuit, the operation margin for noise and the like is widened by giving hysteresis to the input / output characteristics.

In this case, the logical threshold value of the input buffer circuit has a width of (V _thH −V _thL ) in terms of DC.

Therefore, in this input buffer circuit, the input level is V
_An input _{equal to} or higher than _thH is determined to be a high input, while an input equal to or lower than _VthL is determined to be a low input, so that a DC-like operation margin is reduced.

In other words, the conventional input buffer circuit is essentially a DC
It is intended to improve the operation margin for AC input such as noise at the expense of the operation margin for typical input.

For this reason, the following problems may occur in the conventional input buffer circuit described above.

Now, in FIG. 5, for example, when the input A _i is at a high level,
That is, A _O is at a high level.

At this time, the logic inversion occurs in the interior of the input buffer circuit to the noise enters a power or ground, the output A _O goes low, PMOS transistor P ₃ is turned on, NM
Since OS transistor N ₃ is turned off, the logical threshold of the input buffer circuit, shifts in V _thH from V _thL.

Even if the input A _i has occurred internal logic inversion when in a low level, similar shifts to V _thL logic threshold from V _thH in this case.

That is, in the conventional input buffer circuit shown in FIG.
The operating margin is large when noise enters the power supply or ground, but once a malfunction occurs, the operating margin becomes smaller than an input buffer circuit that does not compensate for the input level. Happens.

In order to avoid this, it is effective to increase the width of the hysteresis (V _thH −V _thL ) in FIG. 6 so that the shift of the logic threshold is unlikely to occur even when noise enters. , Which means that the higher logical threshold
Since V _thH is made higher and the lower logic threshold V _thL is made lower, as a result, the margin for the DC-like input level is further sacrificed.

[Means for solving the problem]

According to the input buffer circuit of the present invention, the output is fed back to the input level compensating circuit, so that the input / output characteristics have a high logical threshold when the input transitions from a low level to a high level, and a high level from a high level to a low level. The output is fed back to the input level compensating circuit section via a delay circuit having a low-pass filter function in an input buffer circuit of a type in which a hysteresis is applied so that the logical threshold value when the transition to It is characterized by the following.

Furthermore, an input buffer circuit according to a second aspect of the present invention is the input buffer circuit according to the first aspect, wherein the input buffer circuit comprises:
A signal transition detection circuit is provided.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In the first embodiment shown in FIG. 1, in the conventional input buffer circuit shown in FIG. 5, the output of the inverter 3, to have been directly input to the gate of the PMOS transistor P ₃ and the NMOS transistor N ₃ On the other hand, they are input to the gates of the respective MOS transistors via the positive-phase delay circuit 6.

The delay circuit 6 is essentially a circuit that operates as a low-pass filter that cuts short pulse signals, and is most commonly configured with a series circuit of resistors and capacitors and an even number of stages of inverters.

 Next, the operation of this embodiment will be described.

FIGS. 2 (a) and 2 (b) show the case where the internal logic is inverted by noise entering the power supply or the ground in the input buffer circuit of the present embodiment shown in FIG.
FIG. 3 is a diagram showing a signal waveform inside the input buffer circuit.

Figure 2 (a), when input A _i to the input buffer circuit is at high level, that is, when the output A _O is high, because the noise enters during the time T ₀ through T _1, the The internal logic of the input buffer circuit is inverted, and the input of the inverter 3 which should always be at the low level during normal operation
Shows a state in which the pulse is temporarily inverted and a pulse is generated.

In this state, the output A _O is the input ▲ ▼ of the inverter 3
Is temporarily inverted to the low level.

At this time, the PMOS transistor P ₃ and the NMOS transistor N ₃
The output D _O of the delay circuit 6 as the input to the gate, the output A _O
Is temporarily reduced due to a pulse-like decrease in the level of the signal A. In this case, since the pulse generated at the output A _O is cut by the delay circuit 6, the pulse of the signal D _O is longer than the pulse of the signal A _O. Appears relaxed, delayed by t _d1 . Or, the potential of the D ₀ does not change at all.

That is, while noise time internal logic is inverted occurring T ₀ through T _1, there is no change in the gate potential of PMOS transistor P ₃ and the NMOS transistor N _3, or so small, The logical threshold value of the input buffer circuit does not shift during the time when noise occurs.

Figure 2 (b), when a low level input A _i to the input buffer circuit, i.e. the output A _O is low level, shows a state in which happened malfunction due to noise.

Since the basic operation is the same as that of FIG. 2A except that the waveforms of the signals are reversed, detailed description is omitted.

 Next, a second embodiment of the present invention will be described.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In the second embodiment shown in Figure 3, in the first embodiment shown in FIG. 1, the output D _O of the delay circuit 6, is directly input to the gate of the PMOS transistor P ₃ and the NMOS transistor N ₃ On the other hand, it is input to each gate via the low transition detection circuit 7 and the high transition detection circuit 8.

Additional row transition detection circuit 7, when the output D _O of the delay circuit 6 is changed from the high level to the low level, detects this low-pulse to occur, Moreover, the high transition detection circuit 8,
When the output D _O of the delay circuit 6 is changed from the low level to the high level, a circuit for generating a high pulse detects this.

These circuits can be realized by the same circuit as an address transition detection circuit generally used for an integrated circuit.

 Hereinafter, the operation of the present embodiment will be described.

FIG. 4 is a diagram showing signal waveforms inside the present embodiment.

FIG. 4 also shows a signal waveform of a data output from an external circuit (not shown) activated by a signal from the input buffer circuit for easy understanding. .

In Figure 4, when the input A _i is shifted from the high level to the low level, delayed by the delay time t _d2, the output D _O of the delay circuit 6 is down from the high level to the low level, the data output of the external circuit is changed.

At this time, the row transition detection circuit 7 outputs the output D _{O of the} delay circuit 6.
By detecting the level transitions of the so generates a low pulse of the pulse width (T ₃ -T _2), the gate input T _LO of the PMOS transistor P ₃ is reduced during the time T ₂ through T _3, PMOS transistors P
₃ turns on during this time.

On the other hand, at this time, since the output T _HO high transition detection circuit 8 holds the low level no change, NMOS transistor N ₃ is turned off.

Thus, during the time T ₂ through T _3, the logic threshold value of the input buffer circuit, as shown in FIG. 4, the V _thH.

Then, the input A _i is the transition from the low level to the high level, the output D _O of the delayed delay circuit 6 rises from the low level to the high level, the data output of the external circuit is changed.

At this time, the high transition detection circuit 8 outputs the output D _{O of the} delay circuit 6.
By detecting the level transitions of the so generates a high pulse of the pulse width (T ₅ ~T _4), increases during the gate input of the NMOS transistor N ₃ is a time T ₄ through T _5, the NMOS transistor N ₃ during this time Turn on.

On the other hand, at this time, no change in the output T _LO of the row transition detection circuit 7, since holding the high level, PMOS transistor P ₃ is turned off.

Accordingly, the logical threshold during time T ₄ through T _5, as shown in FIG. 4, the V _thL.

That is, in the circuit configuration of FIG. 3, the delay time of the delay circuit 6 and the pulse width of the output _TLO of the low transition detection circuit 7 and the pulse width of the output _THO of the high transition detection circuit 8 are adjusted.
As shown in Figure 4, the input A _i transits to a low level, while the data output transitions, the logic threshold of the input buffer circuit holds the V _thH, also the input A _i is changed to the high level Thus, the logical threshold value during the transition of the data output can be held at V _thL .

Furthermore, the above-mentioned time T ₂ through T ₃ and T ₄ through T ₅ other times, i.e., during the time T ₃ through T _4, the output T of the row transition detector 7
_LO is at a high level, and the output T _HO of the high transition detection circuit 8 is output.
Is low level, the PMOS transistor P ₃ and the NMOS transistor
Transistor N ₃ are both turned off.

Therefore, in this case, this input buffer circuit is equivalent to an input buffer circuit that does not compensate the input, and
The logical threshold value is V _{thM as} shown in FIG.

Summarizing the above, according to the circuit configuration of FIG. 3, during the transition period of data output where noise is likely to occur, the logical threshold value is shifted in a direction to increase the margin during normal operation,
By holding, malfunction due to noise can be suppressed.

On the other hand, in other periods, the operating margin for the DC-like input level is deteriorated by having the same logical threshold value as the logical threshold value of the input buffer circuit of the type that does not compensate the input level. Can be prevented.

〔The invention's effect〕

As described above, according to the present invention, according to the input / output characteristics, the logical threshold when the input transitions from low level to high level is high, and the logical threshold when the input transitions from high level to low level is By providing a delay circuit having a low-pass filter function for an input buffer circuit having a low hysteresis, even when the internal logic is inverted in the input buffer circuit, the internal logic is inverted. If the time is within the time that can be cut by the delay circuit, this input buffer circuit can maintain the logical threshold value in the normal operation and operate stably without causing a malfunction.

Further, according to the second aspect of the present invention, by providing a signal transition detection circuit between the delay circuit and the input level compensating circuit section, the same effect as described above can be obtained during the operation period of the signal transition detection circuit. In other periods,
It has the same logic threshold value as the input buffer circuit whose input level is not compensated, and has an effect that it is possible to prevent the margin for the DC input level from deteriorating.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIGS. 2 (a) and (b) are diagrams showing internal signal waveforms when noise occurs in the first embodiment. FIG.
FIG. 4 is a diagram showing signal waveforms during the operation of the second embodiment, FIG. 5 is a circuit diagram showing a conventional input buffer circuit, and FIG. 6 is a circuit diagram showing a conventional input buffer circuit. FIG. 3 is a diagram illustrating input / output characteristics of an input buffer circuit. 1 ... power supply terminal, 2 ... ground terminal, 3 ... inverter, 4
... input terminal, 5 ... output terminal, 6 ... delay circuit, 7 ... low transition detection circuit, 8 ... high transition detection circuit.

Claims (2)

(57) [Claims] An output is fed back to an input level compensating circuit, so that the input / output characteristic has a high logic threshold when the input transitions from a low level to a high level, and transitions from a high level to a low level. An input buffer circuit of a type having a hysteresis such that a logical threshold value becomes lower when the output is fed back to the input level compensation circuit section via a delay circuit having a low-pass filter function. Input buffer circuit. 2. The input buffer circuit according to claim 1, wherein a signal transition detection circuit is provided between said delay circuit and said input level compensation circuit section.