JP3028938B2 - Layout method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout method for a semiconductor integrated circuit, and more particularly to a layout method for a semiconductor integrated circuit having a process for reducing clock skew.

[0002]

2. Description of the Related Art Semiconductor integrated circuits (hereinafter referred to as LSIs)
In this case, one clock signal or a plurality of clock signals having different phases are inputted, and this clock signal is distributed to each flip-flop in the LSI, and in synchronization with the clock signal, various operations, decoding and memory are performed. Performs operations such as read and write. Here, if the wiring length from the distribution source of the clock signal to each supply destination is different, clock skew occurs, and the arrival timing of the clock signal to each supply destination is shifted. When the clock skew increases, an erroneous signal is captured by a flip-flop, or an unnecessary whisker-like pulse is generated at the output of the logic gate, and the entire LSI may malfunction. As described above, in a clock synchronous type LSI, the performance such as the operation speed is determined by the magnitude of the clock skew.

Therefore, in a conventional LSI, clock tree synthesis (hereinafter simply referred to as CTS) is used to make a clock line a tree structure of a high-drive buffer to minimize the relative skew of clock input to each block. There are attempts to curb.

FIG. 11 is a schematic diagram showing a logic integrated circuit (semiconductor integrated circuit) wired by CTS. LSI
The internal logic area 13 has a buffer circuit 12a connected to a clock signal input terminal 11 provided outside the logic area 13 and a buffer circuit 12a sequentially doubling the buffer circuit 12a.
Buffer circuits 12b, 12c, 12d,... Cascaded so as to increase by a factor of ²ⁿ . The internal logic area 13 is further provided with a plurality of flip-flops 15 respectively connected to the plurality of buffer circuits 12d. As described above, in the LSI, from the buffer circuit 12a to the terminal flip-flop 15, the buffer circuits 12b to 12b
d and the like are connected in a tree by the clock net 10. For this reason, the clock distribution system is designed so that the load capacity of the buffer circuits 12a to 12d in each stage, that is, the wiring capacity, the input capacity of the next-stage gate, and the like match.

FIG. 12 is a flowchart showing a layout method when the LSI described with reference to FIG. 11 is created.
This layout method is based on the computer aided design (Computer Ai
dedDesign) (hereinafter simply referred to as CAD). First, a circuit design that determines a transistor-level circuit configuration and element characteristics that satisfy given circuit specifications is executed, and an arrangement step of initially arranging each element in the internal logic area 13 is performed (steps S1 and S2). Next, a clock net dividing process for distributing the clock net 10 in a tree shape is performed in accordance with the logical connection information of the designed circuit, and the buffer circuits 12a to 12a-1 are set so that the load capacities of the respective stages match.
2d is inserted into the logical connection information of the circuit (step S3,
S4).

Next, the inserted buffer circuits 12a-1
2d is placed in the internal logic area 13 and the clock net 1
0 is connected to the buffer circuit 1 of each stage by equal-length wiring.
The clock skew is reduced by matching the load capacities of 2a to 12d (steps S5 and S6). In addition, wiring where necessary signal lines are routed in the circuit, where satisfactory wiring is no longer made due to changes in the arrangement of elements or requests for logical inversion, etc.
That is, it is checked whether or not there is an unwired portion (steps S7 and S8). As a result, the process from step S2 is repeated as long as there is an unwired portion. When there are no unwired portions, the process proceeds to step S9 to create mask pattern data based on the layout data.

[0007] Another logical integrated circuit based on a technique using CTS is described in Japanese Patent Application Laid-Open No. Hei 5-159080. FIG. 13 is a schematic diagram showing a logic integrated circuit described in the publication. In this logic integrated circuit, the internal logic area 13
Are divided into a plurality of blocks having the same area as each other. Each of the divided blocks has an input terminal 11 for inputting a clock signal from a clock generation source CL.
And a plurality of stages of buffer circuits 1 connected to the input terminal 11
4 are provided independently of each other.
This clock distribution system is configured in a tree shape that branches from a clock supply source to an end circuit that is each supply destination. The wiring between the buffer circuits 14 in each stage is designed so that the length and the capacitance are equal to each other, and the number of fan-outs in the buffer circuits 14 in each stage is the same.

FIG. 14 is a flowchart showing a procedure of a layout method for producing the logic integrated circuit of FIG.
Each processing step in this flowchart includes step S
10 and S11 are common to steps S1 and S2 described in FIG. 11, and steps S13 to S19 are steps S3 to S9.
However, the difference is that the chip block dividing step is performed between the arrangement step and the clock net dividing step. That is, when laying out the logic integrated circuit described in the above publication, after arranging each element in the internal logic area 13, the internal logic area 13 is divided into arbitrary blocks.

[0009]

By the way, in the conventional layout method described with reference to FIGS. 12 and 14, respectively, the process of reducing the clock skew is performed simultaneously during the placement step and the wiring step. (Step S3
To S6, steps S12 to S16). For this reason, when there is an unwired portion, the process of reducing the clock skew must be repeated at the same time as the wiring for the wiring, which causes an increase in the time required for layout design.

In view of the above, it is an object of the present invention to provide a layout method of a semiconductor integrated circuit which can shorten the time required for layout design and make the design work more efficient when creating layout data by computer-aided design. And

[0011]

In order to achieve the above object, a layout method of a semiconductor integrated circuit according to the present invention is directed to a layout method of a semiconductor integrated circuit for creating layout data by computer-aided design. An arranging step of arranging an element in a logical region, a wiring step of arranging a desired signal line to the element, and dividing the internal logical region into a plurality of blocks having substantially the same area as each other. And a clock skew reduction step of reducing a clock skew by adjusting a delay amount at the time of transmitting a clock signal for each block depending on the number of delay elements to be performed. Here, the number of delay elements attached to each divided block includes zero.

In the layout method of the semiconductor integrated circuit according to the present invention, the clock skew can be reduced by adjusting the number of delay elements for each of the divided blocks. Can be made independent of the placement step and the wiring step. For this reason, even when there is an unwired portion, only the placement / wiring process may be repeated separately from the clock skew reduction process, so that the time required for layout design can be reduced.

Preferably, the clock skew reduction step is a step of, following the placement step and the wiring step, placing a flip-flop and a delay element group corresponding to the flip-flop in a group in each of the divided blocks. And calculating, based on a block closest to an input terminal for supplying a clock signal to the semiconductor integrated circuit, a delay value that reduces a delay amount as a block is further away from the reference block, and based on the calculation result, calculates the delay value. Adjusting the number of delay elements provided in the element group. In this case, the number of delay elements can be adjusted while treating the flip-flop and the delay element group as one group, so that the process of reducing clock skew becomes easy and quick.

[0014] More preferably, the clock skew reduction step further includes a step of replacing an unnecessary delay element among the delay elements arranged in each block with a wiring pattern. In this case, the process of reducing clock skew becomes simpler.

Further, the clock skew reduction step includes the following:
Prior to the arranging step and the wiring step, a block closer to an input terminal for supplying a clock signal to the semiconductor integrated circuit is used as a reference, and a delay value is calculated such that a block further away from the reference block has a smaller delay amount. It is also a preferable embodiment to include a step of arranging a delay element group in which the number of delay elements is adjusted based on the calculation result in each block. in this case,
Since it is sufficient to dispose the delay element groups, for example, one by one in the divided blocks, it is possible to further reduce the influence of the arrangement / wiring process on the wiring property and the accommodation.

It is preferable that the arranging step includes a step of arranging, in each of the blocks, an element corresponding to the delay element group arranged in the clock skew reducing step. In this case, the work of creating the layout data becomes easier.

Preferably, the clock skew reducing step is a block subsequent to the arranging step and the wiring step, which is based on a block closest to an input terminal for supplying a clock signal to the semiconductor integrated circuit and which is distant from the reference block. A step of calculating a delay value with which the delay amount is reduced as much as possible, and inserting a delay element group in which the number of delay elements is adjusted based on the calculation result between the elements arranged in each block.

In this case, after the placement / wiring process is completed, the delay element group is inserted into each block in accordance with the result of the calculation of the delay value. , A delay element group can be inserted. For this reason, it is possible to further reduce the influence on the wiring property and the accommodation property in the arrangement / wiring step.

[0019]

The present invention will be described in more detail with reference to the drawings. FIG. 1 shows an LSI according to a first embodiment of the present invention.
It is a top view which shows a chip typically. LSI chip 21
Has an external input terminal 31 for inputting a clock signal,
An I / O block cell region 22 is provided on the periphery of the chip.
The internal logic region 23 arranged inside the I / O block cell region 22 has a plurality of blocks 24 having the same area.
A to 24I.

FIG. 2 is a flow chart showing a procedure of a layout method for producing an LSI chip in the embodiment, and FIGS. 3 and 4 are LSIs according to this layout method.
It is a front view which shows the preparation process of a chip typically. The layout processing shown in the flowchart is based on the computer assisted design (C
AD).

In the present embodiment, the content of the clock skew reduction processing is different from the clock skew reduction processing in the conventional method described with reference to FIGS. 12 and 14, so that the clock skew reduction processing is performed from the placement step and the wiring step. This can be performed independently after the placement / wiring process.

That is, in the present embodiment, step S30
Then, a circuit design for determining a transistor-level circuit configuration and element characteristics satisfying the given circuit specifications is performed, and then a placement / wiring process A and a clock skew reduction process B are executed to evaluate the designed circuit. Redesign based on this.

In the arrangement / wiring step A, first, an arrangement step of initially arranging the buffer circuit 36 as an element in the internal logic area 23 is executed, and each of the buffer circuits 3
Then, a wiring step of connecting between the six by a clock net (signal line) 33 is performed. Next, it is checked whether or not there is a portion where satisfactory wiring has not been performed due to a change in the arrangement of elements or a request for logical inversion, that is, a portion in an unwired state (steps S31 to S33). As a result, if there is an unwired portion, the process returns to step S31 to repeatedly execute the placement process and the wiring process. If there is no unwired portion, the process proceeds to the clock skew reduction process B.

In the clock skew reduction processing B, first,
The internal logic region 23 of the LSI chip 21 is divided into a plurality of blocks 24A to 24I having the same area (Step S34). Next, as shown in FIG. 3, a flip-flop group 35 is provided for each of the divided blocks 24A to 24I.
And delay element group 34 corresponding to flip-flop group 35
Are grouped and arranged uniformly (step S3
5). Thereby, in each of the blocks 24A to 24I, the flip-flop group 35 and the delay element group 34 are connected, for example, one set to each of the buffer circuits 36 arranged and wired in advance in the arrangement / wiring step A. become.

Further, the block 24 closest to the external input terminal 31 for supplying a clock signal to the LSI chip 21
Based on A, the delay element group 34 is adjusted so that the delay amount decreases as the distance from the reference block 24A increases. In this adjustment, first, with reference to the block 24A, a delay value for the flip-flop group 35 arranged in each of the other blocks 24B to 24I is calculated. Based on the calculation result, the delay elements provided in the delay element group 34 are set such that the delay value of the delay element group 34 connected to the flip-flop group 35 of each of the blocks 24B to 24I is equivalent to the delay value in the block 24A. 34a is adjusted in block units. At this time, blocks 24A to 24I
The unnecessary delay element 34a in each of the above is replaced with a wiring pattern as shown in FIG. In the figure, in the reference block 24A, there are four delay elements 34a,
In the blocks 24B and 24D adjacent to 4A, the delay element 3
4a, the delay elements 34a in the blocks 24C, 24E, and 24G adjacent to the blocks 24B and 24D, respectively.
Are arranged two by two. Also, blocks 24C and 24
Blocks 24F and 24H adjacent to E and 24G respectively include one delay element 34a, and block 24I adjacent to blocks 24F and 24H includes zero delay element 34a.

As described above, in the clock skew reduction processing B, the reference block 24A and the other blocks 24B
The delay value of the delay element group 34 is adjusted for each block in consideration of replacing the wiring delay value added when the clock wiring is performed up to 24I with the delay element group 34. Thus, by adjusting the amount of delay at the time of transmitting a clock signal for each block according to the number of delay elements 34a attached to each block, from the clock signal distribution source to the flip-flop group 35 that is each supply destination. The clock skew in the internal logic area 23 is reduced by making the delay values equivalent.

Next, in step S38, mask pattern data is created based on the layout data.
In this case, first, the plotting is performed by a plotter to perform a check, and after confirming that there is no error in the designed mask pattern data, this data is converted into data for a mask manufacturing apparatus.

As described above, in the present embodiment, the arrangement / wiring process A in which the arrangement or wiring is likely to be requested to be changed by changing the arrangement of the elements or inverting the logic is unlikely to occur. The clock skew reduction process B used as a method is independent. Thus, when an unwired state in which satisfactory wiring cannot be obtained occurs, the object can be achieved by repeatedly performing only the arrangement / wiring step A separately from the clock skew reduction processing B. Therefore, according to the layout method of the present embodiment, when layout data is created by computer-aided design, the time required for the layout design can be shortened and the design work can be made more efficient.

According to the embodiment, the flip-flop group 35 included in the plurality of blocks 24A to 24I is provided.
And the delay element group 34 as one group to perform the clock skew reduction processing. Therefore, as compared with the case where the clock skew reduction processing is performed on a flip-flop basis, the processing is facilitated and the processing time can be reduced. Therefore, for example, it is particularly effective when a large-scale LSI chip having more than several thousands of flip-flops is produced.

Next, the second embodiment of the present invention will be described with reference to FIGS.
An embodiment will be described. FIG. 5 is a flowchart showing a procedure of a layout method for producing an LSI chip according to the embodiment, and FIGS. 6 and 7 are front views schematically showing a production process of the LSI chip by this layout method. The layout processing shown in the flowchart is performed by CAD.

Also in the present embodiment, the contents of the clock skew reduction processing are different from those of the conventional type. Thereby, the clock skew reduction processing can be performed before the placement / wiring step independently of the placement step and the wiring step. That is, in the present embodiment, the clock skew reduction process B ′ and the placement / wiring process A are sequentially performed after the circuit design is performed in step S40.

In the clock skew reduction processing B ', LS
As shown in FIG. 6, the internal logic region 23 of the I chip 21 is divided into a plurality of blocks 24A to 24I having the same area.
(Step S41). Next, with reference to the block 24A closest to the external input terminal 31 that supplies the clock signal to the LSI chip 21, a delay value is calculated such that a block farther from the reference block 24A reduces the delay amount. A delay element group 34 whose number of delay elements is adjusted based on the delay elements is arranged in each block. That is, the other blocks 24B to 24B are based on the block 24A.
The delay value for the flip-flop group 35 is calculated for each I. Further, based on the calculation result, each block 2
The delay element group 34 in which the number of the delay elements 34a is adjusted so that the delay values between 4A to 24I are equivalent is arranged in each of the blocks 24A to 24I (step S42).

Thus, in the standard block 24A, the delay element group 34 having four delay elements 34a, the block 2
In the blocks 24B and 24D adjacent to 4A, the delay element 3
A delay element group 34 having three 4a is arranged. Blocks 24C, 24C adjacent to blocks 24B and 24D, respectively.
In 24E and 24G, a delay element group 34 having two delay elements 34a is arranged. In blocks 24F and 24H adjacent to the blocks 24C, 24E and 24G, a delay element group 34 having one delay element 34a is arranged. In the block 24I adjacent to the blocks 24F and 24H,
A delay element group 34 having zero delay elements 34a is arranged. That is, the delay element group 34 is not arranged in the block 24I.

Next, in the arrangement / wiring step A, in the arrangement step of step S43, elements corresponding to the delay element group 34 are arranged in each of the blocks 24A to 24I. That is, elements other than the delay element group 34 such as the flip-flop group 35 and the buffer circuit 36 are arranged for each of the blocks 24A to 24I. Further, in the wiring step of step S44, each element is connected by the clock net 33 as determined. As a result, as shown in FIG.
In 4A, a buffer circuit 36 and a flip-flop group 35 are connected to a group of four delay elements 34a, and in blocks 24B and 24D, three delay elements 34a are used.
A buffer circuit 36 and a flip-flop group 35 are connected to the delay element groups 34. Block 24C, 2
In 4E and 24G, the delay element 34a has two delay element groups 3
4 and in the blocks 24F and 24H, the delay circuit 34a
6 and the flip-flop group 35 are connected to each other. In the block 24I, the buffer circuit 36 and the flip-flop group 35 are connected to the clock net 33 without the delay element group 34.

Next, in step S45, it is checked whether there is any unwired portion. As a result, if there is an unwired state, the process returns to step S43 to repeat the arrangement process and the wiring process. If there is no unwired portion, the process proceeds to step S46. In step S46, mask pattern data is created based on the layout data.

As described above, also in the second embodiment, the clock skew reduction processing B 'is performed in the arrangement / wiring step A.
, The time required for layout design can be reduced when layout data is created by CAD. In the present embodiment, the following effect is further obtained in addition to this effect. That is, since the placement / wiring step A is performed after the clock skew is reduced by the clock skew reduction processing B ′, the internal logic area 23
In the case where the blocks are divided into nine blocks 24A to 24I as shown in FIG. 6, it is sufficient to arrange nine delay element groups 34 at the maximum, and the influence on the wiring property and the accommodation in the arrangement / wiring step A is reduced. Can be.

Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 8 is a flowchart showing a procedure of a layout method for producing an LSI chip according to the present embodiment, and FIGS. 9 and 10 are front views schematically showing an LSI chip production process by this layout method. The layout processing shown in the flow chart
D.

Also in the present embodiment, the contents of the clock skew reduction processing are different from those of the conventional type. Thus, the clock skew reduction processing can be performed after the placement / wiring step independently of the placement / wiring step. That is, in the present embodiment, after the circuit design is performed in step S50, the clock skew reduction processing B ″ and the placement / wiring step A are sequentially performed.

In the arrangement / wiring process A, step S51
Thus, each of the blocks 24A to 24A in the internal logical area 23
As shown in FIG. 9, the delay element group 3
A flip-flop group 35 and a buffer circuit 36, which are elements other than 4, are arranged. Next, in step S52, each element is connected by the clock net 33 as determined. Further, in step S53, it is checked whether or not there is an unwired state. If there is an unwired state, the process returns to step S51 to repeat the placement step and the wiring step. If there are no unwired parts, the clock skew is reduced. Proceed to process B ".

In the clock skew reduction processing B ″, LS
As shown in FIG. 10, the internal logic region 23 of the I chip 21 is divided into a plurality of blocks 24A to 24I having the same area.
(Step S54). Next, based on the block 24A closest to the external input terminal 31, the flip-flop group 3 is set for each of the other blocks 24B to 24I.
5 is calculated. Further, based on the calculation result, the delay element group 34 in which the number of the delay elements 34a is adjusted so that the delay values between the blocks 24B to 24I are equivalent is inserted into each of the blocks 24A to 24I (step S55). As a result, the LSI chip 21
The state is the same as that of FIG. 4 in the embodiment. Then
In step S56, mask pattern data is created based on the layout data.

As described above, also in the third embodiment, the clock skew reduction processing B ″ is performed in the arrangement / wiring step A.
, The time required for layout design can be reduced when layout data is created by CAD. In the present embodiment, the following effect is further obtained in addition to this effect. That is, since the delay element group 34 is inserted into each of the blocks 24A to 24I after the placement / wiring step A, the block in which the flip-flop group 35 is not disposed is recognized, and the block in which the delay element group 34 does not need to be disposed is determined in advance. It is possible to recognize. Therefore, since the delay element group 34 can be inserted only into a necessary block, it is possible to reduce the influence on the wiring property and the accommodation in the arrangement / wiring step A.

By the way, C described in FIGS.
In the conventional layout method using the TS, the clock nets and the buffer circuits are increased, and the clock nets 10 must be wired so that the load capacity of the buffer circuits in each stage or each block connected in a tree shape matches. . For this reason, the load capacity is increased, the delay amount of the clock signal is increased, and the wiring length is increased, so that there are insufficient wiring channels required for the layout. On the other hand, according to the layout method of the present invention described in the first to third embodiments, it is not necessary to provide the wiring of the clock signal so that the load capacitance of the buffer circuit in each stage or each block matches. Therefore, since the clock net 33 does not need to be formed in a tree shape, the time required for wiring the clock signal is the same as the time required for the wiring of the normal data signal and the like, and the wiring length of the clock net 33 is shortened. The increase in the delay value of the signal can be minimized.

In the conventional layout method, when the clock nets 10 are connected in a tree-like manner and the number of flip-flops 15 to which clocks are supplied increases, the clock net 10 and the buffer circuits 12a to 12c necessary for the connection are provided.
12d and 14 increase to about twice or more of the normal connection method. Therefore, the power consumption when driving the buffer circuit is about 2
More than double. On the other hand, in the layout method of the present invention, since the clock net 33 does not need to be configured in a tree shape, the number of connected buffer circuits 36 can be reduced to less than half of the conventional case, and power consumption is reduced. be able to.

As described above, the present invention has been described based on the preferred embodiment. However, the layout method of the semiconductor integrated circuit of the present invention is not limited to only the above-described embodiment. Various modified and changed layout methods for a semiconductor integrated circuit are also included in the scope of the present invention.

[0045]

As described above, the layout method of a semiconductor integrated circuit according to the present invention shortens the time required for the layout design when the layout data is created by computer-aided design, and makes the design work more efficient. It has a remarkable effect that it can be performed.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing an LSI chip according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a procedure of a layout method for creating an LSI chip according to the first embodiment;

FIG. 3 is a front view schematically showing a process of manufacturing an LSI chip by a layout method in the first embodiment.

FIG. 4 is a front view schematically showing a process of manufacturing an LSI chip by a layout method in the first embodiment.

FIG. 5 is a flowchart illustrating a procedure of a layout method for creating an LSI chip according to a second embodiment of the present invention.

FIG. 6 is a front view schematically showing a process of manufacturing an LSI chip by a layout method according to a second embodiment.

FIG. 7 is a front view schematically showing a process of manufacturing an LSI chip by a layout method according to a second embodiment.

FIG. 8 is a flowchart illustrating a procedure of a layout method for creating an LSI chip according to a third embodiment of the present invention.

FIG. 9 is a front view schematically showing a process of manufacturing an LSI chip by a layout method according to the third embodiment.

FIG. 10 is a front view schematically showing a process of manufacturing an LSI chip by a layout method according to a third embodiment.

FIG. 11 is a schematic diagram showing a conventional logic integrated circuit wired by CTS.

FIG. 12 is a flowchart illustrating a layout method when creating the LSI described in FIG. 11;

FIG. 13 is a schematic diagram showing a conventional logic integrated circuit described in the official gazette.

FIG. 14 is a flowchart illustrating a layout method when the LSI described with reference to FIG. 13 is created.

[Explanation of symbols]

 Reference Signs List 21 semiconductor integrated circuit 23 internal logic area 24A to 24I block 31 input terminal 33 clock net 34 delay element group 34a delay element 35 flip-flop group 36 buffer circuit A arrangement / wiring step B, B ', B "clock skew reduction step

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50 H01L 21/82

Claims (6)

(57) [Claims] 1. A semiconductor integrated circuit layout method for creating layout data by computer-aided design, comprising: an arranging step of arranging an element in an internal logic area of the semiconductor integrated circuit; and wiring a desired signal line to the element. A wiring step; dividing the internal logic region into a plurality of blocks having substantially the same area as each other; adjusting the amount of delay in transmitting a clock signal for each block according to the number of delay elements attached to each block; And a clock skew reducing step of reducing a queue. 2. The clock skew reduction step, following the placement step and the wiring step, is a step of grouping and arranging a flip-flop and a delay element group corresponding to the flip-flop in each of the divided blocks. Calculating, with reference to a block closest to an input terminal for supplying a clock signal to the semiconductor integrated circuit, a delay value in which a delay amount is reduced as a block is further away from the reference block, and based on the calculation result, the delay element; 2. The method according to claim 1, further comprising the step of adjusting the number of delay elements provided in the group. 3. The semiconductor device according to claim 2, wherein the clock skew reduction step further includes a step of replacing an unnecessary delay element among the delay elements arranged in each of the blocks with a wiring pattern. Layout method for integrated circuits. 4. The clock skew reduction step precedes the arranging step and the wiring step, and is based on a block closest to an input terminal for supplying a clock signal to the semiconductor integrated circuit, and the block farther from the reference block is set. 2. The semiconductor integrated circuit according to claim 1, further comprising: calculating a delay value that reduces the delay amount, and arranging a delay element group in which the number of delay elements is adjusted based on the calculation result in each block. Layout method. 5. The semiconductor integrated circuit according to claim 4, wherein said arranging step includes a step of arranging, in each of said blocks, an element corresponding to said delay element group arranged in said clock skew reducing step. Layout method. 6. The clock skew reduction step, which follows the placement step and the wiring step, sets a block closer to an input terminal for supplying a clock signal to the semiconductor integrated circuit as a reference, and moves to a block farther from the reference block. Calculating a delay value that reduces the delay amount, and inserting a delay element group in which the number of delay elements is adjusted based on the calculation result between the elements arranged in each of the blocks. 2. The layout method for a semiconductor integrated circuit according to item 1.