JP3029396B2 - Semiconductor integrated circuit device and refresh timer cycle adjusting method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a refresh timer for generating a refresh signal for performing a refresh operation, such as a DRAM or a pseudo SRAM, and a method of adjusting the cycle of the refresh timer. It relates to measures to reduce the accompanying current consumption.

[0002]

2. Description of the Related Art In recent years, with the spread of portable information communication devices, there has been an increasing demand for memories such as DRAMs to reduce power consumption. In particular, in DRAMs, current consumption occurs due to refreshing even when data is retained, so reducing power consumption during data retention has become an important issue.

As shown in FIG. 14, data retention time in a memory cell of a DRAM has a temperature dependency.
The higher the temperature, the shorter the data retention time. Specifically, when the power supply potential VCC is 3.6 V, the data retention time is reduced by approximately 1 / 1.5 each time the temperature rises by 10 ° C., and the data retention time at 75 ° C. is 25 ° C. It is only 1/10 of. Therefore, in a DRAM having a self-refresh mode, an extremely short refresh cycle corresponding to the data holding time at a high temperature is set in order to guarantee data holding in a high temperature state. Therefore,
When used in a normal temperature state or a low temperature state, the refresh is performed more than necessary, so that unnecessary current is consumed correspondingly.

In the following, a refresh timer for outputting a refresh signal is made to have a temperature dependency.
A technology that reduces the refresh current at low temperatures by making the refresh cycle at low temperatures longer than at high temperatures is a technology developed by the ISSCC Digest of Technical Papers, p.
p.268-269, Feb. 1991. This technique will be described.

The cause of the limit of the data retention time is shown in FIG.
In the case of the NMOS transistor shown in FIG.
In the case of the PMOS transistor shown in FIG. 15B, the leakage current is generated at the PN junction of the memory cell transistor.

Since the temperature dependency of the data retention time is caused by the temperature dependency of the leak current at the PN junction, the temperature characteristics of the refresh timer need only be matched to the temperature characteristics of the memory cell leak. Therefore, in order to make the refresh interval have the same temperature characteristics as that of the memory cell leak, it is common practice to control the refresh interval of the refresh timer by using the leak speed of the memory cell.

Hereinafter, an example of a circuit diagram of a conventional refresh timer using a leak rate of a memory cell will be described with reference to FIG.

As shown in FIG. 16, since the capacity of one memory cell capacitor 203 is very small, about 1000 memory cells are required so as not to be affected by the input capacity of the potential comparison circuit 206 and noise. They are connected in parallel to form a memory cell block 201 as a dummy of the main body memory. That is, the storage nodes 204 and the cell plate nodes 205 are connected to each other, and all the capacitors 203 are connected in parallel. The change in the potential of the storage node 204 is input to the potential comparison circuit 206, where the potential change is compared with the reference potential VREF. Note that the memory cell block 2
01 is generally laid out for the refresh circuit separately from the memory body.

Hereinafter, the circuit operation of the refresh timer configured as described above will be described.

First, the storage node 20 shown in FIG.
4 is the power supply potential V through the memory cell transistor 202
While the CC is charged, the timer circuit 208 outputs an oscillation signal as a refresh signal from the oscillation circuit 209 to the output terminal OUT, and the memory body is refreshed in accordance with the oscillation signal. The number of oscillations of the oscillation signal is counted by the counter circuit 210. When the number of oscillations of all the cells of the memory body is refreshed, the counter circuit 210 outputs a signal to reset the latch circuit 207. Stop oscillation (stop refresh).

Next, when the latch circuit 207 is reset, the memory cell transistor 202 is turned off and the storage node 204 is disconnected from the power supply. Then, the charge held in the storage node 204 gradually decreases due to the PN junction leak of the memory cell transistor 202, and the potential of the storage node 204 drops.

Next, when the potential of the storage node 204 drops to the reference potential VREF, the potential comparing circuit 206
Sets the latch circuit 207, and the latch circuit 20
7 outputs a signal, the timer circuit 208 is reset, the oscillation circuit 209 starts oscillating again, and the counter circuit 210 resumes counting the number of oscillations (refresh start). When the latch circuit 207 outputs a signal, the transistor 202 turns on and the storage node 204 is charged again to the power supply potential VCC. In this way, the refresh execution period and the refresh stop period are alternately repeated.

As described above, the refresh stop period is defined by the time required for the potential of the storage node 204 to fall from the power supply potential VCC to the reference potential VREF. At this time, the potential drop speed of the storage node 204 is designed to be substantially equal to the potential drop speed of the memory cell body, and the temperature characteristics are also designed to be substantially equal. Therefore, according to the present circuit, an optimal refresh stop period, that is, an optimal refresh interval can be set regardless of a temperature change.

By the way, the time when the refresh is required is not necessarily equal to the data holding time among all the main body memory cells. Therefore, the entire memory cell needs to be defined by the memory cell having the shortest data holding time. There is. However, between the memory cell with the shortest data retention time and the average memory cell with the data retention time,
The retention times differ by about 30 times. FIG. 17 shows the case where the power supply potential VCC is 3.6 V and the ambient temperature is 75 ° C.
4 shows a measurement result of a data retention time of a RAM memory cell.
As can be seen from FIG. 17, memory cells having a short data retention time form a group, but occupy only about 0.1% of the entire memory cells. Furthermore, if a large number of memory cells are connected in parallel and the falling speed of the storage node potential is averaged as in the refresh timer described in FIG. Even when a refresh is required, the potential of the storage node 204 of the refresh timer has been averaged and will hardly drop. For example, when the power supply potential VCC is 5V, the potential of the storage node 204 drops only very slowly to about 4.95V. Therefore, the start timing of the refresh period must be very sensitive to a slight change in the reference potential VREF, and it can be seen that it is difficult to set an optimum refresh interval.

As a countermeasure, it is conceivable to quickly lower the potential of the storage node to the reference potential VREF. Conventionally, for example, Japanese Patent Application Laid-Open No. 4-259983
As described in the publication, the capacity of the memory cell capacitor is about 10 times smaller than the capacity of the capacitor of the memory body.
For example, the charge of the storage node may be quickly eliminated at a ratio of 1/100.
As described in Japanese Patent Application Laid-Open No. 777/77, a region having a high impurity concentration is provided in the substrate portion of the dummy memory cell so that the electrical resistance value at the PN junction of the transistor is reduced, and the leakage current is reduced by, for example, one digit. It has been proposed to increase by 1.5 digits.

[0016]

However, the semiconductor integrated circuit device having the conventional refresh timer circuit has some problems as described below. That is, when the capacity of the memory cell plate is reduced to one tenth, it is difficult to divert the memory cell of the memory body as it is, and it is necessary to manufacture the memory cell separately. In this case, it cannot be regarded as a dummy in a strict sense, and there is a difference in temperature-dependent characteristics. Therefore, there is a problem that it is difficult to set an appropriate refresh interval.

Further, when the electric resistance value is reduced, some extra steps are added to the manufacturing process of the memory cell, which is disadvantageous in cost. In addition, there is a drawback that the amount of leak current tends to vary.

The present invention solves the above-mentioned conventional problems at once,
By optimizing the refresh cycle, DRAM
It is an object of the present invention to reduce the refresh current at a low temperature or at a normal temperature.

[0019]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention provides a memory cell capacitor having a small capacitance, whereby a leak current characteristic based on the temperature dependency of a main memory can be easily obtained. , And the storage node potential decreases at a high speed.

Specifically, the first semiconductor integrated circuit according to the present invention
The path device is a first storage node that stores a charge.
And a capacitor in which a second electrode connected to the cell plate and a second electrode connected to the cell plate are opposed to each other, a first electrode is connected to the storage node, and a second electrode applies a charge to the first electrode of the capacitor. Connected to the first power supply
A main body side memory cell array in which memory cells each having an electrode formed by transistors connected to a control line for controlling the amount of electric charge stored in the capacitor, and data of the memory cell array on the main body side are held. A refresh timer which outputs a refresh signal of the memory cell array. The refresh timer detects a voltage drop due to a leak current of the memory cell array. Pulse generating means for outputting a signal to a control means for controlling the leak monitoring means while outputting a signal, wherein the leak monitoring means has the same configuration as the memory cells constituting the memory cell array on the main body side, And the third electrode of the transistor is in contact with the control means. A memory cell array in which the memory cells arranged in the dummy memory cell cause a voltage drop due to the leak current; and a storage node or a cell plate of the memory cells constituting the dummy memory cell array, and the dummy memory cell array is connected to the dummy memory cell array. A potential comparing means for comparing a potential generated by the cell array with a predetermined potential and outputting a signal when the potential matches the predetermined potential; and forming the dummy memory cell array.
The memory cell capacity value of the main body is
By making the capacitance value smaller than the memory cell
Or a memory constituting the dummy memory cell array
Generate leakage current from cell plate node of cell
It allows that have a leak accelerating means for accelerating the voltage drop of the memory cells constituting the dummy memory cell array.

According to the first semiconductor integrated circuit device , since the leak monitor has memory cells having the same configuration as the memory cells on the main body side, the leak current can be monitored reliably and the leak monitor means The voltage drop of the memory cell array is controlled by the
The capacitance value of the memory cell is used to configure the memory cell array on the main unit.
Smaller than the capacity value of the memory cell
Are the memory cells that make up the dummy memory cell array
Since there is a leak accelerating means for accelerating by generating a leak current from the plate node, the potential of the capacitor of the leak monitoring means can be rapidly lowered.

In the first semiconductor integrated circuit device, the pulse generation means is connected to the potential comparison means and the control means, and is connected to the signal latch means for holding a received signal; It is preferable to have an oscillating means for outputting a pulse serving as a refresh signal and a timer means comprising a counter for counting a predetermined number of the pulses .

In the first semiconductor integrated circuit device, it is preferable that the pulse generating means has a delay means connected to the potential comparing means and the control means for delaying a received signal .

In the first semiconductor integrated circuit device, it is preferable that the pulse generation means outputs all the refresh signals concentrated in a part of a refresh cycle which is a generation cycle of the detection signal .

In the first semiconductor integrated circuit device, the pulse generating means outputs the refresh signal consisting of one pulse synchronized with a generation cycle of the detection signal.
Is preferred.

A second semiconductor integrated circuit device according to the present invention
Is a configuration in which the configuration in which the potential comparison means is connected to each cell plate of the memory cells forming the dummy memory cell array is added to the configuration of the first semiconductor integrated circuit device .

A third semiconductor integrated circuit device according to the present invention
According to another aspect of the present invention, the leak accelerating means adds to the configuration of the first semiconductor integrated circuit device a configuration in which each cell plate of the memory cells forming the dummy memory cell array is electrically open.

Since the electrode on the cell plate side is electrically opened by the third semiconductor integrated circuit device, the electric charge on the opposing electrode also naturally disappears as the potential disappears from the storage node. Thus, the charge of the storage node can be eliminated without receiving a large resistance.
Accordingly, since the charge of the storage node can be eliminated without receiving a large resistance, the charge immediately leaks through the junction of the transistor after the supply of the charge to the storage node is stopped, and the potential of the storage node drops rapidly. I do.

In a third semiconductor integrated circuit device, the transistor of the memory cell is an N-type MOS transistor, and the leak accelerating means is configured to apply the dummy memory cell array to the first memory cell array. It is preferable that the power supply is connected to a boosted power supply having a higher potential than that of the power supply .

In the third semiconductor integrated circuit device, the transistor of the memory cell is an N-type MOS transistor, and the leak accelerating means is configured such that the substrate of the N-type MOS transistor on the dummy memory cell array side is connected to the main body side. Is preferably connected to a step-down power supply having a lower potential than a power supply connected to the substrate of the N-type MOS transistor on the memory cell array side .

In the third semiconductor integrated circuit device, at least one of the storage node or the cell plate on the dummy memory cell array side is connected via a fuse at one electrode and the other electrode is grounded. One spare capacitor is connected, the capacitance value to be coupled to the storage node is preferable that the fuse can be adjusted by being cut
No.

With this configuration, when electric charges are supplied to the storage node by the first power supply and the potentials of the storage node and the node on the cell plate side increase, the electric charge is supplied to the spare capacitor on the storage node side or the cell plate side. Since the charge is stored via the fuse, the amount of charge held in the storage node is increased by the amount of the spare capacitor, so when the fuse is blown, the amount of charge held by the spare capacitor is increased. The amount of charge held in the storage node is reduced. Therefore,
The capacitance value coupled to the storage node can be adjusted to decrease by blowing the fuse.

In the third semiconductor integrated circuit device, a first electrode is connected to at least one of the storage node or the cell plate on the dummy memory cell array side via a fuse, and a second electrode is connected to the first electrode. And at least one spare transistor whose third electrode is connected to the control means,
Lowering speed of the potential of the storage node, it is preferable the fuse can be adjusted by being cut
New

With this arrangement, when the potentials of the storage node and the node on the cell plate side fall, the electric charge also flows through the fuse to the spare transistor on the storage node side or the cell plate side, so that the spare transistor is Since the junction leakage of the transistor increases by the amount of the existing transistor, when the fuse is cut, the junction leakage as a whole is reduced by the junction leakage of the spare transistor. Therefore, the falling speed of the storage node potential can be adjusted so as to be reduced by cutting the fuse.

A fourth semiconductor integrated circuit device according to the present invention
In the configuration of the first semiconductor integrated circuit device , the leak acceleration unit may connect a first electrode to each cell plate of the memory cells forming the dummy memory cell array,
The second electrode is connected to a second power supply, and the third electrode is an auxiliary transistor connected to the control means.

When the auxiliary transistor is turned off by the fourth semiconductor integrated circuit device , the node on the cell plate side is in an electrically open state. The same operation as in the invention of Item 3 is performed. In addition, the potential drop at the node on the cell plate side due to the junction leak of the auxiliary transistor further accelerates the potential drop at the storage node. Conversely, when the auxiliary transistor is turned on when the potential of the storage node drops, the potential drop speed of the storage node is reduced because the potential drop of the storage node is suppressed.
Therefore, by the on / off operation of the auxiliary transistor, not only the potential drop speed of the storage node is further accelerated than in the case of the third aspect of the present invention, but also the acceleration / deceleration of the potential drop speed of the storage node is controlled. Therefore, the refresh timing can be further optimized.

Each time the potential of the storage node drops to a predetermined potential and is again initialized to the first power supply potential, the node on the cell plate side is driven by the second power supply to the first power supply potential.
And the potential in the same potential direction as the power supply of the power supply, the imbalance between the first electrode and the second electrode of the capacitor when the potential rises or falls is suppressed.

In the fourth semiconductor integrated circuit device, it is preferable that the second power supply is equal to the potential of the first power supply.
New

In a fourth semiconductor integrated circuit device, the transistor of the memory cell is an N-type MOS transistor, and the leak accelerating means is configured to apply the dummy memory cell array to the first memory cell array. It is preferable that the power supply is also connected to a boosted power supply having a higher potential than that of the power supply .

In the fourth semiconductor integrated circuit device, the transistor of the memory cell is an N-type MOS transistor, and the leak accelerating means is arranged such that the substrate of the N-type MOS transistor on the dummy memory cell array side is connected to the main body side. It is preferable that the power supply is also connected to a step-down power supply having a lower potential than the power supply connected to the substrate of the N-type MOS transistor on the memory cell array side .

In the fourth semiconductor integrated circuit device, at least one of the storage node or the cell plate on the side of the dummy memory cell array is connected via a fuse at one electrode and the other electrode is grounded. One spare capacitor is connected, the capacitance value to be coupled to the storage node is preferable that the fuse can be adjusted by being cut
No.

In the fourth semiconductor integrated circuit device, a first electrode is connected to at least one of the storage node or the cell plate on the side of the dummy memory cell array via a fuse, and a second electrode is connected to the first electrode. And at least one spare transistor whose third electrode is connected to the control means,
Lowering speed of the potential of the storage node, it is preferable the fuse can be adjusted by being cut
New

In the fourth semiconductor integrated circuit device, it is preferable that the control means controls the operation of the transistor and the operation of the auxiliary transistor of the dummy memory cell array separately .

With this arrangement , the control means turns on / off the auxiliary transistor separately from the transistor based on the control signal for turning on / off the transistor of the dummy memory cell array so that the potential drop speed of the storage node changes. In order to control the operation, the potential drop speed of the storage node can be accelerated or decelerated.

A first refresh timer according to the present invention
The cycle adjusting method includes a cycle of a refresh timer that outputs a refresh signal for holding data of the main body side memory cell array by a data holding time of a dummy memory cell array having a memory cell having the same configuration as that of the main body side memory cell array. For the adjustment method, a measurement step of measuring the output cycle of the refresh signal is compared with a target value predetermined based on a standard value of a device constituting the memory cell array on the main body side and a measurement value obtained by the measurement step. evaluation process and, Bei Eteiru an adjusting step of adjusting the output cycle of the refresh signal when it has not reached the result a target value of the evaluation which to evaluate.

According to the first refresh timer cycle adjusting method , after the output cycle of the refresh signal from the refresh timer is measured in the measuring step, the target value set in advance in the evaluation step based on the standard value of the device is measured. And the measured value obtained by the measuring step are compared and evaluated. If the target value is not reached, the refresh cycle adjusting means is adjusted in the adjusting step, so that data can be held even under the worst temperature condition. In addition, the refresh cycle at normal temperature or low temperature can be extended according to the holding characteristics of the memory cell.

First Refresh Timer Period Adjustment Method
In the refresh cycle adjusting means, supply and capacitor storage node in which one of the electrodes and the cell plate to the connected another electrode for accumulating electric charge is opposite, the charge on the storage node and the storage node And a transistor for controlling the amount of charge stored in the storage node, wherein at least one of the storage node or the cell plate of the dummy memory cell is connected to the power supply. The first electrode is connected via a fuse, the second electrode is connected to the power supply, and the third electrode is connected to control means for controlling the amount of charge stored in the capacitor. A transistor is connected, and the adjusting method in the adjusting step is the fuse. It is done by cutting
preferable.

Second refresh timer according to the present invention
The cycle adjusting method includes a cycle of a refresh timer that outputs a refresh signal for holding data of the main body side memory cell array by a data holding time of a dummy memory cell array having a memory cell having the same configuration as that of the main body side memory cell array. A preparatory step of measuring a data retention time of a device constituting the memory cell array on the main body side under a predetermined condition, and setting a target value from the measured value; A measurement step of measuring under the same conditions as the preparation step, an evaluation step of comparing and evaluating the target value of the preparation step and the measurement value of the measurement step, and when the evaluation result has not reached the target value. Bei Eteiru an adjusting step of adjusting the output cycle of the refresh signal.

According to the second refresh timer cycle adjusting method , in the preparatory step, the data retention time of the device constituting the memory cell array on the main body side is measured under predetermined conditions, and the target value is determined from the measured value. A value is set, and in a measurement step, an output cycle of a refresh signal from a refresh timer that outputs a refresh signal for holding data of the memory cell array on the main body side is measured under the same conditions as in the preparation step. Thereafter, in the evaluation step, the target value in the preparation step is compared with the measurement value in the measurement step, and as a result of the evaluation, if the target value is not reached, the output cycle of the refresh signal is adjusted in the adjustment step. Since the optimum refresh period can be set for each device without being limited to the device specification value, and the devices used in the preparation process are actually measured under predetermined conditions, the same as the preparation process in the measurement process The measurement under the worst temperature condition is unnecessary.

Second Refresh Timer Period Adjustment Method
In the refresh cycle adjusting means, supply and capacitor storage node in which one of the electrodes and the cell plate to the connected another electrode for accumulating electric charge is opposite, the charge on the storage node and the storage node And a transistor for controlling the amount of charge stored in the storage node, wherein at least one of the storage node or the cell plate of the dummy memory cell is connected to the power supply. The first electrode is connected via a fuse, the second electrode is connected to the power supply, and the third electrode is connected to control means for controlling the amount of charge stored in the capacitor. A transistor is connected, and the adjusting method in the adjusting step is the fuse. It is done by cutting
preferable.

[0051]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is an all-pair configuration diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention. In FIG. 1, a memory cell array in which memory cells each including one capacitor and one transistor are arranged receives a refresh signal periodically from a refresh timer via a refresh counter and a word driver. The refresh timer has a memory cell having the same configuration as the memory cell on the main body side, detects a drop in the potential of the storage node of the memory cell to a predetermined potential, and notifies a pulse generating circuit of the leak monitor circuit; A pulse generating circuit for generating a pulse serving as a trigger for the refresh signal. The word driver is connected to all the word lines of the memory cell array, and supplies charges for holding data by activating transistors connected to the word lines (WLn) sequentially selected by the refresh counter. .

FIG. 2A is a circuit diagram of a leak monitor circuit of a refresh timer in the semiconductor integrated circuit device according to the first embodiment of the present invention. As shown in FIG. 2A, the refresh timer includes a capacitor 11 having a first electrode 11a and a second electrode 11b,
A drain electrode 13a, which is a first electrode connected to a first electrode 11a of the capacitor 11 and forms a storage node 12 for storing charges, a first power supply 15A (potential) for supplying charges stored in the storage node 12 : VCC)
A source electrode 13b, which is a second electrode, and a gate electrode 13c, which is a third electrode connected to a control terminal RST for controlling a current between the drain electrode 13a and the source electrode 13b, are respectively provided on the substrate. NM being done
The potentials of the OS transistor 13 and the storage node 12 are monitored. When the potential of the storage node 12 charged to the power supply potential VCC through the transistor 13 drops to the reference potential VREF due to the leakage current of the transistor 13, the refresh timer is used. Connect signal to terminal R
And Q potential output circuit 16. As a feature of this embodiment, the second electrode 11b of the capacitor 11 forms a cell plate 14 and is electrically open.

Although not shown in the figure, a memory cell comprising capacitor 11 and transistor 13 has a capacity of 100
About 0 are connected in parallel to form a dummy memory cell array 17.

Hereinafter, the operation of the leak monitor circuit configured as described above will be described with reference to FIGS. 2 (a) and 2 (b). FIG. 2B is a schematic sectional view of the leak monitor circuit device. The description of the same components as shown in FIG. 2A will be omitted by retaining the same reference numerals. First, when the control terminal RST is turned on, the transistor 1
3, a predetermined voltage is applied to the gate electrode 13c, and the charge is supplied from the bit line 15B to the storage node 12, so that the potential of the storage node becomes the power supply potential V.
Become CC. Next, when the control terminal RST is turned off, the electric charge accumulated in the storage node 12 mainly flows out from the drain electrode of the transistor 13 as a leak current 18 to the substrate, so that the potential of the storage node 12 gradually decreases. Go down. The potential comparator 16 connected to the storage node 12 constantly monitors the potential of the storage node 12, and outputs a detection signal when the potential of the storage node 12 drops below the reference potential VREF.

The potential drop rate of the storage node 12 is as follows:
Since the cell plate 14 is electrically open, the parasitic capacitance 19 and the like coupled to the storage node 12 become relatively small, so that the speed is increased.

Hereinafter, a potential drop in the storage node 12 will be described.

First, it is assumed that the transistor 13 is turned on and the potential of the storage node 12 is at VCC.
Next, since the transistor 13 is turned off and the storage node 12 is brought into a floating state, electric charge stored in the storage node 12 is mainly lost as a junction leak current of the transistor 13, so that the potential of the storage node 12 is reduced. Descends. This storage node 1
2 is determined by the resistance value of the current leak path and the capacitance value coupled to the storage node 12. In order to change the resistance value of the current leak path, the size of the transistor 13 may be adjusted. To change the capacitance value, the size of the capacitor 11 may be adjusted when the potential of the second electrode 11b of the capacitor 11 is fixed. However, since the size of the transistor 13 and the capacitor 11 is limited due to the layout, the product of the resistance value of the current leakage path or the capacitance value coupled to the storage node 12, that is, the potential drop rate of the storage node 12 is reduced. In some cases, the desired value cannot be set.

Next, the relationship between the potential falling speed of the storage node and the refresh cycle will be described. The refresh cycle required to hold the data of all the memory cells of the memory body is defined by the memory cell having the worst data holding characteristic. As shown in FIG. There is a time difference of about 30 times between the time when cells cannot hold data and the time when 50% of memory cells cannot hold data. For example, 1
When the 000 memory cells are divided into blocks as shown in FIG. 2A, the potential drop speed of the storage node 12 is an average of 1000, so that the storage node of the memory cell having the shortest data retention time is used. This is about 1/30 of the potential drop rate of Twelve. That is, even if the storage node 12 of the memory cell with the shortest data retention time drops by 1 V, the potential of the storage node 12 connected to the dummy memory cell 17 drops by only 0.03 V. Therefore, if the reference potential VREF fluctuates even at 0.01 V, the timing at which the potential comparison circuit 16 outputs a signal greatly fluctuates.

FIG. 3 is a diagram comparing the potential drop speed of the leak monitor circuit of the present embodiment with the potential drop speed of the conventional leak monitor circuit. The time when the control terminal RST is turned off is set to t = 0, and the change between the elapsed time t and the storage node potential is shown. As shown in FIG. 3, a solid line 20 indicates a potential change of the storage node of the present embodiment, and a broken line 21 indicates a potential change of the conventional storage node. Since the potential of the broken line 21 hardly changes with respect to the predetermined time t, the setting margin of the reference potential VREF cannot be set. On the other hand, according to the present embodiment, since the potential drop rate is accelerated, the amount of change in the storage node potential near the predetermined time t is larger than in the past, so that the reference potential VREF can be set with a margin 22 and the refresh period can be reduced. The tolerance 23 of the error can be kept within a relatively narrow range.

As described above, in order to accelerate the potential drop speed of the storage node 12 shown in FIG. The node is configured to be floating. For this reason,
For example, a 16 Mbit D using a 0.5 μm process
In the case of a RAM, the stray capacitance coupled to the storage node 12 is about 1/20 of the capacitance value of the capacitor 11, and the potential drop speed of the storage node 12 is accelerated by about 20 times.

FIG. 4 shows a measurement example. Experimental 1
Power supply voltage VCC = 3.
FIG. 9 is a diagram showing the actual measurement of the potential drop rate of the leak monitor circuit of the present embodiment and the potential drop rate of the conventional leak monitor circuit under the conditions of 6 V, an ambient temperature of 75 ° C., and a substrate potential VBB = −1.3 V. The time when the control terminal RST is turned off is represented by t =
A value of 0 indicates a change between the elapsed time t and the storage node potential. A curve 24 shown in FIG. 4 is a potential change of the storage node of the present embodiment, and a curve 25 is a potential change of the conventional storage node. In the curve 25 showing the conventional potential change, the storage node potential after a lapse of one second exceeds 3.5 V, and it is impossible to set the reference potential VREF. On the other hand, the curve 24 indicating the potential change according to the present embodiment indicates that the storage node potential after one second has elapsed drops to 2.6 V, and the reference potential VREF.
Can be set. Note that it can also be confirmed that the curve 24 indicating the potential change according to the present embodiment approaches the potential drop speed of the storage node of the bad cell, which is a small number of memory cell groups, having poor retention characteristics.

As described above, according to the present embodiment, in the leak monitor circuit of the refresh timer, by electrically opening the node on the cell plate 14 side,
Since the potential of the storage node 12 can be rapidly dropped, the speed of the storage node potential of the main body memory cell having the shortest data retention time can be approached to the fall rate of the storage node potential, so that the refresh interval reflecting the data retention time can be set. Become so. Therefore, since the refresh cycle can be optimized, the refresh current at the time of low temperature or normal temperature in the semiconductor memory device can be reduced.

(First Modification of First Embodiment) Hereinafter, a first modification of the first embodiment of the present invention will be described with reference to the drawings.

FIG. 5A is a circuit diagram of a leak monitor circuit of a refresh timer in a semiconductor integrated circuit device according to this modification. The description of the same components as shown in FIG. 2A will be omitted by retaining the same reference numerals. Dummy memory cell array 1 according to first embodiment
In order to connect the storage nodes 12 of the seven memory cells to each other, the shape of the storage nodes 12 must be changed. Therefore, the same memory cell as the memory cell on the main body side cannot be used as it is. Also in the refresh timer according to the first embodiment shown in FIG. 2, it may be extremely difficult to draw out the storage node 12 and input it to the potential comparison circuit 16 in view of the layout.

According to this modification, the potential comparison circuit 16
The capacitor 11 is connected to the second electrode 11b side, that is, the cell plate 14, and monitors the potential of the second electrode 11b.

That is, even if the cell plate 14 is monitored by the potential comparing circuit 16,
Since the potential drops at the same speed as the storage node 12, the potential comparison circuit 16 outputs a signal at the same time as when the storage node 12 is monitored. Further, in the above-mentioned 16M bit DRAM, each cell plate node 14 is originally connected, and as shown in FIG. 5B, the wiring is drawn out from the cell plate 14 rather than drawn out from the storage node 12, and the potential comparison is performed. It can be seen that it is easier to input to the circuit 16.

As described above, according to the present modification, the potential comparison circuit 16 is connected to the cell plate 14 and monitors the potential of the electrode of the cell plate 14, so that the potential comparison circuit 16 is arranged on the storage node 12 side. Even if there is no room in the layout, the same memory cell as the main body memory can be used.

(Second Modification of First Embodiment) Hereinafter, a second modification of the first embodiment of the present invention will be described with reference to the drawings.

FIG. 6A is a circuit diagram of a leak monitor circuit of a refresh timer in a semiconductor integrated circuit device according to this modification. The description of the same components as shown in FIG. 2A will be omitted by retaining the same reference numerals. In FIG. 6A, the dummy memory cell array 1
The source electrode 13b of the transistor 13 of the memory cell constituting the memory cell 7 is connected to a boosted power supply 15C (potential: VD) having a higher potential than the power supply VCC connected to the second electrode of the transistor constituting the memory cell on the main body side. ing. Also,
To the substrate of the same transistor 13, a step-down power supply (potential: VSUB) having a lower potential than the power supply connected to the substrate of the transistor of the memory cell on the main body side is connected.

According to the present modification, the potential difference applied to the PN junction of the transistor 13 which is an NMOS transistor can be increased (VD-VSUB), and the junction leakage current increases by that much. Can be further accelerated.
FIG. 6B shows a measurement example. FIG. 9 is a diagram illustrating a potential drop speed of the leak monitor circuit of the present modified example and a potential drop speed of the leak monitor circuit of the first embodiment. The time when the control terminal RST is turned off is set to t = 0, and the change between the elapsed time t and the storage node potential is shown. The curve 26 according to the present modified example has a larger gradient of the potential change after the elapse of the time t than the curve 27 according to the first embodiment, and thus the setting margin of the reference potential VREF can be increased.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 7 is a circuit diagram of a leak monitor circuit of a refresh timer in a semiconductor integrated circuit device according to a second embodiment of the present invention. The description of the same components as those of the leak monitor circuit according to the first embodiment shown in FIG. 2A will be omitted by retaining the same reference numerals. In FIG. 7, when the potential of the storage node 12 changes,
First electrode 11a and second electrode 11 of capacitor 11
With respect to the coupling b, when the electric potential is not equilibrium between the time when the potential rises and the time when the potential drops, the storage node 12 repeats charging and discharging, so that the potential of the cell plate 14 keeps rising or falling. Will be. Further, if the potential of the second electrode 11b on the cell plate 14 side continues to rise or fall, there is a possibility that an adverse effect such as destruction of the capacitance insulating film of the capacitor 11 may occur.

In the leak monitor circuit according to the present embodiment, the second electrode 11b of the capacitor 11 is connected to the drain electrode 30a as the first electrode to the cell plate 14, and the source electrode 30b as the second electrode is connected to the second electrode 11b. And a gate electrode 30c as a third electrode is connected to the second power supply 31A (potential: VCC) via the auxiliary transistor 30 connected to the control terminal RST. That is, while the transistor 13 is turned on and the storage node 12 is connected to the potential VCC of the first power supply 15A, the cell plate 14 is charged to the potential VCC of the second power supply 31A, and the transistor 13 is turned off to turn off the storage node. Before the potential of the storage node 12 starts to fall, the auxiliary transistor 30 is turned off to turn off the storage node 12.
Was made to float.

Further, a control circuit for controlling the on / off operation of the auxiliary transistor 30 based on a control signal for turning on / off the transistor 13 so as to change the potential drop speed of the storage node 12 is provided separately. This control circuit is configured so that the timing of the on / off operation of the auxiliary transistor 30 can be changed.

Therefore, according to the present embodiment, the potential falling speed of the storage node 12 is accelerated as compared with the case where the potential of the cell plate 14 is fixed, as in the first embodiment. At this time, the cell plate 14 is charged to the potential VCC of the second power supply 31A every cycle, so that the potential of the cell plate 14 does not continuously rise or fall. Also, the junction plate of the auxiliary transistor 30 causes the cell plate 14
Is further accelerated, the potential drop speed of the storage node 12 is further accelerated as compared with the case where the cell plate 14 is simply electrically opened as in the first embodiment. Will be done.

In addition, the ON / OFF operation of the auxiliary transistor 30 not only increases the potential drop speed of the storage node 12, but also controls the acceleration / deceleration of the potential drop speed of the storage node 12 by the control circuit. Optimization can be achieved. That is, when the potential of the storage node 12 drops, the auxiliary transistor 3
By turning off 0, the potential drop speed of the storage node 12 can be further accelerated. Conversely, when the auxiliary transistor 30 is turned on, the potential drop speed of the storage node 124 can be reduced.

In the leak monitor circuit according to the second embodiment, the auxiliary transistor 30 is turned off and the cell plate 14 is floated before the transistor 13 is turned off.
Until the potential of the storage node 12 decreases to a predetermined potential, the potential of the cell plate 14 is fixed at the potential VCC of the second power supply 31A and the potential of the storage node 12 is not increased without accelerating the potential drop rate of the storage node 12. If the potential drop rate of the storage node 124 is accelerated by dropping the auxiliary transistor 30 to a predetermined potential higher than the potential VREF and then turning off the auxiliary transistor 30 to float the cell plate 14, a more detailed time can be obtained. Can be set.

In the leak monitor circuit according to the second embodiment, the cell plate 14 is connected to the potential VCC of the second power supply 31A via the auxiliary transistor 30, but the auxiliary transistor 30 is connected to the NMOS transistor. In the case of the configuration, the power supply voltage to be connected may be set in consideration of the amount of potential drop of the storage node 12 as long as the junction of the NMOS transistor does not become forward biased. One guide at this time is to set the potential of the second power supply 31A to the sum of the potential VCC of the first power supply 15A and the substrate node potential VBB (negative potential) of the auxiliary transistor 30 (negative potential).
CC + VBB) or more. When the auxiliary transistor 30 is formed of a PMOS transistor, there is no need to consider the power supply voltage to be connected as long as the auxiliary transistor 30 is not adversely affected.

(First Modification of Second Embodiment) Hereinafter, a first modification of the second embodiment of the present invention will be described with reference to the drawings.

FIG. 8 is a circuit diagram of a leak monitor circuit of a refresh timer in a semiconductor integrated circuit device according to this modification. The same components as those shown in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 8, in the leak monitor circuit of this modification, one electrode of one or more spare capacitors C11 to C1n is connected to storage node 12 by a fuse F2.
1 to F2n, and the other electrode is grounded. One or more spare capacitors C21 to C2n are connected to the cell plate 14 by a fuse F3.
1 to F3n are connected in parallel. The capacitance value coupled to the storage node 12 is determined by the fuse F2
1 to F2n or F31 to F3n.

The drain electrodes of one or more spare transistors T11 to T1n are connected in parallel to the storage node 12 via fuses F11 to F1n, and the source electrodes are connected to the first power supply 15A. Each gate electrode is connected to the control terminal RST, and the drain electrode of one or more spare transistors T21 to T2n is connected to the fuse F in the cell plate 14.
The source electrodes are connected to the second power supply 31A, respectively, and the gate electrodes are respectively connected to the control terminals RST. The amount of leakage current flowing out of the storage node 12 is configured to be adjustable so as to be reduced by cutting the fuses F11 to F1n or F41 to F4n.

As described above, the potential drop speed of the storage node 12 is defined by the stray capacitance coupled to the storage node 12, the leak current of the transistor 13, and the auxiliary transistor 30 when the auxiliary transistor 30 is provided. Is done.

Therefore, the potential drop speed of the storage node 12 can be accelerated by reducing the stray capacitance coupled to the storage node 12 or increasing the leakage current of the transistor 13 or the auxiliary transistor 30. Conversely, the potential drop rate of the storage node 12 can be reduced by increasing the stray capacitance coupled to the storage node 12 or reducing the leakage current of the transistor 13 or the auxiliary transistor 13.

Accordingly, one or more spare capacitors C11 to C1n and C21 to C2n are adjusted to reduce the stray capacitance coupled to the storage node 12.
To the storage node 12 and the cell plate 1 respectively.
4 through fuses F21 to F2n and F31 to F3n, respectively, and the fuse F21
To F2n or some of F31 to F3n, the capacitance value coupled to the storage node 124 can be reduced. Of course, the spare capacitors C11 to C1n and C21 to C2n may be arranged on only one of the storage node 12 and the cell plate 14.

In order to reduce the leakage current of the transistor 13 and the auxiliary transistor 30,
One or more spare transistors T11-T1n and T2
1 to T2n are stored in the storage node 12 and the cell plate 14, respectively, with the fuses F11 to F1n and F41 to F2.
4n, the fuse F1
By appropriately cutting some of 1 to F1n or F41 to F4n, the current leaking from the storage node 12 can be reduced. Of course, the spare transistors T11 to T1n and T21 to T2n may be arranged on only one of the storage node 12 and the cell plate 14.

For example, to accelerate the potential drop speed of the storage node 12, the spare capacitors C11 to C1n
And fuses F21-F connecting C21-C2n
2n or some of F31 to F3n are cut appropriately. At this time, the fuses F11 to F1n connecting the spare transistors T11 to T1n and T21 to T2n
And F41 to F4n may be left as they are without cutting.

As described above, according to this modification, the potential drop speed of storage node 124 is reduced
Fuse F21-F of 11-C1n and C21-C2n
It can be adjusted to accelerate by cutting 2n or F31 to F3n. Conversely, the spare transistor T1
1 to T1n and fuses F11 to F1 of T21 to T2n
n or some cutting of F41 to F4n can be adjusted to reduce the speed.

Third Embodiment Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 9A is a circuit diagram of a refresh timer in a semiconductor integrated circuit device according to the third embodiment of the present invention. The refresh timer shown in FIG. 9A includes a leak monitor circuit having an auxiliary transistor according to the second embodiment, a pulse generation circuit described in the present embodiment, and a driver circuit which is a control unit of the leak monitor circuit. ing. Therefore, the same components as those of the leak monitor circuit shown in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted.

The pulse generation circuit receives a signal output when the latch circuit 40 is set, outputs an oscillation signal as a refresh signal in response to a signal output when the latch circuit 40 is set, and outputs a predetermined signal. A timer circuit that outputs a signal for resetting the latch circuit 40 when the oscillation signal of the number of oscillations of the clock signal has been output, and stops the output of the oscillation signal in response to the output signal of the latch circuit 40 reset by the signal. 41.

The timer circuit 41 outputs an oscillation signal in response to the output of the latch circuit 40 set by the output of the leak monitor circuit. The oscillation circuit 42 counts the number of oscillations and counts the number of oscillations and reaches a predetermined number of oscillations. , Latch circuit 40
And a counter circuit 43 that outputs a reset signal.

Hereinafter, the basic circuit operation of the refresh timer configured as described above will be described with reference to the timing chart shown in FIG. First, at time t1, the storage node 12 of the leak monitor circuit connects to the first power supply 15A through the transistor 13.
Is charged to the potential VCC. While the storage node 12 is being charged, the timer circuit 41 outputs a pulse signal serving as a refresh signal from the oscillation circuit 42 to the output terminal OUT, and the counter circuit 43 counts the number of oscillations of the pulse signal. At the same time, the memory cell array on the main body side is refreshed in synchronization with the pulse signal output from the timer circuit 41. Next, at time t2, when the oscillation is completed by the number of times of refreshing all the memory cells of the memory cell array on the main body side, the counter circuit 43 outputs a signal to reset the latch circuit 40, and
The oscillation of the oscillation circuit 42 is stopped (refresh is stopped).

Next, when the latch circuit 40 is reset, the driver circuit 44 which has received the reset signal turns off the transistor 13 of the leak monitor circuit to disconnect the storage node 12 from the first power supply 15A, Turn off the transistor 30 and turn off the cell plate 1
4 is disconnected from the second power supply 31A. As described in the second embodiment, it is desirable that the transistor 13 and the auxiliary transistor 30 can be individually controlled.

Next, the electric charge held in the storage node 12 gradually decreases due to the junction leak of the transistor 13, and the potential of the storage node 12 starts to drop. Incidentally, as described with reference to FIG. 3, the potential drop amount of the storage node 12 is larger than the broken line 46 by the conventional leak monitor circuit as shown by the curve 45, and the setting margin of the reference potential VREF is smaller. growing. When the potential of the storage node 12 drops to the reference potential VREF at time t3, the latch circuit 40 is set by the output signal from the potential comparison circuit 16 and a signal is output from the latch circuit 40. The timer circuit 41 is reset by the output signal of the latch circuit 40, and the oscillation circuit 42 starts oscillating again.
Restarts counting the number of oscillations (refresh starts).

Further, the transistor 13 and the auxiliary transistor 30 of the leak monitor circuit are turned on by the reset output signal of the latch circuit 40, and the storage node 12 is again charged to the potential VCC of the first power supply 15A. become. In this way, the refresh execution period,
The refresh stop period is alternately repeated.

As described above, according to the refresh timer of this embodiment, the leak monitor circuit accelerates the potential drop speed of the storage node 12 to approach the potential drop speed of the storage node of the main memory cell having the shortest data retention time. This makes it possible to set a refresh interval reflecting the data holding time. Of course, if the leak monitor circuit or the pulse generation circuit of another embodiment or the modification is used as the leak monitor circuit, it is possible to set the refresh interval more optimally.

(Fourth Embodiment) Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 10A is a circuit diagram of a refresh timer in a semiconductor integrated circuit device according to a fourth embodiment of the present invention. The refresh timer shown in FIG. 10A includes the leak monitor circuit having the auxiliary transistor according to the second embodiment, the pulse generation circuit described in the present embodiment, and a driver circuit which is a control unit of the leak monitor circuit. ing. Therefore, the same components as those of the leak monitor circuit shown in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted.

The pulse generating circuit includes a delay circuit 50 that receives a detection signal output from the potential comparator 16 in the leak monitor circuit after detecting and outputting the reference potential VREF, and delays and inverts the detection signal. The oscillator circuit 42 outputs a pulse signal serving as a refresh signal based on the signal output from the delay circuit 50, and a counter circuit 43 counts the pulse signal a predetermined number of times.

The operation of the refresh timer configured as described above will be described below with reference to the timing chart shown in FIG. First, at time t1, when the potential of the storage node 12 in the leak monitor circuit drops below the reference potential VREF, the potential comparator 16 outputs a detection signal. The detection signal is supplied to the delay circuit 50 of the pulse generation circuit.
Is input to The output signal delayed by the delay circuit 50 is input to the oscillation circuit 42 at time t2, and the oscillation circuit 42 outputs a pulse signal to the output terminal OUT, and the transistor 13 and the auxiliary transistor of the leak monitor circuit via the driver circuit 44. Input to 30 gate electrodes. Thereby, the storage node 12 is recharged to the potential VCC until time t3, and the output of the detection signal of the leak monitor circuit stops. That is, the delay circuit 50 latches the output of the leak monitor circuit and generates the pulse width of the delay time t4, thereby defining the charging time of the storage node 12. The operation cycle t of the leak monitor circuit is twice as long as the output time of the output signal (t4
× 2) and the potential drop time t5 when the potential of the storage node 12 drops from VCC to the reference potential VREF.

The output of the delay circuit 50 becomes a trigger,
The oscillation circuit 42 oscillates and outputs a signal as a refresh timer. In synchronization with this signal, the word lines of the memory cell array on the main body side are sequentially selected and refresh is performed. Note that the output of the leak monitor circuit may be directly connected to the oscillation circuit 42.

A counter circuit 43 is connected to the oscillating circuit 42. When the oscillating circuit 42 oscillates a predetermined number of times corresponding to the number of word lines, the counter circuit 43
As a result, the oscillation circuit 42 is stopped, and the refresh operation ends. In this case, the refresh operation is a concentrated refresh mode that is performed intensively during a part of the operation period t of the leak monitor circuit.

The delay time t generated by the delay circuit 50
4 only needs to be sufficient to trigger the oscillation circuit 42, and precision is not required.

The delay time t generated by the delay circuit 50
4 is longer than the time required to refresh all the word lines, if the output of the leak monitor circuit or the output of the delay circuit 50 is used as the enable signal of the oscillation circuit 42, the counter circuit 43 becomes unnecessary. . By the way,
The oscillation circuit 42 continues to oscillate while the enable signal is being input.

As described above, according to the refresh timer of this embodiment, the leak monitor circuit accelerates the potential drop speed of the storage node 12 to approach the potential drop speed of the storage node of the main memory cell having the shortest data retention time. This makes it possible to set a refresh interval reflecting the data holding time. Of course, if the leak monitor circuit or the pulse generation circuit of another embodiment or the modification is used as the leak monitor circuit, it is possible to set the refresh interval more optimally.

(First Modification of Fourth Embodiment) Hereinafter, a first modification of the fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 11A is a circuit diagram of a refresh timer in a semiconductor integrated circuit device according to this modification. The refresh timer shown in FIG. 11A includes a leak monitor circuit having the auxiliary transistor according to the second embodiment, a pulse generation circuit described in the present embodiment, and a driver circuit which is a control unit of the leak monitor circuit. ing. Therefore, the same components as those of the leak monitor circuit shown in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted.

The pulse generating circuit includes a delay circuit 51 for receiving a detection signal output from the potential comparator 16 in the leak monitor circuit after detecting and outputting the reference potential VREF, and delaying and inverting the detection signal. Inverting circuit 52 that inverts the signal output from delay circuit 51 and outputs a refresh signal
It is composed of

Hereinafter, the operation of the refresh timer according to the present modification will be described in comparison with the operation of the refresh timer according to the fourth embodiment with reference to FIG.

The leak monitor circuit shown in FIG.
When the potential effect speed of the storage node 12 is high and the operation cycle t of the leak monitor circuit can be set shorter than the upper limit of the refresh cycle, the distributed refresh mode for selecting a word line in synchronization with the output of the leak monitor circuit is used. Applicable. That is, the output cycle t of the leak monitor circuit
With the output of the refresh timer in synchronization with the output period tREF of the refresh timer, the word lines can be sequentially selected and refreshed.

The centralized refresh mode according to the fourth embodiment and the distributed refresh mode according to the present modification are different from each other in one mode.
The case where the refresh intervals in the word lines are set to be equal will be compared. The refresh cycle from when a certain word line is selected to when the next word line is selected is shorter in the concentrated refresh mode because a refresh stop period exists in the concentrated refresh mode. For this reason, a heat generation phenomenon occurs due to the circuit operation, and the heat generation amount increases as the refresh cycle becomes shorter. 1
Since the refresh intervals of the word lines are equal, the average amount of heat generated is equal. However, since the heat is concentrated in the concentrated refresh mode, the temperature rise of the device is larger in the concentrated refresh mode.

Since the data retention characteristic becomes better as the temperature becomes lower, the refresh interval can be set longer in the distributed refresh mode, so that the power consumption can be further reduced.

Further, according to the present modification, an oscillation circuit and a counter circuit are not required as compared with the pulse generation circuits according to the other embodiments, so that the circuit scale of the pulse generation circuit can be reduced.

(Fifth Embodiment) Hereinafter, a fifth embodiment of the present invention will be described.

When a mode for controlling the refresh operation from outside the device is used, a standard value is defined for the refresh cycle, and the data holding characteristics of the device must satisfy the standard. Therefore, even in the self-refresh mode, if the refresh cycle is within the standard value, the device can continue to hold correct data. For example, in a 4k refresh compatible version of 16MDRAM, the refresh cycle is specified to be 64 ms, so that the refresh timer of the present invention may realize a refresh cycle of 64 ms or less under the worst temperature condition. As described with reference to FIG. 16, since the leak characteristics of the memory cells are not uniform, the leak characteristics of the dummy memory cells used in the present invention are not uniform, and the refresh timer cycle differs for each device. If the refresh cycle adjusting circuit shown in FIG. 8 is used, the refresh cycle can be extended or shortened. First, the cycle of a refresh signal generated by a refresh timer is measured for each device under the worst temperature condition, and the measurement result is compared with a target range set for a standard value. If the measurement result does not fall within the target range, the refresh cycle is adjusted by the refresh cycle adjusting circuit, then re-measured and compared again.

Hereinafter, a specific example of the refresh timer cycle adjusting method will be described with reference to the drawings.

FIG. 12 is a flowchart of a refresh timer cycle adjusting method according to the fifth embodiment of the present invention.

First, in step ST1, the target value of the refresh cycle is set to 50 ms or less with respect to the standard value of 64 ms.
Set to 60 ms. Of course, the target value only needs to be a value that satisfies the standard value, and the setting range does not have a strict meaning. Become.

Next, in step ST2, the cycle of the refresh signal output by the refresh timer for each device is measured under the worst temperature condition.

Next, in step ST3, if the first measurement result of a certain device is 100 ms, the target value is compared with the first measurement value, and the device is disqualified.

Next, in step ST4, the refresh cycle is adjusted to be shortened by trimming the fuse of the spare capacitor in the dummy memory cell of the leak monitor circuit of the refresh timer of the device determined to be disqualified. .

Next, the process ST2 is repeated, and the finely adjusted device is re-measured to obtain a second measurement result of 56 m
Since s was obtained, the target value was compared with the second measurement result in the next comparison step ST3, and the result was determined to be acceptable.

Of course, if the result of the remeasurement is out of the target range, the fuse may be trimmed again and the remeasurement may be repeated.

According to the present embodiment, it is possible to realize a refresh timer capable of retaining data even under the worst temperature condition and extending the refresh cycle at normal temperature or low temperature in accordance with the retention characteristics of the memory cell. .

Note that the target value of the refresh cycle may be set in accordance with the inspection standard. That is, since the standard value of the retention characteristic inspection is generally set high within a range that does not reduce the yield so as to be margin-free with respect to the external refresh standard value, the refresh timer cycle is determined according to the inspection standard value. By doing so, the current consumption due to refresh can be further reduced.

(First Modification of Fifth Embodiment) Hereinafter, a first modification of the fifth embodiment of the present invention will be described.

Although the refresh cycle under the control from the outside of the apparatus is standardized to a specific value, in an actual device, the holding characteristics are remarkably good, and the data is held even if the refresh cycle is ten times or more the standard value. May be possible.

Therefore, in this modification, the retention characteristic of each device is measured, and the target value of the refresh timer cycle is set based on the measured value.

Hereinafter, a specific example of the refresh timer cycle adjusting method will be described with reference to the drawings.

FIG. 13 is a flowchart of a refresh timer cycle adjusting method according to this modification.

First, in step ST11, it is assumed that the data retention time of a certain device is 500 ms.

Next, in step ST12, the measured value 50
As a target value with a margin based on 0 ms, 350
ms to 400 ms are set.

Next, in step ST13, the refresh timer cycle using the same device as the actually measured device is measured.

Next, in step ST14, if the first measurement result of a certain device is 250 ms, the target value is compared with the first measurement value to be disqualified.

Next, in step ST15, the refresh cycle is adjusted to be longer by trimming the fuse of the spare transistor in the dummy memory cell of the leak monitor circuit in the refresh timer of the device determined to be disqualified. .

Next, the process ST13 is repeated, and the finely adjusted device is re-measured to obtain the second measurement result 37.
Since 0 ms has been obtained, the target value is compared with the second measurement result in the next comparison step ST14, and the second measurement result falls within the target range, so that the result is judged as pass.

According to this method, an optimum refresh interval can be set for each device. Step ST11
Condition and process ST1 at the time of data retention time measurement in step ST1
Since it is only necessary that the temperature condition at the time of measuring the refresh timer cycle in 3 is the same, there is no need to measure or adjust the refresh timer cycle under the worst temperature condition, and the temperature management becomes easy.

[0140]

As described above, the first embodiment according to the present invention is described .
According to the semiconductor integrated circuit device of the first aspect, the leak monitor means can surely monitor the leak current, and the voltage drop of the memory cell of the leak monitor means is reduced by the dummy memory cell array.
The capacitance value of the memory cells that make up the
Smaller than the capacitance value of the memory cells that make up the
Or a memo that constitutes a dummy memory cell array.
Leakage current is generated from the cell plate node of the recell.
Since the potential of the capacitor of the leak monitor means can be rapidly decreased because of the leak accelerating means for accelerating the refresh cycle, the refresh cycle can be optimized, and the low-temperature Alternatively, the refresh current at room temperature can be reduced.

In the first semiconductor integrated circuit device, the pulse generating means includes: a latch means for latching a detection signal detected by the leak monitor means; an oscillating means for oscillating a pulse signal serving as a refresh signal; When the counter is configured to perform the minute counting, the refresh signal can be reliably generated from the detection signal.

In the first semiconductor integrated circuit device, the pulse generating means is constituted by a delay circuit which delays the output signal of the leak monitor means and outputs the delayed signal as a refresh signal.
Then, since the oscillating means, the counter and the like can be eliminated, the configuration of the device can be simplified. Further, it is possible to easily cope with a distributed refresh mode performed by generating a pulse synchronized with a detection signal output from the leak monitor means.

In the first semiconductor integrated circuit device,
Scan generation means, concentrated in part of the period of the refresh cycle is the occurrence period of the detection signal to generate a pulse as a refresh signal to all the memory cells of the body
Then , the refresh operation can be reliably performed.

In the first semiconductor integrated circuit device,
Scan generation means, and outputs a refresh signal comprising a single pulse synchronized with the generation period of the detection signal, the line Ell refresh operation by selecting one word line connected to the main body of the memory cell array in the order Therefore, compared with the centralized refresh mode in which the refresh signal is transmitted intensively during a part of the refresh cycle, the interval at which the refresh signal is transmitted is increased. Operation becomes stable.

According to the second semiconductor integrated circuit device of the present invention, the same effects as those of the first semiconductor integrated circuit device can be obtained.
In addition, since the potential comparison means is connected to the cell plate side in the dummy memory cell, even if there is no room in the layout for disposing the potential comparison means on the storage node side, the potential comparison means is the same as the memory cell on the main body side. Of memory cells can be used.

According to the third semiconductor integrated circuit device of the present invention, the same effects as those of the first semiconductor integrated circuit device can be obtained.
In addition, since the charge of the storage node in the dummy memory cell can be eliminated without receiving a large resistance, the potential of the storage node drops rapidly after the supply of the charge to the storage node is stopped. Of the storage node in the shortest memory cell. Therefore, the potential of the storage node in the memory cell having the shortest data retention time approaches the potential drop speed, so that the refresh cycle can be optimized, and the refresh current at the time of low temperature or normal temperature in the main body memory such as the DRAM can be reduced. Can be achieved.

According to the fourth semiconductor integrated circuit device of the present invention, the same effects as those of the third semiconductor integrated circuit device can be obtained.
In addition, the potential drop of the storage node can be further accelerated by the junction leak of the auxiliary transistor, and the potential drop speed can be reduced by turning off the auxiliary transistor. And the refresh cycle can be easily optimized.

In addition, since imbalance between the electrodes of the capacitor when the potential rises or drops is suppressed, problems such as destruction of the capacitor insulating film of the capacitor due to the imbalance can be avoided. .

In the fourth semiconductor integrated circuit, the potential of the second power supply connected to the second electrode of the auxiliary transistor is set to be the same as the potential of the first power supply that supplies the charge of the storage node. This makes it difficult for the potential of the capacitor to be unbalanced, so that the potential drop speed of the storage node can be reliably controlled.

[0150] In the fourth semiconductor integrated circuit, the control means controls the separate operation of the on-off of the auxiliary transistor is the transistor so that the potential drop speed of the storage node is changed Then, acceleration and deceleration of the potential drop speed of the storage node Since it can be performed, the refresh timing can be further optimized.

In the third or fourth semiconductor integrated circuit,
The second electrode of the NMOS transistor in the dummy cell
If a boosted power supply having a higher potential than the first power supply connected to the second electrode of the transistor in the memory cell on the main body side is connected , the potential difference at the PN junction of the NMOS transistor becomes large, so that the junction leakage is reduced. As a result, the potential effect speed of the storage node can be further increased. Therefore, the setting margin of the reference potential VREF can be increased, and the operation of the device is stabilized.

In the third or fourth semiconductor integrated circuit,
The substrate of the NMOS transistor in the dummy cell, if a low step-down power-supply electric potential than the power source connected to the substrate of the transistor in the memory cell of the main body side is connected, NMO
Since the potential difference at the PN junction of the S transistor increases, junction leakage increases, and the potential effect speed of the storage node can be further increased.
Therefore, the setting margin of the reference potential VREF can be increased, and the operation of the device is stabilized.

In the third or fourth semiconductor integrated circuit,
If at least one spare capacitor is connected to at least one of the storage node in the dummy memory cell and the node of the cell plate via a fuse , the fuse is cut off to thereby reduce the capacity of the spare capacitor by the capacity of the spare capacitor. Since the value can be reduced, fine adjustment can be performed in a direction in which the capacitance value of the capacitor is reduced and the potential drop speed of the storage node is accelerated. Therefore, for example, when manufacturing a refresh timer,
Adjustment in the direction of decreasing the capacitance value of the capacitor to increase the potential drop speed can be performed for each lot.

In the third or fourth semiconductor integrated circuit,
When at least one spare transistor is connected to at least one of the storage node or the cell plate node in the dummy memory cell via a fuse ,
By cutting the fuse, the amount of the leakage current of the spare transistor can be reduced, so that the amount of the leakage current of the storage node is reduced and the potential of the storage node is reduced in the direction of decreasing the potential. Can be performed. Therefore, for example, when manufacturing a refresh timer, adjustment in the direction of decreasing the potential drop speed can be performed for each lot.

A first refresh timer according to the present invention
According to the cycle adjusting method , data can be held even under the worst temperature condition, and the refresh cycle at room temperature or at low temperature can be extended according to the holding characteristics of the memory cell. The current can be reduced.

A second refresh timer according to the present invention
According to the cycle adjusting method , the first refresh timer
In addition to obtaining the same effect as the period adjustment method , the actual refresh value is obtained and evaluated for each device, so the optimal refresh cycle can be set for each device without being limited to the device specification value. Alternatively, current consumption due to refreshing at a low temperature can be further reduced.

Further, since the measurement under the worst temperature condition is not required in the measurement process, the temperature can be easily controlled.

First or second refresh timer period
In the adjusting method, a first electrode is connected to at least one of a storage node or a cell plate of a dummy memory cell via a fuse, a second electrode is connected to a power supply, and a third electrode is a charge storage amount of a capacitor. targeting refresh cycle adjusting means having at least one spare transistor connected to the control means for controlling the, the fuse connected to transistor of the pre <br/> Bei
Since the leakage current flowing out of the spare transistor is reduced, fine adjustment can be performed in a direction in which the potential drop speed of the storage node is reduced. Therefore, for example, when manufacturing a refresh timer, adjustment in the direction of decreasing the potential drop speed can be performed for each lot.

[Brief description of the drawings]

FIG. 1 is an all-pair configuration diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2A is a circuit diagram of a leak monitor circuit of a refresh timer in the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 2B is a schematic sectional view of a leak monitor circuit device of a refresh timer in the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 3 is a comparison diagram of a potential drop speed of a leak monitor circuit and a potential drop speed of a conventional leak monitor circuit in the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 4 is an actual measurement diagram of a potential drop speed of a leak monitor circuit and a potential drop speed of a conventional leak monitor circuit in the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 5A is a circuit diagram of a leak monitor circuit of a refresh timer in a semiconductor integrated circuit device according to a first modification of the first embodiment of the present invention. (B) is a schematic cross-sectional view of a leak monitor circuit device of a refresh timer in a semiconductor integrated circuit device according to a first modification of the first embodiment of the present invention.

FIG. 6A is a circuit diagram of a leak monitor circuit of a refresh timer in a semiconductor integrated circuit device according to a second modification of the first embodiment of the present invention. (B) shows the potential drop rate of the leak monitor circuit in the semiconductor integrated circuit device according to the second modification of the first embodiment of the present invention and the leak monitor circuit in the semiconductor integrated circuit device according to the first embodiment of the present invention. It is a comparison figure with a potential fall speed.

FIG. 7 is a circuit diagram of a leak monitor circuit of a refresh timer in a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram of a leak monitor circuit of a refresh timer in a semiconductor integrated circuit device according to a first modification of the second embodiment of the present invention.

FIG. 9A is a circuit diagram of a refresh timer in a semiconductor integrated circuit device according to a third embodiment of the present invention. (B) is a timing chart of a refresh timer in the semiconductor integrated circuit device according to the third embodiment of the present invention.

FIG. 10A is a circuit diagram of a refresh timer in a semiconductor integrated circuit device according to a fourth embodiment of the present invention. (B) is a timing chart of a refresh timer in a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 11A is a circuit diagram of a refresh timer in a semiconductor integrated circuit device according to a first modification of the fourth embodiment of the present invention. (B) is a timing chart of a refresh timer in a semiconductor integrated circuit device according to a first modification of the fourth embodiment of the present invention.

FIG. 12 is a flowchart of a refresh timer cycle adjusting method according to a fifth embodiment of the present invention.

FIG. 13 is a flowchart of a refresh timer cycle adjusting method according to a first modification of the fifth embodiment of the present invention.

FIG. 14 is a diagram showing the temperature dependence of the data retention time of a DRAM memory cell.

FIG. 15A is a schematic cross-sectional view of an NMOS transistor showing a leakage current at a PN junction. (B) is a schematic sectional view of a PMOS transistor showing a leakage current at a PN junction.

FIG. 16 is a circuit diagram of a refresh timer in a conventional semiconductor integrated circuit device.

FIG. 17 is a diagram showing data retention characteristics of a DRAM memory cell.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Capacitor 11a 1st electrode 11b 2nd electrode 12 Storage node 13 Transistor 13a Drain electrode 13b Source electrode 13c Gate electrode 14 Cell plate 15A 1st power supply 15B Bit line 15C Boost power supply 16 Potential comparison circuit 17 Dummy memory cell 18 Leakage Current 19 Parasitic capacitance 20 Storage node potential change of first embodiment 21 Conventional storage node potential change 22 Margin 23 Allowable range 24 Storage node potential change of first embodiment 25 Conventional storage node potential change 26 First modification Change of storage node potential 27 Storage node potential change of first embodiment 30 Auxiliary transistor 30a Drain electrode 30b Source electrode 30c Gate electrode 31A Second power supply RST Control terminal OUT Force terminal VREF Reference potential T11-T1n Spare transistor T21-T2n Spare transistor C11-C1n Spare capacitor C21-C2n Spare capacitor F11-F1n Fuse F21-F2n Fuse F31-F3n Fuse F41-F4n Fuse 40 Latch circuit 41 Timer Circuit 42 Oscillator 43 Counter circuit 44 Driver circuit 45 Potential drop curve of storage node 46 Conventional potential drop curve 50 Delay circuit 51 Delay circuit 52 Inverting circuit t Operating cycle of leak monitor circuit t4 Delay time t5 Potential drop time tREF Refresh timer Output cycle 201 Memory cell block 202 Memory cell transistor 203 Capacitor 204 Storage node 205 Cell plate node 206 Potential comparison circuit 207 Latch circuit 208 timer circuit 209 oscillation circuit 210 Counter circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-199694 (JP, A) JP-A-61-50287 (JP, A) JP-A-4-344387 (JP, A) JP-A-59-1984 207089 (JP, A) JP-A-2-195594 (JP, A) JP-A-4-252490 (JP, A) JP-A-61-190794 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/40-11/409

Claims (20)

(57) [Claims] A first electrode which is a storage node for storing electric charges and a second electrode connected to a cell plate facing the first electrode; a first electrode connected to the storage node; Two electrodes are connected to a first power supply that supplies a charge to the first electrode of the capacitor;
A main body side memory cell array in which memory cells each including a third electrode and a transistor connected to a control line for controlling the amount of charge stored in the capacitor are arranged; and data of the memory cell array on the main body side is held. A refresh timer that outputs a refresh signal for performing the following operation. The refresh timer includes: a leak monitor that detects a voltage drop due to a leak current of the memory cell array; and a detection signal that is output by the leak monitor. Pulse generating means for outputting the refresh signal and outputting a signal to a control means for controlling the leak monitoring means, wherein the leak monitoring means has the same configuration as the memory cells constituting the memory cell array on the main body side. And the third of the transistor
A dummy memory cell array in which memory cells whose electrodes are connected to the control means are arranged to generate a voltage drop due to the leak current; and any one of a storage node or a cell plate of the memory cells constituting the dummy memory cell array on the other hand, are connected, the dummy memory cell array by comparing a potential and a predetermined potential to generate a potential comparison means for outputting a signal when the potential and the predetermined potential match, the dummy memory cell array Constituent memory cell contents
A memory constituting the memory cell array on the main body side with a quantity value
By making it smaller than the cell capacitance, or
The memory cells of the memory cell array
A leak accelerating means for accelerating a voltage drop of the memory cells forming the dummy memory cell array by generating a leak current from a heat node . 2. The pulse generation unit is connected to the potential comparison unit and the control unit, and holds a received signal. The signal latch unit is connected to the signal latch unit and outputs a pulse serving as the refresh signal. 2. The semiconductor integrated circuit device according to claim 1, further comprising: an oscillating unit that performs the operation and a timer unit that includes a counter that measures a predetermined number of times of the pulse. 3. The semiconductor integrated circuit according to claim 1, wherein said pulse generation means has a delay means connected to said potential comparison means and said control means and delaying a received signal. apparatus. 4. The pulse generator according to claim 1, wherein the pulse generator outputs all the refresh signals concentrated in a part of a refresh cycle which is a cycle of generation of the detection signal. Semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 1, wherein said pulse generation means outputs said refresh signal composed of one pulse synchronized with a generation cycle of said detection signal. 6. A storage node for storing a charge.
The first electrode and the second electrode connected to the cell plate
An opposite capacitor and a first electrode are connected to the storage device.
Connected to the dynode and the second electrode is in front of the capacitor.
A first power supply for supplying a charge to the first electrode;
A third electrode controls the amount of charge stored in the capacitor.
Note composed of a transistor connected to the control line
A main body side memory cell array in which recells are arranged; and a main body side memory cell array for holding data of the memory cell array.
A refresh timer that outputs a refresh signal
The refresh timer detects a voltage drop due to a leak current of the memory cell array.
Leak monitor means for outputting, and output from the leak monitor means
And output the refresh signal.
Control means for controlling the leak monitor means.
A pulse generator for outputting a signal, wherein the leak monitor includes a memory cell constituting the memory cell array on the main body side;
The same configuration, and the third
Are arranged in a memory cell having the electrodes connected to the control means.
Causes a voltage drop due to the leak current.
A dummy memory cell array and a list of memory cells constituting the dummy memory cell array.
Connected to either the storage node or the cell plate.
And the potential generated by the dummy memory cell array
Comparing the potential with the predetermined potential,
Potential comparing means for outputting a signal when they match, and the memory cells constituting the dummy memory cell array
And a leakage accelerating means for accelerating the voltage drop of the potential comparison means, characterized in that it is connected to each cell plate of the memory cells constituting the dummy memory cell array semiconductors integrated circuits apparatus. 7. A storage node for storing charges.
The first electrode and the second electrode connected to the cell plate
An opposite capacitor and a first electrode are connected to the storage device.
Connected to the dynode and the second electrode is in front of the capacitor.
A first power supply for supplying a charge to the first electrode;
A third electrode controls the amount of charge stored in the capacitor.
Note composed of a transistor connected to the control line
A main body side memory cell array in which recells are arranged; and a main body side memory cell array for holding data of the memory cell array.
A refresh timer that outputs a refresh signal
The refresh timer detects a voltage drop due to a leak current of the memory cell array.
Leak monitor means for outputting, and output from the leak monitor means
And output the refresh signal.
Control means for controlling the leak monitor means.
A pulse generator for outputting a signal, wherein the leak monitor includes a memory cell constituting the memory cell array on the main body side;
The same configuration, and the third
Are arranged in a memory cell having the electrodes connected to the control means.
Causes a voltage drop due to the leak current.
A dummy memory cell array and a list of memory cells constituting the dummy memory cell array.
Connected to either the storage node or the cell plate.
And the potential generated by the dummy memory cell array
Comparing the potential with the predetermined potential,
Potential comparing means for outputting a signal when they match, and the memory cells constituting the dummy memory cell array
And a leakage accelerating means for accelerating the voltage drop of the leakage accelerating means, each cell plate of the memory cells constituting the dummy memory cell array characterized in that it is electrically opened semiconductors Integrated circuit device. 8. The transistor of the memory cell is an N-type transistor.
A OS transistors, the leakage accelerating means, claims, characterized in that it is connected to a high boosted power supply potentials than the first power source, wherein the dummy memory cell array is applied to the body side of the memory cell array Item 8. A semiconductor integrated circuit device according to item 7 . 9. The transistor of the memory cell is an N-type transistor.
An OS transistor, wherein the leak accelerating means is configured such that a substrate of the N-type MOS transistor on the dummy memory cell array side has a potential higher than a power supply connected to a substrate of the N-type MOS transistor on the main body side memory cell array side. Characterized by being connected to a low step-down power supply
A semiconductor integrated circuit device according to claim 7 . 10. At least one of the storage node or the cell plate on the side of the dummy memory cell array is connected to at least one spare capacitor having one electrode connected via a fuse and the other electrode grounded. 8. The semiconductor integrated circuit device according to claim 7 , wherein the capacitance value coupled to the storage node can be adjusted by cutting the fuse. 11. A first electrode is connected to at least one of the storage node or the cell plate on the dummy memory cell array side via a fuse, and a second electrode is connected to the first power supply. At least one spare transistor whose third electrode is connected to the control means is connected to the storage node, and the rate of decrease in the potential of the storage node can be adjusted by cutting the fuse. The semiconductor integrated circuit device according to claim 7 . 12. A storage node for storing charge.
A first electrode and a second electrode connected to the cell plate;
And the first electrode is connected to the storage device.
And a second electrode is connected to the capacitor
Connected to a first power supply for supplying a charge to the first electrode;
And a third electrode controls the amount of charge stored in the capacitor.
And a transistor connected to the control line
Memory cell array on the main body side in which memory cells are arranged
And a memory for holding data of the memory cell array on the main body side.
A refresh timer that outputs a refresh signal
The refresh timer detects a voltage drop due to a leak current of the memory cell array.
Leak monitor means for outputting, and output from the leak monitor means
And output the refresh signal.
Control means for controlling the leak monitor means.
A pulse generator for outputting a signal, wherein the leak monitor includes a memory cell constituting the memory cell array on the main body side;
The same configuration, and the third
Are arranged in a memory cell having the electrodes connected to the control means.
Causes a voltage drop due to the leak current.
A dummy memory cell array and a list of memory cells constituting the dummy memory cell array.
Connected to either the storage node or the cell plate.
And the potential generated by the dummy memory cell array
Comparing the potential with the predetermined potential,
Potential comparing means for outputting a signal when they match, and the memory cells constituting the dummy memory cell array
Leak accelerating means for accelerating the voltage drop of the memory cell. The leak accelerating means has a first electrode connected to each cell plate of the memory cells constituting the dummy memory cell array, and a second electrode connected to the second electrode. Connected to the power supply of the third
Semiconductors integrated circuit device you wherein a is the electrode is an auxiliary transistor being connected to said control means. 13. The semiconductor integrated circuit device according to claim 12 , wherein said second power supply is equal to a potential of said first power supply. 14. The transistor of the memory cell is an N-type MOS transistor, wherein the leak accelerating means is configured such that the dummy memory cell array has a higher potential than the first power supply applied to the main body side memory cell array. 13. The power supply according to claim 12, wherein the power supply is connected to a step-up power supply.
3. The semiconductor integrated circuit device according to 1. 15. The transistor of the memory cell is an N-type MOS transistor, wherein the leak accelerating means is configured such that the substrate of the N-type MOS transistor on the dummy memory cell array side is the N-type MOS transistor on the main body side memory cell array side. 13. The semiconductor integrated circuit device according to claim 12 , wherein the power supply is also connected to a step-down power supply having a lower potential than a power supply connected to the substrate of the type MOS transistor. 16. At least one of a storage capacitor connected to at least one of the storage node and the cell plate on the dummy memory cell array side via a fuse and a grounded other electrode is connected to at least one spare capacitor. 13. The semiconductor integrated circuit device according to claim 12 , wherein a capacitance value coupled to said storage node can be adjusted by cutting said fuse. A first electrode connected to at least one of the storage node or the cell plate on the dummy memory cell array side via a fuse; a second electrode connected to the first power supply; At least one spare transistor whose third electrode is connected to the control means is connected to the storage node, and the rate of decrease in the potential of the storage node can be adjusted by cutting the fuse. The semiconductor integrated circuit device according to claim 12 . 18. wherein, claims, characterized in that to control separately the operation of the operation and the auxiliary transistor of the transistors of the dummy memory cell array
13. The semiconductor integrated circuit device according to item 12 . 19. The same structure as the memory cell array on the main body side.
Of dummy memory cell array with memory cells
The data in the memory cell array on the main body side is determined by the retention time.
Refresh signal to output a refresh signal to hold the data
A method for adjusting a cycle of a flash timer, the method comprising: measuring an output cycle of the refresh signal.
And the specification of the devices constituting the memory cell array on the main body side.
A target value determined in advance based on the rating value and the measuring step
An evaluation step of evaluating by comparing the measured value by, when said not reached the result a target value of the evaluation refresh
An adjusting step of adjusting an output cycle of a flash signal, wherein the refresh cycle adjusting means includes a capacitor having one electrode serving as a storage node for storing charges and the other electrode connected to the cell plate facing each other. And a transistor connected between the storage node and a power supply for supplying charges to the storage node, the transistor comprising a transistor for controlling the amount of charge stored in the storage node. A first electrode is connected to at least one of the storage node or the cell plate of the cell via a fuse, a second electrode is connected to the power supply, and a third electrode controls the amount of charge stored in the capacitor. At least one spare transistor connected to the control means, The adjusting method in integer steps, lapis lazuli Fresh timer period adjustment method to <br/> and performing by cutting the fuse. 20. The same structure as the memory cell array on the main body side.
Of dummy memory cell array with memory cells
The data in the memory cell array on the main body side is determined by the retention time.
Refresh signal to output a refresh signal to hold the data
A cycle adjusting method Sshutaima over, data of devices constituting the main body of the memory cell array
Data retention time is measured under specified conditions, and
And setting the output cycle of the refresh signal to the same value as the preparation step.
A measuring step to measure under the conditions of, a target value by the preparing step, and a measured value by the measuring step
An evaluation step in which the target is not reached as a result of the evaluation.
An adjusting step of adjusting an output cycle of the flash signal, wherein the refresh cycle adjusting means is configured such that a first electrode serving as a storage node for storing charges and a second electrode connected to the cell plate face each other. The leak monitoring means, comprising: a capacitor; and a dummy memory cell connected between the storage node and a power supply for supplying charge to the storage node, the transistor including a transistor for controlling a charge accumulation amount of the storage node. A first electrode is connected to at least one of the storage node or the cell plate of the dummy memory cell via a fuse, a second electrode is connected to the power supply, and a third electrode is a charge storage amount of the capacitor. At least one spare transistor connected to control means for controlling Features and to Brighter fresh timer period adjustment method to be performed by the adjustment method in integer step of cutting the fuse.