Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JP3029681B2 - Wiring formation method - Google Patents
[go: Go Back, main page]

JP3029681B2 - Wiring formation method - Google Patents

Wiring formation method

Info

Publication number
JP3029681B2
JP3029681B2 JP03030057A JP3005791A JP3029681B2 JP 3029681 B2 JP3029681 B2 JP 3029681B2 JP 03030057 A JP03030057 A JP 03030057A JP 3005791 A JP3005791 A JP 3005791A JP 3029681 B2 JP3029681 B2 JP 3029681B2
Authority
JP
Japan
Prior art keywords
wiring
compound semiconductor
metal
substrate
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP03030057A
Other languages
Japanese (ja)
Other versions
JPH04268751A (en
Inventor
和之 猪口
昌久 池谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP03030057A priority Critical patent/JP3029681B2/en
Publication of JPH04268751A publication Critical patent/JPH04268751A/en
Application granted granted Critical
Publication of JP3029681B2 publication Critical patent/JP3029681B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、化合物半導体装置の
配線形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring of a compound semiconductor device.

【0002】[0002]

【従来の技術】化合物半導体を用い構成される例えば電
界効果トランジスタ、ダイオード等の化合物半導体素
子、これら素子を多数集積化した化合物半導体集積回路
(これらを化合物半導体装置と称することにする。)で
は、半導体素子とボンデイングパッドとの間、半導体素
子間に配線が形成される。そして、GaAs等の化合物
半導体は半絶縁性の基板が得られるため、上記配線を基
板上に直接形成しても電気的な絶縁が図れることから、
上記配線は化合物半導体基板上に直接形成されていた。
2. Description of the Related Art For example, compound semiconductor elements such as field effect transistors and diodes, which are formed using compound semiconductors, and compound semiconductor integrated circuits in which a number of these elements are integrated (these are referred to as compound semiconductor devices). Wiring is formed between the semiconductor element and the bonding pad and between the semiconductor elements. Since a semi-insulating substrate is obtained from a compound semiconductor such as GaAs, electrical insulation can be achieved even when the wiring is directly formed on the substrate.
The wiring was formed directly on the compound semiconductor substrate.

【0003】例えばGaAs基板に複数個の電界効果ト
ランジスタ(FET)を有する化合物半導体装置の配線
は、文献(沖電気研究開発134,Vol.54,N
o.2,p.23(昭和62年)では、以下に説明する
ように形成されていた。図3(A)はその説明に供する
要部平面図、図3(B)は図3(A)のP−P線に沿っ
た位置での断面図である。
For example, the wiring of a compound semiconductor device having a plurality of field effect transistors (FETs) on a GaAs substrate is described in the literature (Oki Electric R & D 134, Vol.
o. 2, p. 23 (1987), it was formed as described below. FIG. 3A is a plan view of a main part for explanation, and FIG. 3B is a cross-sectional view taken along a line PP of FIG. 3A.

【0004】先ず、FETの動作領域11、ゲート電極
13及びオーミック電極15の形成即ちFETの要部形
成が終了したGaAs基板17の、配線形成予定領域以
外の部分がフォトレジスト(図示せず)により覆われ
る。
First, a portion of the GaAs substrate 17 where the formation of the FET operating region 11, the gate electrode 13 and the ohmic electrode 15, ie, the main portion of the FET has been completed, except for the region where the wiring is to be formed is formed of a photoresist (not shown). Covered.

【0005】次に、この試料上にTi、Pt(白金)及
びAu(金)が順に真空蒸着される(図示せず)。
Next, Ti, Pt (platinum) and Au (gold) are sequentially vacuum-deposited on the sample (not shown).

【0006】次に、この試料が好適な有機溶剤中に浸漬
され上記フォトレジストが溶解されこのフォトレジスト
上のTi膜等の金属膜が共に除去(リフトオフ)され
る。Ti膜等の金属膜の残存部分により配線19が構成
される。
Next, the sample is immersed in a suitable organic solvent to dissolve the photoresist, and a metal film such as a Ti film on the photoresist is removed (lifted off). The wiring 19 is constituted by the remaining portion of the metal film such as the Ti film.

【0007】その後、GaAs基板17表面の汚染を防
止するためにこの試料上にSiN膜等の絶縁膜いわゆる
パッシベーション膜(図示せず)が例えばCVD法によ
り300〜400℃程度の温度で形成される。
Thereafter, in order to prevent contamination on the surface of the GaAs substrate 17, an insulating film such as a SiN film or a so-called passivation film (not shown) is formed on the sample at a temperature of about 300 to 400 ° C. by, for example, a CVD method. .

【0008】[0008]

【発明が解決しようとする課題】しかしながら、従来の
方法で形成した配線は、パッシベーション膜形成中に表
面状態が変化してしまうことが多かった。すなわち、従
来の配線形成方法では、平坦な表面状態の配線が得にく
かった。このため、配線抵抗の増加による素子特性劣
化、製造歩留りの低下等を招くという問題点があった。
However, the surface state of the wiring formed by the conventional method often changes during the formation of the passivation film. That is, in the conventional wiring forming method, it is difficult to obtain a wiring having a flat surface state. For this reason, there has been a problem that device characteristics are degraded due to an increase in wiring resistance, manufacturing yield is reduced, and the like.

【0009】平坦な表面状態の配線が得られにくかった
主な原因は、以下の(a)〜(d)であろうと考えられ
る。
The main reasons why it is difficult to obtain a wiring having a flat surface state are considered to be the following (a) to (d).

【0010】(a)パッシベーション膜形成中に試料に
熱が加わること。
(A) Heat is applied to the sample during the formation of the passivation film.

【0011】(b)化合物半導体と配線材料として用い
られるTi、Pt、Au、Al等とは、300℃以上の
温度で相互拡散しやすい性質を有していること。
(B) The compound semiconductor and Ti, Pt, Au, Al or the like used as a wiring material have a property of being easily diffused at a temperature of 300 ° C. or more.

【0012】(c)化合物半導体表面には必ず自然酸化
膜(図3(B)中21で示すもの)が存在し、或は配線
形成工程前までの工程中において薬品や熱の作用により
1〜2nm程度の膜厚の自然酸化膜が形成される。しか
し、これら自然酸化膜は、その膜質が良好ではなく膜厚
も不均一なことが多い。これがため、配線金属及び化合
物半導体基板間の相互拡散を不均一なものとする。ま
た、配線金属が酸化しやすい金属である場合(上記Ti
はこれに該当する。)この自然酸化膜中の酸素は配線金
属によって還元され配線金属の一部を酸化するが、自然
酸化膜の膜質・膜厚が不均一であるため、配線金属の一
部酸化も不均一に行われる。
(C) A natural oxide film (shown at 21 in FIG. 3 (B)) always exists on the surface of the compound semiconductor, or 1 to 3 due to the action of chemicals or heat before the wiring forming step. A natural oxide film having a thickness of about 2 nm is formed. However, these natural oxide films often have poor film quality and uneven thickness. This makes the interdiffusion between the wiring metal and the compound semiconductor substrate non-uniform. When the wiring metal is a metal that is easily oxidized (the above-mentioned Ti
Corresponds to this. The oxygen in the natural oxide film is reduced by the wiring metal and oxidizes a part of the wiring metal. However, since the film quality and thickness of the natural oxide film are not uniform, the partial oxidation of the wiring metal is also unevenly performed. Will be

【0013】(d)例えば、製造工程中のフォトリソグ
ラフィ工程におけるレジスト残膜を除去するためのアッ
シング工程において露出した化合物半導体基板部分が酸
素プラズマにさらされ酸化されると、これで形成された
酸化物が不安定なために凝集し表面形状を悪化させる。
(D) For example, when a portion of the compound semiconductor substrate exposed in an ashing process for removing a resist remaining film in a photolithography process in a manufacturing process is exposed to oxygen plasma and oxidized, the oxidation formed by the exposure is performed. Since the material is unstable, it aggregates and deteriorates the surface shape.

【0014】この発明はこのような点に鑑みなされたも
のであり、従ってこの発明の目的は、化合物半導体下地
上に酸化しやすい金属から成る配線又は該金属を最下層
とする多層配線を形成するに当たり、配線形成後に該配
線に熱が加わった場合でも従来より安定な配線を形成す
ることが出来る方法を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to form a wiring made of a metal which is easily oxidized or a multilayer wiring having the metal as the lowermost layer on a compound semiconductor base. In view of the above, an object of the present invention is to provide a method capable of forming a more stable wiring even if heat is applied to the wiring after the wiring is formed.

【0015】[0015]

【課題を解決するための手段】この目的の達成を図るた
め、この出願に係る発明者は種々の研究を重ねた。その
結果、化合物半導体下地の配線形成予定領域に良質な酸
化膜を積極的に形成することによりこの発明の目的を達
成出来ると考えた。
Means for Solving the Problems In order to achieve this object, the inventors of the present application have made various studies. As a result, it has been considered that the object of the present invention can be achieved by positively forming a high-quality oxide film in a region where a wiring is to be formed under the compound semiconductor.

【0016】従ってこの発明によれば、化合物半導体下
地上に酸化しやすい金属から成る配線又は該金属を最下
層とする多層配線を形成するに当たり、波長185nm
の光及び波長254nmの光を含む紫外線並びに酸素を
加熱した化合物半導体下地表面に均一に接触させ該下地
表面に該下地の酸化膜を形成し、然る後当該配線を形成
することを特徴とする。
Therefore, according to the present invention, when forming a wiring made of a metal that is easily oxidized or a multilayer wiring having the metal as the lowermost layer on the compound semiconductor base, the wavelength is 185 nm.
And an ultraviolet ray including light having a wavelength of 254 nm and oxygen are uniformly brought into contact with the heated surface of the compound semiconductor base to form an oxide film on the base, and thereafter, the wiring is formed. .

【0017】ここで、化合物半導体下地とは、GaAs
基板、InP基板、GaP基板、InAs基板等の各種
化合物半導体基板そのものの場合、これら基板に素子が
作り込まれた中間体の場合等、配線が形成され得る広く
下地をいう。
Here, the compound semiconductor base is GaAs.
In the case of various compound semiconductor substrates such as a substrate, an InP substrate, a GaP substrate, an InAs substrate, etc., it refers to a broad base on which wiring can be formed, such as an intermediate in which elements are formed on these substrates.

【0018】また、化合物半導体下地を加熱する方法と
しては、例えば化合物半導体下地自体を例えばヒータ、
ランプ等を用いて加熱する方法、誘導加熱により加熱す
る方法等を挙げることが出来る。
As a method of heating the compound semiconductor base, for example, the compound semiconductor base itself is heated by, for example, a heater,
A method of heating using a lamp or the like, a method of heating by induction heating, and the like can be given.

【0019】また、加熱温度は、あまり低いと酸化膜の
形成速度が遅すぎ実用的ではなくあまり高いと例えば化
合物半導体下地の構成元素の蒸発等の異常現象が生じる
ので、これらを考慮した適正値とするのが良い。例えば
化合物半導体下地としてGaAs基板を用いる場合は、
100℃〜300℃の範囲内の温度とするのが好適であ
る。この範囲であると、実用的な速度で酸化膜を形成出
来かつGaAs基板からの砒素抜けを防止出来るからで
ある。なお、酸化膜の形成速度は酸素ガス濃度にも依存
するので、この条件も、使用装置等を考慮し決定する。
If the heating temperature is too low, the formation rate of the oxide film is too slow to be practical, and if it is too high, abnormal phenomena such as evaporation of the constituent elements of the compound semiconductor base will occur. Good to be. For example, when a GaAs substrate is used as a compound semiconductor base,
The temperature is preferably in the range of 100 ° C to 300 ° C. This is because, if it is in this range, an oxide film can be formed at a practical speed and arsenic can be prevented from being removed from the GaAs substrate. Since the formation rate of the oxide film also depends on the oxygen gas concentration, this condition is also determined in consideration of a device to be used and the like.

【0020】また、この発明の方法により形成する酸化
膜の膜厚は、薄すぎては酸化膜が島状構造となり配線金
属及び化合物半導体下地間に均一な膜質・膜厚の酸化膜
を形成する目的に合わない。また厚すぎる必要もない。
従って、必要最小限の膜厚にすれば良い。少なくとも3
nm以上とするのが好適である。
On the other hand, if the thickness of the oxide film formed by the method of the present invention is too small, the oxide film has an island structure, and an oxide film having a uniform film quality and thickness is formed between the wiring metal and the compound semiconductor base. Not fit for purpose. Nor do they need to be too thick.
Accordingly, the film thickness may be set to the minimum necessary. At least 3
It is preferable that the thickness be not less than nm.

【0021】[0021]

【作用】この発明によれば、化合物半導体下地表面には
自然酸化膜に比べ膜質均一性・膜厚均一性ともに優れる
酸化膜が形成される。このため、化合物半導体下地と配
線金属との間の相互拡散が配線全域で均一に起るか或は
均一に抑制される。
According to the present invention, an oxide film having excellent film quality uniformity and film thickness uniformity is formed on the surface of a compound semiconductor base as compared with a natural oxide film. For this reason, the interdiffusion between the compound semiconductor base and the wiring metal uniformly occurs or is suppressed uniformly throughout the wiring.

【0022】さらに、この酸化膜上に形成される酸化し
やすい金属から成る配線又は該金属を最下層とする多層
配線は、この酸化膜の膜質・膜厚が均一であるため酸化
膜と接する部分が均一に酸化物になる。実施例の例でい
えばTi/Pt/Auから成る多層配線の最下層を構成
するTi膜の化合物半導体下地側には均一なTiOX
形成される。この酸化物は安定かつピンホールが非常に
少い良質な膜となるためこれによっても化合物半導体下
地と配線金属との間の相互拡散が抑制される。
Further, the wiring made of a metal which is easily oxidized or the multilayer wiring having the metal as the lowermost layer formed on the oxide film is in contact with the oxide film because the quality and thickness of the oxide film are uniform. Becomes uniformly oxide. In the example of the embodiment, uniform TiO X is formed on the compound semiconductor underlayer side of the Ti film constituting the lowermost layer of the multilayer wiring composed of Ti / Pt / Au. Since this oxide is a high-quality film that is stable and has very few pinholes, this also suppresses interdiffusion between the compound semiconductor base and the wiring metal.

【0023】[0023]

【実施例】以下、図面を参照してこの発明の配線形成方
法の実施例について説明する。なお、この実施例は半絶
縁性GaAs基板に複数個の電界効果トランジスタ(F
ET)を有する化合物半導体下地にTi、Pt及びAu
から成る多層配線(Tiが最下層)を形成する例であ
る。ここで、図2(A)及び(B)並びに図1(A)〜
(C)は、その説明に供する工程図である。特に、図2
(A)は半絶縁性GaAs基板に複数個の電界効果トラ
ンジスタを有する化合物半導体下地の一部をGaAs基
板上方から見て概略的に示した平面図、図2(B)は図
2(A)のQ−Q線位置での断面図である。また、図1
(A)〜(C)は図2に示した化合物半導体下地に配線
を形成する手順を図2(B)に対応する断面により示し
た図である。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a wiring forming method according to an embodiment of the present invention; In this embodiment, a plurality of field effect transistors (F
Et, Ti, Pt and Au
This is an example of forming a multi-layer wiring (Ti is the lowermost layer) composed of. Here, FIGS. 2A and 2B and FIGS.
(C) is a process drawing provided for the explanation. In particular, FIG.
2A is a plan view schematically showing a part of a compound semiconductor base having a plurality of field-effect transistors on a semi-insulating GaAs substrate as viewed from above the GaAs substrate, and FIG. 2B is a plan view of FIG. FIG. 3 is a cross-sectional view taken along line QQ of FIG. FIG.
FIGS. 3A to 3C are diagrams showing a procedure for forming wiring on the compound semiconductor base shown in FIG. 2 by a cross section corresponding to FIG.

【0024】先ず、図2(A)及び(B)に示すよう
に、直径が3インチ(1インチは約2.54cm。以
下、同様。)の半絶縁性GaAs基板31の所定領域
に、公知のイオン注入技術及びアニール技術によりFE
Tの動作領域33を形成し、さらに、公知の成膜方法及
びフォトリソグラフィ技術によりゲート電極35、ソー
ス・ドレインとなるオーミック電極37をそれぞれ形成
する。
First, as shown in FIGS. 2A and 2B, a predetermined area of a semi-insulating GaAs substrate 31 having a diameter of 3 inches (1 inch is approximately 2.54 cm; the same applies hereinafter) is provided. FE by ion implantation technology and annealing technology
An operation region 33 of T is formed, and a gate electrode 35 and ohmic electrodes 37 serving as a source / drain are formed by a known film forming method and a photolithography technique.

【0025】ゲート電極35は例えばタングステン
(W)を含む合金であるW−Al等、Wを含む化合物で
あるWSi、WN等、または基板側から順に積層したT
i、Pt及びAu等の多層金属で構成出来る。また、オ
ーミック電極は例えば基板側から順に積層したAuG
e、Ni及びAuから成る多層金属で構成出来る。もち
ろんこれらに限られず他の材料でも良い。
The gate electrode 35 is made of, for example, an alloy containing tungsten (W), such as W-Al, a compound containing W, such as WSi or WN, or a T-layer laminated in order from the substrate side.
It can be composed of a multilayer metal such as i, Pt, and Au. Further, the ohmic electrode is, for example, AuG laminated in order from the substrate side.
It can be composed of a multilayer metal composed of e, Ni and Au. Of course, other materials may be used without being limited to these.

【0026】次に、能動領域33、オーミック電極37
等が形成されたGaAs基板31を低圧水銀灯(300
Wの出力のもの)装備の容量が約2l(リットル)の容
器内に設置する。GaAs基板と低圧水銀灯との距離は
この実施例の場合5cmとしている。次いで、このGa
As基板を100℃に加熱しかつこれに低圧水銀灯から
の光を照射しながら容器内に10l(リットル)/分の
割合で酸素を流す。このようにして、波長185nmの
光及び波長254nmの光を含む紫外線並びに酸素をG
aAs基板31に加熱状態で接触させる。この際、容器
内にオゾンが発生していることが確認された。なお、酸
素及び紫外線が基板に均一に接触するように、基板設置
位置、低圧水銀灯設置位置、及び酸素供給方法を工夫し
た。
Next, the active region 33 and the ohmic electrode 37
The GaAs substrate 31 on which is formed a low-pressure mercury lamp (300
It is installed in a container with a capacity of about 2 liters. In this embodiment, the distance between the GaAs substrate and the low-pressure mercury lamp is 5 cm. Then, this Ga
While heating the As substrate to 100 ° C. and irradiating it with light from a low-pressure mercury lamp, oxygen is flowed into the container at a rate of 10 l (liter) / min. In this manner, ultraviolet light including light having a wavelength of 185 nm and light having a wavelength of 254 nm and oxygen
The substrate is brought into contact with the aAs substrate 31 in a heated state. At this time, it was confirmed that ozone was generated in the container. The substrate installation position, the low-pressure mercury lamp installation position, and the oxygen supply method were devised so that oxygen and ultraviolet light uniformly contacted the substrate.

【0027】上述の処理を1分間行ったところ、GaA
s基板31の、ゲート電極35で覆われた部分及びオー
ミック電極37で覆われた部分以外の表面に膜厚が3n
mの酸化膜39が形成出来た。また、この酸化工程にお
いて、ゲート電極35の表面及びオーミック電極37の
表面はほとんど酸化されていないことが分った(図1
(A))。また、3インチのGaAs基板内の各所での
酸化膜39の膜厚を測定し膜厚分布を求めた。その分布
の標準偏差は0.3nmであることが分った。これらの
ことより、この発明に係る酸化膜の形成方法は素子にダ
メージを与えることなく膜厚が均一な酸化膜形成が可能
なことが理解できる。
When the above processing was performed for 1 minute, GaAs
On the surface of the s-substrate 31 other than the portion covered with the gate electrode 35 and the portion covered with the ohmic electrode 37, the film thickness is 3n.
m of the oxide film 39 was formed. Also, it was found that the surface of the gate electrode 35 and the surface of the ohmic electrode 37 were hardly oxidized in this oxidation step (FIG. 1).
(A)). Further, the thickness of the oxide film 39 at various points in the 3-inch GaAs substrate was measured to determine the thickness distribution. The standard deviation of the distribution was found to be 0.3 nm. From these facts, it can be understood that the oxide film forming method according to the present invention can form an oxide film having a uniform thickness without damaging the element.

【0028】次に、酸化膜39形成済みGaAs基板3
1の配線形成予定領域以外の領域を例えばフォトレジス
ト41により覆う。その後、この試料を例えば真空蒸着
装置(図示せず)内に設置する。そして、この試料上に
この場合Tiを100nmの膜厚で、Ptを50nmの
膜厚で、Auを300nmの膜厚で順に形成する。これ
により、試料上に酸化しやすい金属(この場合Ti)を
最下層とする多層配線用薄膜43を形成する(図2
(B))。
Next, the GaAs substrate 3 on which the oxide film 39 has been formed
A region other than the one wiring formation planned region is covered with, for example, a photoresist 41. Thereafter, the sample is placed in, for example, a vacuum evaporation apparatus (not shown). Then, in this case, Ti is formed in a thickness of 100 nm, Pt is formed in a thickness of 50 nm, and Au is formed in a thickness of 300 nm in this case. As a result, a thin film 43 for a multilayer wiring is formed on the sample with a metal (in this case, Ti) which is easily oxidized as the lowermost layer (FIG. 2).
(B)).

【0029】次に、多層配線用薄膜43の不要部分をリ
フトオフ法により除去することにより酸化しやすい金属
を最下層とする多層配線(Ti/Pt/Au)43aが
形成出来る(図1(C))。
Next, by removing unnecessary portions of the multilayer wiring thin film 43 by a lift-off method, a multilayer wiring (Ti / Pt / Au) 43a having easily oxidizable metal as the lowermost layer can be formed (FIG. 1C). ).

【0030】このように形成された多層配線43aの表
面形状(モルフォロジー)は、平坦でありかつその後の
パッシベーション膜形成のためのCVD工程における3
00〜400℃の熱によっても変化しないことが分っ
た。
The surface shape (morphology) of the multilayer wiring 43a formed in this manner is flat, and is 3D in the subsequent CVD process for forming a passivation film.
It was found that there was no change even with heat of 00 to 400 ° C.

【0031】上述においてはこの発明の配線形成方法の
実施例について説明したが、この発明は上述の実施例の
みに限られるものではなく、以下に説明するような変更
を加えることが出来る。
Although the embodiment of the wiring forming method of the present invention has been described above, the present invention is not limited to the above-described embodiment, and the following modifications can be added.

【0032】例えば、上述の実施例では酸素流量を10
l(リットル)/分としていたが、酸素流量を1〜50
l(リットル)/分の範囲で実験を行ったところいずれ
のの場合も実施例と同様な効果が得られた。
For example, in the above embodiment, the oxygen flow rate is set to 10
1 (liter) / minute, but the oxygen flow rate is 1 to 50
Experiments were performed in the range of 1 (liter) / min. In each case, the same effect as in the example was obtained.

【0033】また、上述の実施例では、配線をTiを最
下層とするTi/Pt/Auの三層配線としていたが、
Ti/Al、Ti/Auのような二層配線を形成する場
合、また酸化しやすい金属のみで配線を構成した場合も
実施例と同様な効果が得られることは明らかである。
In the above embodiment, the wiring is a three-layered wiring of Ti / Pt / Au with Ti being the lowermost layer.
It is apparent that the same effect as that of the embodiment can be obtained when a two-layer wiring such as Ti / Al or Ti / Au is formed, or when the wiring is formed only of a metal which is easily oxidized.

【0034】また、上述の実施例では酸化しやすい金属
としてTiを用いていたがこれに限られない。例えば、
Ni(ニッケル)やAl(アルミニウム)を用いた場合
でも実施例と同様な効果が得られることは明らかであ
る。
Further, in the above-described embodiment, Ti is used as the easily oxidizable metal, but the present invention is not limited to this. For example,
It is clear that the same effects as in the embodiment can be obtained even when Ni (nickel) or Al (aluminum) is used.

【0035】また、上述の実施例では化合物半導体下地
をFETの形成されたGaAs基板としていたがこれに
限られない。例えばInP基板、GaP基板、InAs
基板II−VI族化合物半導体基板等も低圧水銀灯からの光
及び酸素によりその表面に酸化膜形成が可能なことから
これらもこの発明の対象となる。
Further, in the above-described embodiment, the GaAs substrate on which the FET is formed is used as the compound semiconductor base, but the present invention is not limited to this. For example, InP substrate, GaP substrate, InAs
Substrates II-VI compound semiconductor substrates and the like can also form oxide films on their surfaces by light and oxygen from a low-pressure mercury lamp, and these are also objects of the present invention.

【0036】また、この発明の電極形成方法はシリコン
基板、ゲルマニウム基板、基板、SiC基板、ボロンナ
イトライド基板、タンタルナイトライド基板に配線を形
成する場合の適用も期待出来る。
The electrode forming method of the present invention can also be expected to be applied to the case where wiring is formed on a silicon substrate, a germanium substrate, a substrate, a SiC substrate, a boron nitride substrate, or a tantalum nitride substrate.

【0037】[0037]

【発明の効果】上述した説明からも明らかなように、こ
の発明の配線形成方法によればに、酸化しやすい金属か
ら成る配線又は該金属を最下層とする多層配線が形成さ
れる化合物半導体下地に対し、当該配線形成前に良質な
酸化膜を積極的に形成しその後当該配線を形成するよう
にしたので、化合物半導体下地と配線金属との間の相互
拡散が配線全域で均一に起るか或は均一に抑制される。
さらに、配線のこの酸化膜と接する部分が均一に酸化物
になるのでこれによっても化合物半導体下地と配線金属
との間の相互拡散が抑制される。
As is apparent from the above description, according to the wiring forming method of the present invention, a compound semiconductor base on which a wiring made of a metal which is easily oxidized or a multilayer wiring having the metal as the lowermost layer is formed. In contrast, a high-quality oxide film was positively formed before the formation of the wiring and the wiring was formed thereafter, so that mutual diffusion between the compound semiconductor base and the wiring metal occurs uniformly in the entire wiring. Alternatively, it is uniformly suppressed.
Furthermore, since the portion of the wiring that is in contact with the oxide film is uniformly made of oxide, this also suppresses the interdiffusion between the compound semiconductor base and the wiring metal.

【0038】これがため、配線形成後に配線に熱が加わ
った場合でも従来より安定な配線を形成することが出
来、ひいては、高温で半導体装置を動作しても特性が変
化しない効果が期待出来る。
Therefore, even if heat is applied to the wiring after the formation of the wiring, it is possible to form a more stable wiring than before, and it is expected that the characteristics will not change even if the semiconductor device is operated at a high temperature.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(A)〜(C)は、実施例の配線形成方法の説
明に供する工程図である。
FIGS. 1A to 1C are process diagrams for explaining a wiring forming method according to an embodiment;

【図2】(A)及び(B)は、実施例で用いた化合物半
導体下地の説明に供する図である。
FIGS. 2A and 2B are views for explaining a compound semiconductor base used in Examples.

【図3】(A)及び(B)は、従来技術の説明に供する
図である。
FIGS. 3A and 3B are diagrams for explaining a conventional technique.

【符号の説明】[Explanation of symbols]

31:半絶縁性のGaAs基板 33:動作領域 35ゲート電極 37:オーミック
電極 39:酸素及び紫外線を用い形成した酸化膜 41:フォトレジスト 43:酸化しやすい金属を最下層とする多層配線用薄膜 43a:酸化しやすい金属を最下層とする多層配線
31: Semi-insulating GaAs substrate 33: Operating region 35 Gate electrode 37: Ohmic electrode 39: Oxide film formed using oxygen and ultraviolet light 41: Photoresist 43: Multilayer wiring thin film 43a having easily oxidizable metal as the lowermost layer 43a : Multilayer wiring with metal that is easily oxidized as the bottom layer

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/3205 - 21/3213 H01L 21/768 ──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/3205-21/3213 H01L 21/768

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 化合物半導体下地上に酸化しやすい金属
から成る配線又は該金属を最下層とする多層配線を形成
するに当たり、波長185nmの光及び波長254nm
の光を含む紫外線並びに酸素を、加熱した化合物半導体
下地表面に均一に接触させて該下地表面に該下地の酸化
膜を形成し、然る後当該配線を形成することを特徴とす
る配線形成方法。
In forming a wiring made of a metal that is easily oxidized or a multilayer wiring having the metal as the lowermost layer on a compound semiconductor base, light having a wavelength of 185 nm and a wavelength of 254 nm are used.
Forming an oxide film on the underlying surface of the compound semiconductor by uniformly contacting ultraviolet light and oxygen containing the above light with the heated surface of the underlying compound semiconductor, and thereafter forming the wiring. .
【請求項2】 請求項1に記載の配線形成方法におい
て、酸化しやすい前記金属をチタン(Ti)、ニッケル
(Ni)及びアルミニウム(Al)から選ばれた1種以
上の金属としたことを特徴とする配線形成方法。
2. The wiring forming method according to claim 1, wherein said easily oxidizable metal is at least one metal selected from titanium (Ti), nickel (Ni) and aluminum (Al). Wiring forming method.
JP03030057A 1991-02-25 1991-02-25 Wiring formation method Expired - Fee Related JP3029681B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03030057A JP3029681B2 (en) 1991-02-25 1991-02-25 Wiring formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03030057A JP3029681B2 (en) 1991-02-25 1991-02-25 Wiring formation method

Publications (2)

Publication Number Publication Date
JPH04268751A JPH04268751A (en) 1992-09-24
JP3029681B2 true JP3029681B2 (en) 2000-04-04

Family

ID=12293200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03030057A Expired - Fee Related JP3029681B2 (en) 1991-02-25 1991-02-25 Wiring formation method

Country Status (1)

Country Link
JP (1) JP3029681B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6279902B1 (en) 1992-10-22 2001-08-28 Semiconductor Energy Laboratory Co., Ltd. Game system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6279902B1 (en) 1992-10-22 2001-08-28 Semiconductor Energy Laboratory Co., Ltd. Game system

Also Published As

Publication number Publication date
JPH04268751A (en) 1992-09-24

Similar Documents

Publication Publication Date Title
KR900008277B1 (en) Manufacturing Method of Field Effect Transistor
KR910006673B1 (en) Manufacturing Method of Semiconductor Device
JP3077524B2 (en) Method for manufacturing semiconductor device
JPS6164171A (en) Manufacture of semiconductor element
JP3240725B2 (en) Wiring structure and its manufacturing method
JPH06310492A (en) Titanium-based thin film etching solution and method for manufacturing semiconductor device
JP3029681B2 (en) Wiring formation method
JPS61105845A (en) Opening formation
JPS59175726A (en) Manufacture of semiconductor device
JPH01244666A (en) Manufacture of semiconductor device
JPH0361346B2 (en)
TWI922212B (en) Thin film transistor
JP3081361B2 (en) Method for manufacturing semiconductor device
JPH118396A (en) Method of manufacturing thin film transistor and thin film transistor
US20260032965A1 (en) Thin-film transistors and related methods of manufacture with metal nitride source/drain
US7183151B2 (en) Method for fabricating field effect transistor
KR100269519B1 (en) Method of forming photoresist pattern on metal layer and method of fabricating liquid crystal display
JPH022639A (en) Manufacture of field effect transistor
JPH0653249A (en) Method for manufacturing semiconductor device
JPH04101445A (en) Manufacture of semiconductor device
JPH0447970B2 (en)
JP2835398B2 (en) Manufacturing method of field effect transistor
JPH05167063A (en) Ohmic electrode, its formation method and semiconductor device
JPS6314478A (en) Method for manufacturing field effect transistors
JPH09293735A (en) Method for manufacturing field effect transistor

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20000125

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090204

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090204

Year of fee payment: 9

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100204

Year of fee payment: 10

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees