JP3032172B2 - Address decode circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NAND circuit type address decode circuit for decoding an address signal, and more particularly to a CMOS address decode circuit configured using P-channel and N-channel MISFETs.

[0002]

2. Description of the Related Art Generally, an address decode circuit used in a semiconductor memory device comprises a P-channel side logic block composed of a plurality of P-channel enhancement-type MISFETs and a plurality of N-channel enhancement-type MISFETs. It is composed of an N-channel side logic block.

FIG. 6 is a block diagram of a conventional address decoding circuit. A positive power supply voltage V _DD is applied to a P-channel side logic block 51, and a 0 V is applied to an N-channel side logic block 52.
A reference voltage V _SS of V is supplied. And
Address signals A0 to An to be supplied to the gates of the respective MISFETs in the P-channel side logic block 51 and the N-channel side logic block 52 are supplied through a plurality of input wirings 53. In addition, the corresponding outputs of the two logic blocks 51 and 52 are connected to a plurality of output wires 54 in a wiring space existing between the two logic blocks. This address decode circuit is a so-called NAND circuit system, in which several sets of P-channel MISFETs connected in parallel in the P-channel side logic block 51 are connected in series in the N-channel side logic block 52. Some N-channel M
Each of the ISFETs is provided, and one partial decoding circuit is constituted by one set of P-channel MISFETs connected in parallel and one set of N-channel MISFETs connected in series. Therefore, this address decode circuit is composed of a set of partial decode circuits.

FIG. 7 shows a configuration of one partial decode circuit of the conventional address decode circuit. The two P-channel MISFETs QP1 and QP2 provided in the P-channel side logic block 51 are connected in parallel between the power supply voltage V _DD application point and the output node. Also,
The two N-channel MISFETs QN1 and QN2 provided in the N-channel side logic block 52 are connected to a reference voltage V _SS.
And the output node is connected in series. An address signal IN is applied to each gate of the P-channel MISFET QP1 and the N-channel MISFET QN1.
1 is input to the gates of the P-channel MISFET QP2 and the N-channel MISFET QN2.
N2 is input, and an output signal OUT is output from the output node.

FIG. 8 is a pattern plan view showing the element structure of a portion corresponding to the partial decode circuit of FIG. 7 when the conventional address decode circuit is actually integrated. In the figure, reference numeral 61 denotes a power supply wiring made of aluminum for transmitting a power supply voltage V _DD , 62 denotes a power supply wiring made of aluminum for transmitting a reference voltage V _SS , and 63, 64, and 65 denote the P-channel MISFETs QP1, QP1, respectively. P-type diffusion regions serving as source and drain regions of QP2, 66, 67, and 68 are source-drain regions of the N-channel MISFETs QN1 and QN2 and N-type diffusion regions serving as a part of the output wiring, respectively. Polysilicon wirings serving as gate electrodes of the MISFETs, 71 and 72 are signal wirings made of aluminum for providing input signals IN1 and IN2 to the polysilicon wirings 69 and 70, respectively, and 73 is a P channel MI.
The above P which becomes a common drain region of the SFETs QP1 and QP2
This is a jumper wiring made of aluminum for connecting the N-type diffusion region 64 and the N-type diffusion region 68 serving as the drain region of the N-channel MISFET QN1.

[0006]

By the way, in the above-mentioned conventional address decode circuit, a large number of partial decode circuits as shown in the pattern plan view of FIG. 8 are formed on a chip. It is necessary to provide a signal wiring for supplying an address signal outside the logic block, which requires a wide wiring area.
Further, since the address decode circuit is configured by a set of a large number of partial decode circuits, the layout of the partial decode circuit becomes complicated as the memory capacity increases,
There is a problem that the area occupied on the chip increases. Further, it is necessary to use a jumper wiring in the logic block in order to extract an output signal in each partial decoding circuit. As a result, the area occupied by each partial decoding circuit becomes large, and in particular, the memory capacity increases and the address signal This becomes remarkable as the number of bits increases.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an address decoding circuit capable of reducing the area occupied on a chip.

[0008]

According to the present invention, there is provided an address decode circuit comprising a plurality of partial decode circuits for decoding an address signal, wherein the first logical block includes a plurality of first channel type MISFETs. A plurality of second channel type MISFETs are provided, and a second logic block is provided adjacent to the first logic block in the first direction, and traverses the first and second logic blocks. A plurality of MISFETs for transmitting the address signal to be supplied to the respective gates of the first channel type and second channel type MISFETs in the first and second logic blocks. The address input wiring and the plurality of address input wirings
The first and second logic blocks
Power supply wiring for supplying a power supply voltage and a reference voltage to the
The first direction from one side of the array of the first and second logical blocks
And an output wiring that is arranged so as to be taken out in a second direction intersecting the direction and that connects the outputs of the first and second logic blocks.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments with reference to the drawings. FIG. 1 is a block diagram of an address decoding circuit according to the present invention. The P-channel logic block 11 is supplied with a positive power supply voltage V _DD , and the N-channel logic block 12 provided adjacent to the P-channel logic block 11 is supplied with a reference voltage V _{SS of} 0 V. ing. This address decode circuit is a so-called NAND circuit system, in which several sets of P-channel MISFETs connected in parallel in the P-channel side logic block 11 are connected in series in the N-channel side logic block 12. Several sets of N-channel MISFETs are provided, respectively, and one partial decode circuit is constituted by one set of P-channel MISFETs connected in parallel and one set of N-channel MISFETs connected in series.

Further, a plurality of address input wirings 13, 13,... Are provided so as to continuously cross the P-channel side logic block 11 and the N-channel side logic block 12. The corresponding outputs of the two logic blocks 11 and 12 are connected to a plurality of output wirings 14 and 14 outside the two logic blocks.
Connected to ...

FIG. 2 shows the configuration of one partial decoding circuit of the address decoding circuit of the above embodiment. In the P channel side logic block 11, two P channel enhancement type MISFETs QP1, QP
P2 is provided, and both MISFETs are connected in parallel between the application point of the power supply voltage V _DD and the output wiring 14. Two N-channel enhancement-type MISFETs QN1 and QN2 are provided in the N-channel side logic block 12, and both MISFETs are connected in series between the point to which the reference voltage V _SS is applied and the output wiring 14. ing. An input wiring to which an address signal IN1 is applied to each gate of the P-channel MISFET QP1 and the N-channel MISFET QN1
13-1 is connected, and P-channel MISFETs QP2 and N
An input line 13-2 to which an address signal IN2 is applied is connected to each gate of the channel MISFET QN2.

Here, the two input wirings 13-1 and 13-2 are used.
Are provided so as to traverse the P-channel side logic block 11 and the N-channel side logic block 12, so that a wide address for supplying an address signal to a large number of partial decode circuits as in the prior art is provided. No input wiring area is required.

FIG. 3 shows an address decoding circuit according to the above-described embodiment, in which the address signals are A0, / A0 to A2, /
FIG. 3 is a circuit diagram showing the entire configuration when the number of bits is A3, that is, 3 bits. In this case, the P-channel side logical block is
Two blocks 11-1 and 11-2 are provided, and two N-channel side logic blocks 12-1 and 12-2 are provided. In the one P-channel side logic block 11-1, three P-channel enhancement-type MISFETs QP11 and QP1 each having a source and a drain connected in parallel are provided.
2, QP13, QP14, QP15, QP16, QP17, QP18
, QP19, QP20, QP21, and QP22. The common sources of the MISFETs QP11, QP12, and QP13 are connected to the point to which the power supply voltage _VDD is applied, and the common drain is connected to the output wiring 14a for obtaining the output signal Q1. Similarly, the MISFETs QP14, QP15, QP16
_Are connected to the point of application of the power supply voltage V _DD , and these common drains are connected to the output wiring 14b for obtaining the output signal Q2.
It is connected to the. Similarly, the MISFET QP17
, QP18, QP19 have a common source connected to the point to which the power supply voltage _VDD is applied, and a common drain connected to an output line 14c for obtaining an output signal Q3. Similarly, the MI
The common sources of the SFETs QP20, QP21, and QP22 are connected to the point to which the power supply voltage _VDD is applied, and their common drain is connected to the output wiring 14d for obtaining the output signal Q4.

The one N-channel logic block 12-1 is provided adjacent to the P-channel logic block 11-1. In the logic block 12-1, a source and a drain are connected in series. Three N-channel enhancement-type MISFETs QN11 and QN12
, QN13, QN14, QN15, QN16, QN17, QN18
, QN19, QN20, QN21, QN22. The MISFETs QN13, QN16, QN19
, QN22 are connected to the output wirings 14a, 14b, 1
4c and 14d, respectively.

Further, the N-channel side logic block 12-
1. The other N-channel side logic block 12-2 is provided adjacent to 1. In this logic block 12-2, three N-channel enhancement type transistors each having a source and a drain connected in series are provided. MISFET QN31,
QN32, QN33, QN34, QN35, QN36, QN37, Q
N38, QN39, QN40, QN41, QN42 are provided. The MISFETs QN33, QN36, QN3
9, QN42 have output signals Q5, Q6, Q
7 and Q8 are connected to output wirings 14e, 14f, 14g, and 14h, respectively.

Adjacent to the N-channel side logic block 12-2, another P-channel side logic block 11-2 is provided. In the logic block 12-2, the source and the drain are connected in parallel. Three MISFETs QP31, QP32 of enhancement type with each
, QP33, QP34, QP35, QP36, QP37, QP38,
QP39, QP40, QP41 and QP42 are provided. The common sources of the MISFETs QP31, QP32, and QP33 are connected to the point to which the power supply voltage V _DD is applied, and the common drain is connected to the output wiring 14e. Similarly, a common source of the MISFETs QP34, QP35, and QP36 is connected to a point to which the power supply voltage V _DD is applied, and a common drain thereof is connected to the output wiring 14f. Similarly, the common sources of the MISFETs QP37, QP38, and QP39 are connected to the point to which the power supply voltage V _DD is applied, and the common drain is connected to the output wiring 14g. Similarly, the common sources of the MISFETs QP40, QP41, and QP42 are connected to the point to which the power supply voltage V _DD is applied, and the common drain is connected to the output wiring 14h.

The logic blocks 11-1, 12-1,.
Six input wirings 13a to 13f are provided so as to continuously traverse the insides of 12-2 and 11-2. And input wiring 13
a transmitted on the P channel MI
SFET QP20, QP14, N-channel MISFET
QN14, QN20, QN31, QN37, P-channel MISF
It is supplied to the gates of ET QP34 and QP40. The inverted address signal of the address signal A0 transmitted on the input wiring 13b is a P-channel MISFET QP19, QP11, N
Channel MISFETs QN11, QN17, QN34, QN4
0 is supplied to the gates of the P-channel MISFETs QP31 and QP37. The address signal A1 transmitted on the input line 13c is applied to the P-channel MISFETs QP21 and QP18.
, N channel MISFETs QN18, QN21, QN32
, QN35 and P-channel MISFETs QP38 and QP41. The inverted address signal of the address signal A1 transmitted on the input line 13d is
SFET QP15, QP12, N-channel MISFET
QN12, QN15, QN38, QN41, P-channel MISF
It is supplied to the gates of ET QP32 and QP35. The address signal A2 transmitted on the input wiring 13e is supplied to the N-channel MISFETs QN33, QN36, QN39, QN42 and the P-channel MISFETs QP33, QP36, QP39, QP42.
Is supplied to each gate. The inverted address signal of the address signal A2 transmitted on the input wiring 13f is a P-channel MISFET QP22, QP19, QP16, QP13,
N-channel MISFETs QN13, QN16, QN19, Q
It is supplied to each gate of N22.

In the circuit having such a configuration, for example, when the address signals A0, A1, and A2 are all at "1" level and these inverted address signals are all at "0" level, the N-channel side logic block 12- The three MISFETs QN31, QN32, and QN33 connected in series in 2 all conduct, and the output signal Q8 becomes "0" level. At this time, in the P-channel side logical blocks 11-1 and 11-2,
Since any one of the P-channel MISFETs connected between each output wiring other than the output wiring 14h for obtaining the output signal Q8 and the power supply voltage _VDD is rendered conductive, the remaining output signals Q1 to Q7 are all It becomes “1” level. Thus, the address decode circuit of FIG. 3 operates as an NAND circuit type address decode circuit.

FIG. 4 shows a region surrounded by a dashed line in FIG. 3 when the address decoding circuit of FIG. 3 is actually integrated, that is, the P-channel side logic block 11-2.
FIG. 4 is a pattern plan view showing an element structure of a portion of a logic block 12-2 on the N channel side.

The six input wirings 13a to 13f are made of aluminum, respectively.
Two power wirings 15 and 16 for transmitting the power supply voltage V _DD and the reference voltage V _SS are arranged together on one side of the logic block. In the figure, reference numerals 17a to 17e denote P-type diffusion regions serving as source and drain regions of the P-channel MISFET, respectively. The P-type diffusion region 17a is connected to the power supply wiring 15 via a contact portion 18. Further input wiring
Gate electrodes 20a and 20b made of polysilicon are connected to 13a via respective contact portions 19a and 19b.
The one gate electrode 20a is connected to the P-type diffusion regions 17a and 17a.
b, during which the P-channel M
An ISFET QP40 is formed. Similarly, the other gate electrode 20b extends between the P-type diffusion regions 17a and 17d, and the P-channel MISFE
TQP34 is formed. Hereinafter, similarly, the input wiring 13
b, each gate electrode 20c, 20d made of polysilicon via each contact portion 19c, 19d, and the input wiring 13c, each gate electrode 20e, 20f made of polysilicon via each contact portion 19e, 19f, The input wiring 13d has respective gate electrodes 20g and 20h made of polysilicon through the respective contact portions 19g and 19h, and the input wiring 13e has respective gate electrodes 20i and 20j made of polysilicon through the respective contact portions 19i and 19j. However, the input wiring 13f has
k, each gate electrode 20 made of polysilicon through 19l
k, 20l are connected to each other, and each gate electrode is
Are extended between a pair of corresponding P-type diffusion regions based on the circuit connection state as shown in FIG.

In the drawing, reference numerals 21a to 21n denote N-type diffusion regions serving as source and drain regions of the N-channel MISFET, respectively. The N-type diffusion region 21a is connected to the power supply wiring 16 via a contact portion 22. Further, the input wiring 13a
Are connected to respective gate electrodes 24a and 24b made of polysilicon through respective contact portions 23a and 23b. The one gate electrode 24a extends between the N-type diffusion regions 21a and 21e.
FET QN37 is formed. Similarly, the other gate electrode 24b is extended between the N-type diffusion regions 21a and 211, and the N-channel MISFET is interposed therebetween.
QN31 is formed. Hereinafter, similarly, the input wiring 13
b, the gate electrodes 24c and 24d made of polysilicon via the contact portions 23c and 23d, the input wire 13c has the gate electrode 24e made of polysilicon via the contact portions 23e, and the input wire 13d The gate electrode 24f made of polysilicon is connected to the input wiring via the contact portion 23f.
13f are connected to respective gate electrodes 24g and 24h made of polysilicon via respective contact portions 23g and 23h, and each gate electrode is connected to a corresponding pair of N based on the circuit connection state as shown in FIG. Extending between the mold diffusion regions or between two pairs of N-type diffusion regions.

On the other hand, the output wirings 14a to 14e are formed by using wiring made of aluminum or a combination of wiring made of aluminum and wiring made of polysilicon. These output wirings 14a to 14e are arranged on the opposite side of the logic block from the side on which the two power supply wirings are arranged. For example, the output wiring 14h is formed only of a wiring made of aluminum, and the wiring 14h is connected to the P-type diffusion region 17b through the contact portions 25a and 25b.
And the N-type diffusion region 21n. The output wiring
14g denotes aluminum wirings 26a, 26b each made of aluminum and a polysilicon wiring 27 made of polysilicon connecting both aluminum wirings.
The aluminum wiring 26a is connected to the P-type diffusion region 17c and the N-type diffusion region 21k via the contact portions 25c and 25d. The output wirings 14f are aluminum wirings made of aluminum, respectively.
26c, 26d and a polysilicon wiring 27b made of polysilicon for connecting both aluminum wirings. The aluminum wiring 26c is provided with contact portions 25e, 25f.
Are connected to the P-type diffusion region 17d and the N-type diffusion region 21h through the gate. The output wiring 14e is composed of aluminum wirings 26e and 26f made of aluminum and a polysilicon wiring 27c made of polysilicon for connecting both aluminum wirings. The aluminum wiring 26e is connected via contact portions 25g and 25h. It is connected to the P-type diffusion region 17e and the N-type diffusion region 21d.

As described above, the input wires 13a to 13f for transmitting the address signal are arranged so as to cross the first and second logic blocks, so that the input wires are formed outside the logic block as in the related art. The area occupied on the chip can be reduced by a region necessary for forming these input wirings as compared with the case where the input wiring is formed. Further, unlike the related art, the P-channel MISFET connected in parallel and the N-channel MISFET connected in series do not necessarily need to be provided adjacent to each other, so that the pattern layout is simplified, and the area occupied on the chip also on the layout. Can be reduced. Further, it is not necessary to use a jumper wiring in the logic block in order to extract an output signal in each partial decoding circuit, and as a result, the area occupied by each partial decoding circuit can be reduced.

FIG. 5 is a characteristic diagram comparing the area occupied on the chip in the conventional address decode circuit and that in the address decode circuit of the present invention. Comparing the area of the conventional address decode circuit with that of the present invention, the address decode circuit of the present invention can be reduced to about half of the conventional area. This relationship is maintained even if the number of bits of the address signal increases.

Note that the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications are possible. For example, although the case where the address signal has 3 bits has been described in the circuit of FIG. 3, it goes without saying that the present invention can be naturally applied to those having 3 bits or less.

[0026]

As described above, according to the present invention, it is possible to provide an address decode circuit capable of reducing the area occupied on a chip.

[Brief description of the drawings]

FIG. 1 is a block diagram of an address decoding circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of one partial decode circuit of the address decode circuit according to the embodiment.

FIG. 3 is a circuit diagram showing an entire configuration of the address decoding circuit according to the embodiment when an address signal has 3 bits.

FIG. 4 is a pattern plan view showing a part of the element structure when the address decode circuit of FIG. 3 is integrated;

FIG. 5 is a characteristic diagram showing a comparison between an area occupied on a chip in a conventional address decode circuit and an address decode circuit according to the present invention;

FIG. 6 is a block diagram of a conventional address decode circuit.

7 is a circuit diagram showing a configuration of one partial decode circuit of the conventional address decode circuit shown in FIG.

8 is a pattern plan view showing a partial element structure of the partial decode circuit shown in FIG. 7;

[Explanation of symbols]

11, 11-1, 11-2: P-channel side logic block, 12, 12-1, 12-2: N-channel side logic block, 13, 13a to 13f: address input wiring, 14, 14a to 14h: output wiring 15, 16 ... power supply wiring, 17a-17e ... P-type diffusion region, 18, 19a-19l, 22, 23a-23h ... contact portion, 20a-20l, 24a-24h ... gate electrode, 21a-21n ... N-type diffusion Area, QP1, QP2, QP11 to QP22, QP31 to QP42 ... P-channel MISFET, QN1, QN2, QN11 to QN22, QN31 to QN42 ... N-channel MISFET.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-28092 (JP, A) Proceedings of the IEEE 1986, CUSTOM INTEGRATED CIRCUITS CONFERENCE, p. 2-5, "A HIGH PERFORMER NCE, MULTISOURCE, SCALEABLE CMOS CELL L FAMILY" (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/40-11/419

Claims (1)

(57) [Claims] 1. An address decoding circuit comprising a plurality of partial decoding circuits for decoding an address signal, wherein a first channel type MISFET is provided in plurality.
A logic block, a plurality of second channel type MISFETs, a second logic block provided adjacent to the first logic block in a first direction, and a first logic block and a second logic block. MICHs of the first channel type and the second channel type in the first and second logic blocks are arranged so as to extend transversely in the first direction.
A plurality of address input lines for transmitting the address signal to be supplied to each gate of the SFET, and extending so as to be parallel to the plurality of address input lines.
The power supply voltage and the reference are provided to the first and second logic blocks.
A power supply line for supplying a voltage and the first and second logic blocks from one side of the array;
Arranged so as to be taken out in a second direction crossing the first direction.
And an output wiring for connecting the outputs of the first and second logic blocks.