JP3033299B2 - Drive circuit for solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a solid-state imaging device such as a CCD imager applied to a video camera or the like.

[0002]

2. Description of the Related Art Conventionally, photoelectric conversion elements and charge-coupled elements (C
A so-called CCD imager composed of a CD (Charge Coupled Device) or the like is widely used in video cameras as an imaging means. As this CCD imager, a FIT type CCD (Frame Inte
rline Transfer CCD).

FIG. 7 shows a configuration of the FIT type CCD and its driving circuit. In FIG. 7, reference numeral 1 denotes a FIT type CCD imager, and this imager 1 has light receiving elements corresponding to respective pixels arranged in a matrix. An image section 2, a storage section 3 for temporarily storing signal charges stored in the image section 2, and a horizontal register 4 for transferring the signal charges stored in the storage section 3 for each horizontal line; An image pickup signal is read for each horizontal line from an output circuit (not shown) connected to the output terminal 5 at one end of the horizontal register 4.

The FIT type CCD imager 1
The configuration shown in FIG. That is, the oscillation signal output from the voltage controlled oscillator (VCO) 11 is transmitted to the first, second, third, and fourth counters 12, 13,
14 and 15 and the respective counters 12-15
And a signal of the corresponding frequency. The output of the first counter 12 is supplied to a read timing generator 16 to generate a read pulse, and the output of the second counter 13 is supplied to a sweep timing generator 17 to generate a sweep pulse. Is supplied to a frame shift timing generator 18 to generate a frame shift pulse, and the output of the fourth counter 15 is supplied to a line shift timing generator 19 to generate a line shift pulse. In this case, the read pulse, the sweeping pulse, and the frame shift pulse are generated within a vertical blanking period of a video signal to be captured, and the line shift pulse is generated in a horizontal period during the video period of the video signal to be captured. However, the timing of the read pulse and the sweep pulse varies depending on the set shutter speed.

[0005] The sweeping pulse output from the sweeping timing generator 17, the frame shift pulse output from the frame shift timing generator 18, and the line shift pulse output from the line shift timing generator 19 are sent to the synthesizing circuit 20. It is supplied and combined into one output. Then, the combined output pulse and the read pulse output by the read timing generator 16 are supplied to the image unit driver 21. The line shift pulse output from the line shift timing generator 19 is supplied to the storage unit driver 22.

A power supply circuit 23 is connected to each of the drivers 21 and 22, and the power supply circuit 23 generates three types of power supply voltages V _H , V _L and V _T. in this case,
The voltage V _H is a potential corresponding to the high-level signal “1”, the voltage _VL is a potential corresponding to the low-level signal “0”, and the voltage V _T
Is a potential higher than the potential _VH by a predetermined amount. And
The voltage V _H ,
_VL and _VT are supplied. The supply of the power causes the image section driver 21 to generate an image section drive pulse shown in FIG. That is, the voltage VH changes from the voltage _VH to the voltage _VL at the generation timing of the pulse supplied from the synthesizing circuit 20 to the image unit driver 21, and the generation timing of the read pulse supplied from the timing generator 16 to the image unit driver 21. to produce a driving pulse which varies from the voltage V _H to the voltage V _T. In FIG. 8, the sweep pulse is denoted by P ₁ , the read pulse is denoted by P ₂ , the frame shift pulse is denoted by P ₃ , and the line shift pulse is denoted by P ₄ .

[0007] Then, the image section driving pulse is supplied to CC.
It is supplied to the image unit 2 of the D imager 1. The supply to the image portion 2 of the driving pulses shown in A of FIG. 8, at the image portion 2 in the vertical blanking interval, is first sweep supply pulse P _1, the signal charge sweep accumulated for each pixel after discarded, is supplied reading pulse P ₂ after a predetermined corresponding to the shutter speed time is read out to the vertical transfer registers in the image portion 2, further followed frameshift pulse P ₃ and is the read is supplied signals The charges are transferred to the storage unit 3. Then, in the video period, the line shift pulse P ₄ is continuously supplied with the horizontal period. Supply to the image portion 2 of the line shift pulse P ₄ is not intended for shifting some signal directly, it is for improving the imaging properties as described below.

The storage section driver 22 is supplied with the voltages V _H and V _L from the power supply circuit 23 to generate a storage section drive pulse shown in FIG. 8B. That is, a drive pulse that changes from the voltage _VH to the voltage _VL at the generation timing of the pulse supplied from the line shift timing generator 19 to the storage unit driver 22 is generated. Then, the storage section drive pulse is transmitted to the CCD imager 1.
Is supplied to the storage unit 3. By supplying the drive pulse to the storage unit 3, the signal charges supplied to the storage unit 3 from the image unit 2 via the vertical transfer register and temporarily accumulated during the vertical blanking period are transferred by one horizontal scanning cycle. Lines are transferred to the horizontal transfer register 4 line by line, output from the output terminal 5 one horizontal line at a horizontal period, and one image pickup signal is output in one field period.

As described above, in the case of the FIT type CCD imager, the signal charges obtained in the image unit 2 are temporarily transferred to the storage unit 3 and accumulated, and then the signal charges are transferred in one horizontal cycle.
A process of outputting from the storage unit 3 for each horizontal line is performed.

[0010]

[SUMMARY OF THE INVENTION Incidentally, when the thus drive the FIT type CCD imager, signal charge accumulated in the image section 2, the supply of the pulse P ₁ sweep from reading by supplying the read pulse P ₂ time to sweep in, nothing does not require operation, it is not necessary to supply the original drive pulse, the line shift pulse P ₄ horizontal period shown in a of FIG. 8 in order to improve the imaging characteristics Supplied.

That is, if the period from reading to sweeping is fixed to a high level instead of supplying the line shift pulse P ₄ , the dark current generated from the surface level of the buried channel forming the vertical transfer register will be described. There is a drawback that the number increases. Also, the line shift pulse P ₄
If the period from reading to sweeping out is fixed to a low level instead of supplying the signal, it is impossible to deplete the area under the sensor section composed of the light receiving element, and the smear source directly enters the vertical transfer register, The inconvenience of smearing occurs. Further, the line shift pulse P
_If , instead of supplying ₄ , the low level and the high level are alternately set for each vertical transfer register during the period from reading to sweeping, the signal amount will be biased by the sensor and flicker will occur. There was a problem that occurs. Therefore, by supplying the pulse such as line shift pulses P _4, allowing no good imaging of these adverse effects.

On the other hand, CCD imagers tend to have a large number of pixels in recent years. In particular, CCD imagers that capture high-resolution video signals such as high-definition video signals have a much larger number of pixels than those used in the normal NTSC system. Are arranged. In order to read out the signals of many pixels in a short time,
The transfer clock frequency must be very high. In this case, it is necessary not only to simply increase the frequency but also to increase (and not deteriorate) the transfer efficiency so that the rising and falling edges of the clock waveform are steep and the amplitude is increased.

As described above, a pulse having a high frequency, a steep rise, and a high amplitude requires a large amount of instantaneous current and power, and has a disadvantage of large power consumption.

[0014] Here, as a line shift pulse P ₄ which such power is high transfer clock was directly above and is supplied to the image portion in time to sweep from reading, to be consumed that much wasteful power However, if the level is fixed to the high level or the low level as described above, various inconveniences occur, and the imaging characteristics deteriorate.

In view of the foregoing, it is an object of the present invention to provide a driving circuit of a solid-state imaging device capable of reducing driving power while maintaining good imaging characteristics.

[0016]

According to the present invention, as shown in FIG. 1, for example, light receiving elements corresponding to respective pixels are arranged in a matrix to accumulate signal charges, and the accumulated signal charges are read out pulses. The image portion 2 is read from the light receiving element to the vertical transfer register and is swept out of the vertical transfer register by the sweeping pulse, and the signal charge read from the image portion 2 by the read pulse is transferred by the frame shift pulse. An FIT type solid-state imaging device including a storage unit 3 for temporarily storing the data, and a line transfer register 4 for transferring and outputting the signal charges stored in the storage unit 3 line by line in accordance with a line shift pulse having a predetermined frequency. A sweep pulse, a read pulse, and a frame shift pulse are sequentially transmitted to the device during the vertical blanking period. In the drive circuit of the solid-state imaging device which supplies a line shift pulse during a video period from the sweep pulse to the readout pulse during the video period, a signal having a frequency lower than the frequency of the line shift pulse (a The signal divided by the frequency divider 24 is supplied to the vertical transfer register of the image unit 2 to transfer the signal from the light receiving element to the vertical transfer register.

According to the present invention, for example, as shown in FIG. 1, light receiving elements corresponding to respective pixels are arranged in a matrix to accumulate signal charges, and the accumulated signal charges are vertically transferred from the light receiving elements by a read pulse. An image portion 2 read out to the register 4 and swept out of the vertical transfer register 4 to the outside by a sweeping pulse, and a signal charge read out from the image portion 2 by a reading pulse is transferred by a frame shift pulse and temporarily stored. To a FIT type solid-state imaging device having a storage unit 3 for performing transfer and a line transfer register 4 for transferring and outputting the signal charges stored in the storage unit 3 line by line in accordance with a line shift pulse of a predetermined frequency. Sweep by supplying sweep pulse, read pulse, and frame shift pulse in order during blanking period And between the pulses to the read pulse and the electronic shutter, the drive circuit of the solid-state imaging device for supplying line shift pulse to the video period, during video period, the line shift pulse voltage level lower than the (potential V _H1) A signal (potential V _H2 ) is supplied to the vertical transfer register of the image section 2 to transfer the signal from the light receiving element to the vertical transfer register.

[0018]

In the period from when the charge accumulated by the supply of the read pulse is read to when it is swept by the supply of the sweep pulse,
Since a signal having a lower frequency than the line shift pulse is supplied to the image unit 2, the power of the signal supplied to the image unit 2 can be reduced accordingly.

Further, a signal having a lower level than the line shift pulse is supplied to the image section 2 during a period from the time when the electric charge accumulated by the supply of the read pulse is read to the time when the electric charge is swept by the supply of the sweep pulse. The power of the signal supplied to the image unit 2 can be reduced accordingly.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

In this embodiment, the present invention is applied to a FIT type CCD imager, and portions corresponding to those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the present embodiment, as shown in FIG. 1, the line shift pulse output from the line shift timing generator 19 is supplied to the storage section driver 22 for line shift, and the 1 / n frequency divider is used. 24. In this 1 / n frequency divider 24, the line shift pulse is frequency-divided by a predetermined factor. The division ratio in this case is, for example, 1 / in the case of an imager for the NTSC system.
3 and 1/6 in the case of a high-definition imager
And In the following description, it is assumed that the frequency division ratio is set to 1/3. The pulse divided by the divider 24 is supplied to the synthesizing circuit 20. Then, in the synthesizing circuit 20, the sweeping pulse output by the sweeping-out timing generator 17, the frame shift pulse output by the frame shift timing generator 18, and the pulse output by the frequency divider 24 are output as one system. Combine. Then, the combined output of one system is supplied to the image section driver 21 together with the read timing pulse, and the image section driver 21 generates an image section drive pulse based on each supplied pulse. The driving pulse is supplied to the image section 2 of the CCD imager 1.

In this case, the image part drive pulse (pulse generated during the video period) generated based on the pulse divided by the frequency divider 24 is used to sharpen the rise and fall of the waveform. No processing is performed. In addition, the storage unit driver 22 applies various processes to the storage unit drive pulse generated based on the line shift pulse, such as sharpening the rising and falling edges of the waveform, so that high-speed transfer can be performed well. Apply as needed.

The other parts are the same as those shown in FIG.
The configuration is the same as that of the above circuit.

FIG. 2 shows the driving pulses supplied to the CCD imager 1 in the configuration of FIG.
2 is a drive pulse for the image section, B in FIG. 2 is a drive pulse for the storage section, and the drive pulse for the storage section is generated based on the line shift pulse output from the line shift timing generator 19, and is shown in FIG. This is the same as the drive pulse of the conventional example.

The image section drive pulse includes a sweep pulse P ₁ , a read pulse P _2, and a frame shift pulse P ₃ generated during a vertical blanking period,
A pulse Pa having a cycle corresponding to a pulse obtained by dividing the line shift pulse by ３ during the video period is generated. In this case, the pulse Pa, like the pulse P ₁ and a frame shift pulse P ₃ sweeping, is formed by a change between the potential V _H and the potential V _L. That is, in the video period, the pulse Pa
Is generated, a drive pulse that temporarily drops from the potential _VH to the potential _VL is generated. The storage section drive pulse shown in FIG. 2B is a pulse having a frequency three times that of the pulse Pa.

As described above, the pulse Pa is supplied to the image section 2 during a period from the time when the electric charge accumulated by the supply of the read pulse is read to the time when the electric charge is swept by the supply of the sweep pulse, whereby the dark current and the smear source are supplied. , Flicker and the like can be prevented. Since the pulse Pa is a pulse having a lower frequency than the storage section drive pulse based on the line shift pulse, the power of the pulse Pa can be reduced, and the wasteful power consumption in the imager drive circuit is correspondingly reduced. Can be reduced.

Here, the condition for determining the power P of the pulse Pa is shown by the following equation.

[0029]

[Equation 1] P∝CV * Vf

## EQU1 ## Here, CV is an amplitude and Vf is a frequency. Therefore, for example, by reducing the frequency to 1/3,
The power of the pulse Pa can be reduced to 1/3.

In addition to simply reducing the frequency, the pulse waveform itself does not require processing (such as steepening of the rising edge of the waveform) for increasing the transfer efficiency like the storage section driving pulse, and this is wasteful. Power consumption can be reduced.

The frequency dividing ratio for dividing the line shift pulse by the frequency divider 24 is preferably set to be the largest in a state where the generation of dark current can be prevented. For example, in the case of an NTSC imager, the dividing ratio is 1/3. By circulating, a pulse having an almost lowest frequency that can prevent generation of dark current is obtained. In the case of a high-vision imager, by dividing the frequency by 1/6, a pulse having an almost lowest frequency that can prevent generation of dark current can be obtained.

Next, a second embodiment of the present invention will be described with reference to FIGS. This second embodiment is also applied to a FIT type CCD imager, and FIG.
Are denoted by the same reference numerals, and the detailed description thereof will be omitted.

In this embodiment, as shown in FIG. 3, the line shift pulse output from the line shift timing generator 19 is supplied to the storage section driver 22 and the line shift pulse is directly supplied to the synthesizing circuit 20. I do. Then, the synthesizing circuit 20 synthesizes the sweeping pulse, the frame shift pulse, and the line shift pulse into one system output. Then, the combined output of one system is supplied to the image section driver 21 together with the read timing pulse, and the image section driver 21 generates an image section drive pulse based on each supplied pulse. Drive pulse is C
It is supplied to the image section 2 of the CD imager 1.

In this case, in this example, four types of power supply voltages V _H1 , V _H2 , V _L , and V _T are created by the power supply circuit 23 that supplies power to the image section driver 21. here,
The voltage V _H1 is a potential corresponding to the high level signal “1”, the voltage V _H2 is a potential corresponding to about １ ／ of the high level signal “1”, the voltage _VL is a potential corresponding to the low level signal “0”,
The voltage _VT is a potential higher by a predetermined amount than the potential _VH1 .
The voltage V _H1 and the voltage V _H2 are connected to the power switch 2
5 to be selectively supplied to the image section driver 21. That is, the voltage V _H1 output from the power supply circuit 23 is supplied to the first fixed contact 25a of the changeover switch 25, and the voltage V _H2 is supplied to the second fixed contact 25b of the changeover switch 25. The changeover switch 25
The voltage (V _H1 or V _H2 ) obtained at the movable contact 25m of
It is supplied to the image unit driver 21.

The switching of the movable contact 25m is performed in conjunction with the switching between the video period of the video signal obtained by imaging and the vertical blanking period. That is, during the vertical blanking period, the movable contact 25m is connected to the first fixed contact 25.
The movable contact 25m is connected to the second fixed contact 25b during the video period. Therefore, A in FIG.
As shown in (1), the image part drive pulse Pb generated in the image period by the image part driver 21 is a pulse that temporarily drops from the potential V _H2 to the potential _VL at the generation timing of the line shift pulse. The image section drive pulse generated during the vertical blanking period changes from the potential V _H1 to the potential _VL at the generation timing of the sweeping pulse P ₁ and the frame shift pulse P ₃ , and the timing section 16 transmits the image section driver. The potential V _H1 changes to the potential V _T at the generation timing of the read pulse P ₂ supplied to 21. In addition, as shown in FIG. 4B, the storage unit drive pulse generated by the storage unit driver 22 generates the potential V when the line shift pulse is generated.
_The pulse temporarily drops from _H1 to the potential _VL .

[0037] Incidentally, the shutter speed is set to the imager 1, when the timing pulse P ₁ is supplied sweep is other than the vertical blanking period, is required to change the switching timing of the movable contact 25m of the power changeover switch 25 is there.

Other parts are the same as those shown in FIG.
The configuration is the same as that of the above circuit.

With this configuration, the pulse Pb is supplied to the image section 2 during a period from the time when the electric charge accumulated by the supply of the read pulse is read to the time when the electric charge is swept by the supply of the sweep pulse, whereby the dark current is reduced. , Smear sauce,
It is possible to prevent the occurrence of flicker and the like. And
Since the pulse Pb is a pulse having a lower level than the storage section driving pulse based on the line shift pulse, the power of the pulse Pb can be reduced,
As a result, unnecessary power consumption for driving the imager can be reduced. That is, since the condition for determining the power P of the pulse Pb is determined by the above-mentioned equation (1), the level is reduced from the potential V _H1 to the potential V _H2 so as to be １ ／ or less, so that the pulse Pb
Can be reduced to 以下 or less. For example, by reducing a pulse having an amplitude of 9 to 10 V by 4 to 5 V,
The power can be reduced to about 1/4.

When the pulse level is reduced as in the second embodiment, the potential V _H2 on the high level side of the pulse Pb is set to the lowest level that can prevent the occurrence of smear and flicker. Is most preferred.

In this embodiment, the power is reduced by lowering the level of the pulse Pb. However, instead of lowering the level, the duty ratio of the pulse is changed (for example, 50% when the high level period is equal to the low level period). The power may be reduced by supplying a sine wave instead of a pulse.

In the second embodiment as well, processing for increasing the transfer efficiency is not required for the pulse Pb as in the case of the storage section drive pulse, and wasteful power consumption can be reduced from this point as well.

Next, a third embodiment of the present invention will be described with reference to FIGS. The third embodiment is also applied to a FIT type CCD imager, and is shown in FIG.
Are denoted by the same reference numerals, and the detailed description thereof will be omitted.

In this example, as shown in FIG. 5, the line shift pulse output from the line shift timing generator 19 is supplied to the storage section driver 22 to perform the line shift, and the 1 / n frequency divider is used. 24. In this 1 / n frequency divider 24, the line shift pulse is frequency-divided by a predetermined factor. The setting conditions of the frequency division ratio in this case are the same as in the case of the first embodiment described above. The pulse divided by the frequency divider 24 is output to the synthesizing circuit 2.
Supply 0. Then, in the synthesizing circuit 20, the sweep pulse output by the sweep timing generator 17, the frame shift pulse output by the frame shift timing generator 18, and the pulse output by the frequency divider 24 are set to 1
Combine with the output of the system. Then, the combined output of one system is supplied to the image section driver 21 together with the read timing pulse, and the image section driver 21 generates an image section drive pulse based on each of the supplied pulses.

Then, power is supplied to the image driver 21.
The power supply circuit 23 supplies four types of power supply voltages V_H1,
V_H2, V_L, V_TIs created. Here, the voltage V_H1Ha
Potential V corresponding to the level signal “1”, voltage V_H2Is Haile
The potential, the voltage V, corresponding to about の of the bell signal “1”_LIs
The potential V corresponding to the low level signal “0”, the voltage V_TIs the potential
V _H1The potential is higher than the potential by a predetermined amount. And the voltage V
_H1And voltage V_H2Is selected via the power switch 25
To the image driver 21
You. That is, the voltage V output by the power supply circuit 23_H1Switch
To the first fixed contact 25a of the switch 25,
Pressure V_H2To the second fixed contact 25b of the changeover switch 25.
Pay. The movable contact 25 of the changeover switch 25
m (V_H1Or V_H2), The image part Dora
To the iva 21.

The switching of the movable contact 25m is imaged.
Period and vertical blanking period of the video signal obtained by
It is performed in conjunction with the switching between the modes. That is, the vertical blanking period
Between the movable contact 25m and the first fixed contact 25a.
And during the video period, the movable contact 25m is
2 fixed contact 25b. Therefore, in FIG.
As shown in FIG.
The image portion drive pulse Pc to be generated is
The potential V_H2From the potential V _LTemporarily
This results in a pulse that gradually decreases. In this case, in this example
The line shift pulse divided by the divider 24 is the image part
Since it is supplied to the driver 21, the same as in the first embodiment,
The frequency of the pulse Pc is a fraction of the line shift pulse
(For example, 1/3).

The image section driving pulse generated during the vertical blanking period changes from the potential V _H1 to the potential _VL at the timing of generation of the sweeping pulse P ₁ and the frame shift pulse P ₃ , and the timing generator 16 Read pulse P ₂ supplied to image section driver 21
It changes from potential V _H1 to the potential V _T at the generation timing.
The storage unit drive pulse generated by the storage unit driver 22 is a pulse that temporarily drops from the potential _VH1 to the potential _VL at the generation timing of the line shift pulse, as shown in FIG. 6B.

The other parts are the same as those shown in FIG.
The configuration is the same as that of the above circuit.

With this configuration, the pulse Pc is supplied to the image section 2 during a period from the time when the electric charge accumulated by the supply of the read pulse is read to the time when the electric charge is swept out by the supply of the sweep pulse, whereby the dark current is reduced. , Smear sauce,
It is possible to prevent the occurrence of flicker and the like. And
Since the pulse Pc is a pulse having a lower level and frequency than the storage section drive pulse based on the line shift pulse, the power of the pulse Pb can be reduced, thereby reducing unnecessary power consumption for driving the imager. it can. That is, since the condition for determining the power P of the pulse Pc is determined by the above-mentioned equation (1), for example, the frequency divider 2
Assuming that the frequency division ratio at 4 is 1/3, the power decreases to 1/3 due to the decrease in frequency, and to about 1/4 when the level decreases, and the power of the pulse Pc is reduced to about 1 /
It can be reduced to 12. When the frequency division ratio of the frequency divider 24 is 1/6, the power of the pulse Pc is reduced to about 1
/ 24.

It should be noted that the pulse P in the case of the third embodiment
The conditions for determining the frequency of c are the same as those in the first embodiment, and the conditions for determining the level of the pulse Pc are as follows:
This is the same as the second embodiment described above. In this case, as described in the second embodiment, instead of lowering the level of the pulse Pc, a pulse having a different duty ratio or a sine wave can be used.

[0051]

According to the present invention, a signal having a frequency lower than that of the line shift pulse is supplied to the image portion during a period from the time when the charge accumulated by the supply of the read pulse is read to the time when the charge is swept by the supply of the sweep pulse. Accordingly, the power of the signal supplied to the image unit can be reduced accordingly, and the driving power of the imager can be reduced without deteriorating the imaging characteristics at all.

Also, a signal having a lower level than the line shift pulse is supplied to the image section during a period from the time when the electric charge accumulated by the supply of the read pulse is read to the time when the electric charge is swept by the supply of the sweep pulse. Accordingly, the power of the signal supplied to the image unit can be reduced, and the driving power of the imager can be reduced without deteriorating the imaging characteristics at all.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining a first embodiment;

FIG. 3 is a configuration diagram showing a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining a second embodiment;

FIG. 5 is a configuration diagram showing a third embodiment of the present invention.

FIG. 6 is a timing chart for explaining a third embodiment;

FIG. 7 is a configuration diagram showing a conventional example.

FIG. 8 is a timing chart for explaining a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CCD imager 2 Image part 3 Storage part 4 Horizontal register 11 Voltage control oscillator 19 Line shift timing generator 21 Image part driver 22 Storage part driver 23 Power supply circuit 25 Power supply switch

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/30-5/335

Claims (2)

(57) [Claims] 1. A light receiving element corresponding to each pixel is arranged in a matrix to accumulate signal charges, and the accumulated signal charges are transferred from the light receiving element to a vertical transfer register by a read pulse.
The vertical transfer level is read out by the
An image portion swept out of the register to the outside; a storage portion in which signal charges read out from the image portion by the readout pulse are transferred by a frame shift pulse and temporarily stored; and a signal charge stored in the storage portion is stored. FIT type solid shooting with a line transfer registers to output the transferred line by line in accordance with the line shift pulse of a predetermined frequency
To the imaging device,
Pulse, the read pulse, and the frame shift pulse in this order.
To the above readout pulse to the above readout pulse.
Is an electronic shutter, and the line shift is performed during the video period.
In the driving circuit of the solid-state imaging device for supplying the scan pulse, a signal having a frequency lower than the frequency of the line shift pulse is transmitted to the vertical transfer register of the image section during the video period.
The vertical rotation from the light receiving element
A driving circuit for a solid-state imaging device, wherein the driving circuit transfers the data to a transfer register . 2. A light receiving element corresponding to each pixel is arranged in a matrix to accumulate signal charges, and the accumulated signal charges are transferred from the light receiving element to a vertical transfer register by a read pulse.
The vertical transfer level is read out by the
An image portion swept away from the register to the outside, a storage portion in which signal charges read out from the image portion by the read pulse are transferred by a frame shift pulse and temporarily stored, and a signal charge stored in the storage portion is stored. FIT type solid shooting with a line transfer registers to output the transferred line by line in accordance with the line shift pulse of a predetermined frequency
To the imaging device during the vertical blanking period.
Pulse, the read pulse, and the frame shift pulse in this order.
To the above readout pulse to the above readout pulse.
Is an electronic shutter, and the line shift is performed during the video period.
In the driving circuit of the solid-state imaging device for supplying a scan pulse, a signal having a level lower than the voltage of the line shift pulse is supplied to the vertical transfer register of the image section during the video period.
The vertical rotation from the light receiving element
A driving circuit for a solid-state imaging device, wherein the driving circuit transfers the data to a transfer register .