JP3034657B2 - Package for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for semiconductor devices, and more particularly to a PGA (Pin Grid Array) type package suitable for large-scale semiconductor devices. In recent years, the number of package leads has tended to increase further with the increase in the scale of semiconductor integrated circuits. In this regard, a PGA type package in which many leads protrude from the lower surface of the package is preferable.

A PGA type package is roughly classified into a ceramic type and a plastic type. The former uses a ceramic plate for a substrate on which a semiconductor element is mounted, and the latter uses a glass epoxy laminated plate (see FIG. 3). Although the plastic PGA type package has the advantage of being cheaper than the ceramic PGA type package, it is pointed out that the plastic PGA type package is inferior in heat dissipation. Therefore, a PGA type package that satisfies both low cost and heat dissipation is required.

[0003]

2. Description of the Related Art FIG. 4 is a structural view of a conventional PGA type package excellent in heat dissipation. In the figure, reference numeral 10 denotes a substrate, and a metal 11 such as copper is used for a core material (core) of the substrate 10. This metal 11 has an insulating resin 12 around it.
And a plurality of holes 11 for mounting leads 13
a, 11b and recess 1 for accommodating semiconductor element 14
5 are formed. 16 is a circuit pattern, 17
Is a bonding wire, and 18 is a cap. Since the bottom surface of the semiconductor element 14 is fixed to the metal 11, the heat resistance is reduced and the heat dissipation is improved.

[0004]

However, in such a conventional package for a semiconductor device, the lead 13 is not provided.
The same number of holes must be formed in the metal 11, and the number of leads 13 becomes extremely large depending on the scale of the mounted semiconductor element.

Accordingly, an object of the present invention is to provide a semiconductor package which does not require drilling holes in metal, reduces processing costs, and has excellent heat dissipation.

[0006]

Means for Solving the Problems The present invention, in order to achieve the above object, a semiconductor device package including a first metal substrate, a semiconductor element on the lower surface of the substrate
A second metal having an opening larger than the
Then, when a recess for mounting the semiconductor element is formed,
Both the lower surface side of the substrate, wherein the semiconductor element, a circuit pattern to be electrically connected to form the land to be connected to the circuit pattern, terminals for external connection to said lands to be mounted on the recess Are provided and joined.

[0007]

According to the present invention, it suffices to merely join the lead by abutting the land on the land on the lower surface side of the substrate, and it is not necessary to form a hole in the metal, thereby reducing the processing cost. Further, a so-called cavity-down structure can be obtained by mounting a semiconductor element on the lower surface of the substrate, and a heat radiation effect can be further improved by attaching a heat sink or the like to the upper surface of the substrate.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The outline of the present invention will be described below with reference to the drawings. Figure 1 is a <br/> view showing a package for a semiconductor device according to the present invention. In FIG. 1A, reference numeral 20 denotes a substrate. A metal 21 made of copper or a copper alloy is used for a core material (core) of the substrate 20.
A recess 21a for mounting the semiconductor element 22 is formed. On the lower surface side, a wiring pattern 24 and an n integrated with the wiring pattern 24 are provided via an insulating resin 23.
The number of lands 25 (n is the total number of leads 26) is formed. Here, the planar shape of the land 25 is substantially circular as shown in FIG.
Greater than the width of. A lead 26 is attached to each land 25. In this mounting method, the head of the lead 26 is brought into contact with the land 25, and the two are joined by soldering. 28 is a solder resist, 2
9 is a bonding wire and 30 is a cap.

According to such a configuration, a land 25 integral with the wiring pattern 24 is formed on the lower surface side of the substrate 20, and the lead 26 is abutted on the land 25 to be joined.
The hole processing for the metal (metal plate) 21 is not required, and the processing cost can be reduced. Moreover, since a semiconductor element is mounted 2 2 on the lower surface of the substrate 20, shown in claim 2
As shown in FIG. 1, a so-called cavity-down structure can be used. By attaching a heat radiating plate to the upper surface of the substrate 20, the heat radiation effect can be further improved.

FIG. 2 is a view showing an embodiment of a semiconductor device package according to the present invention. In FIG. 2, reference numeral 30 denotes a substrate. The core material of the substrate 30 is made of a metal (hereinafter, referred to as a first metal) 3 made of copper or a copper alloy as described in the outline.
1 is provided on the lower surface side of the first metal 31 via a second insulating resin 32 made of copper or copper alloy.
Metal 33 is attached. An opening 33a larger than the size of the semiconductor element 34 is formed in the second metal 33, and the insulating resin 32 applied inside the opening 33a is removed except for the inner peripheral wall of the opening 33a.
Thereby, a concave portion 35 for accommodating the semiconductor element 34 is formed. Insulating resin 3 around the second metal 33
2 and a wiring pattern 36 on the lower surface of the second metal 33 in contact with the insulating resin 32 and on the side wall of the concave portion 35.
Are formed in series. The lands 37 (37a, 37b...) Are integrally connected to the wiring pattern 36, and the lands 37 are provided in the same number as the leads 38 (38a, 38b...). The planar shape of the land 37 is substantially circular as in the first embodiment, and the diameter thereof is larger than the width of the wiring pattern 36 (see FIG. 1B). The head of a lead 38 is abutted on each land 37 and joined by solder 39.

Here, one lead (for example, 38a)
The land 37a and the first metal 31 are electrically connected to each other via a wiring pattern.
The land 37b joined to one lead (for example, 38b) and the second metal 33 are electrically connected via a wiring pattern. For example, the wiring pattern extending to the side wall of the concave portion 35 is connected to the first metal 31 and the wiring pattern is connected to the land 37a, and a concave portion reaching the second metal 33 is formed in the wiring pattern 36. Then, conduction between the second metal 33 and the wiring pattern 36 may be established by plating.

This eliminates the need for drilling holes in the first metal 31 and the second metal 33, thereby reducing the processing cost as in the first embodiment. Further, since the first metal 31 can be used as a ground line and the second metal 33 can be used as a power supply line, there is a specific effect that the wiring density on the lower surface of the substrate can be increased.

In general, in a cavity-down PGA type package, a large number of wiring patterns are present on the lower surface of the substrate. When lands for hitting leads are further formed, the land diameter is larger than the width of the wiring patterns. Therefore, the wiring area of the portion sandwiched between the lands is pressed. For this reason, the number of wirings between lands must be reduced, and the merit as a PGA type package suitable for multi-pin may be lost.

In this embodiment, since the first metal 31 and the second metal 33 can be assigned to a ground line and a power line, respectively, it is not necessary to form a power line pattern on the lower surface of the substrate. As a result, the wiring density of the signal line can be increased.

[0015]

According to the present invention, it is possible to eliminate the need for drilling holes in metal, to reduce the processing cost, and to provide a PGA type package excellent in heat dissipation.

[Brief description of the drawings]

FIG. 1 is a structural view schematically showing the present invention .

FIG. 2 is a structural diagram of an embodiment of the present invention .

FIG. 3 is a structural view of a conventional plastic PGA type package.

FIG. 4 shows a conventional plastic PGA using a metal core.
It is a structure diagram of a mold package.

[Explanation of symbols]

 20: Substrate 21: Metal 22: Semiconductor element 24: Circuit pattern 26: Lead 25: Land

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 23/12

Claims (3)

(57) [Claims] In a semiconductor device package using a first metal for a substrate, a semiconductor element is formed on a lower surface of the substrate .
A second metal having a larger opening is provided and
Along with forming a recess in which the semiconductor element is mounted,
A circuit pattern electrically connected to the semiconductor element mounted in the concave portion and a land connected to the circuit pattern are formed on the lower surface of the substrate, and the land is externally connected.
A package for a semiconductor device, wherein a connection terminal is provided and joined. 2. The method according to claim 1, wherein the second metal is provided on a lower surface side of the substrate.
The number of leads erected as terminals for parts connected to the
Connect the first metal and the second metal to a ground line and
The package for a semiconductor device according to claim 1 , wherein the package is used as a source line . 3. The external dimensions of the first metal and the external dimensions of the second metal.
2. The method according to claim 1, wherein the external dimensions are substantially equal.
Package of the semiconductor device.