JP3036196B2 - Communication device with fault tolerance - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication apparatus having fault tolerance, and is used, for example, in a multiplex transmission system for performing digital communication in balanced communication.

[0002]

2. Description of the Related Art Conventionally, in a data communication system, various devices have been devised to improve the reliability of communication. In some cases, the communication device has the ability to correctly perform all or a part of predetermined functions as seen from the outside without causing a system shutdown.

One example of this is a balanced communication device that uses at least two transmission lines.
Even if one transmission line is fixed at an arbitrary potential (including zero potential) (fail) for some reason,
If even the other transmission line operates normally, it is possible to obtain received data, although the noise resistance performance, which is a merit of balanced communication, is impaired.

However, it is not preferable to leave the communication apparatus unattended even though the communication apparatus is in an abnormal state. Therefore, it is determined which transmission line has failed, and a countermeasure against some abnormality (for example, using To the person)
Need to be applied.

As an example of such a failure detecting circuit, there is a circuit as shown in FIG.
3826774A1). In the circuit shown in FIG. 7, the count counter 24 periodically counts up the count value, and the count value is reset by a demodulated signal from the comparator 20.
4 and a central processing unit (hereinafter referred to as a CPU) 25 for detecting a failure of the negative signal line 1 or the positive signal line 2.

In other words, according to the circuit shown in FIG. 7, when the negative signal line 1 and the positive signal line 2 are normal, a demodulated signal is output from the comparator 20 and the count value of the counter 24 is reset. However, when either the negative signal line 1 or the positive signal line 2 fails, the counter 20 continues to count up because no demodulated signal is output from the comparator 20.

When the count value reaches a predetermined value,
The count counter 24 outputs an error signal to the CPU 25,
The CPU 25 turns on the analog switch 21 via the status register 26. Then, a specified voltage of V _CC / 2 (V) is supplied to the positive signal line 2 through the voltage follower 23 and is input to the positive input terminal of the comparator 20. As a result, when demodulation is performed by the comparator 20, the count value of the count counter 24 is reset, so that the CPU 25 can detect that the positive signal line 2 has failed.

However, when the demodulation by the comparator 20 is not performed, the counting counter 24 continues counting up again, and when the count value reaches a predetermined value, the counting counter 24 outputs an error signal to the CPU 25 again. Next, the CPU 25 turns on the analog switch 22 via the status register 26. Then, a specified voltage of V _cc / 2 is supplied to the negative signal line 1 through the voltage follower 23, and is input to the negative input terminal of the comparator 20.

At this time, when demodulation is performed by the comparator 20, the count counter 24 is reset, so that the CPU 25 can detect that the negative signal line 1 has failed.

[0010]

However, in the conventional detection circuit described above, when the fail determination of the negative signal line 1 and the positive signal line 2 is to be performed, the CPU 25 controls the analog switches 22 and 22 to switch. In this case, the failure determination by the counter 24 and the CPU 25 must be performed twice in chronological order, which causes a problem that the time required for the failure determination becomes longer.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a communication apparatus which can perform demodulation using a balanced transmission line even if any of the transmission lines fails, requires a time required for a failure determination. It is an object of the present invention to provide a communication device provided with a fault tolerance capable of reducing an error.

[0012]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a balanced transmission line comprising first and second transmission lines for transmitting first and second communication signals having different polarities, and the balanced transmission line. And a transmission device for transmitting the first and second communication signals via the first and second communication signals via the balanced transmission line.
A communication device having a receiving device for receiving the communication signal of the second type and a failure determination circuit for determining whether or not the balanced transmission line has failed, wherein the failure determination circuit performs the second communication based on the first communication signal. Monitoring the transmission line of
The monitoring state is reset by the second communication signal, and it is determined whether or not the second transmission line has failed based on whether or not the monitoring state of the second transmission line has reached a predetermined period. First determining means for monitoring the first transmission line based on the second communication signal, resetting the monitoring state based on the first communication signal, and determining whether the first transmission line has failed; And a second determining means for determining whether the monitoring state of the first transmission line has reached a predetermined period or not, employing a communication device having fault tolerance. is there.

[0013]

With the above arrangement, in the first determining means, the monitoring state of the second transmission line by the first communication signal is reset by the second communication signal, so that, for example, when the second transmission line fails. The monitoring state of the second transmission line is continued without being reset, and when this monitoring state reaches a predetermined period, it is determined that the second transmission line has failed.

Similarly, in the second determining means, the monitoring state of the first transmission line by the second communication signal is reset by the first communication signal. For example, when the first transmission line fails, The monitoring state of the first transmission line is continued without being reset, and when this monitoring state reaches a predetermined period, it is determined that the first transmission line has failed.

Therefore, it is possible to determine whether or not the second transmission line has failed by the first determining means, and determine whether or not the first transmission line has failed by the second determining means. In addition, the failure determination of the first transmission line and the failure determination of the second transmission line can be performed in parallel.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to an embodiment shown in the drawings. In this embodiment, a case where the present invention is applied to a communication driver / receiver will be described. FIG. 1 is a configuration diagram showing a schematic configuration of a communication driver / receiver according to one embodiment of the present invention.

In FIG. 1, a driver 100 for transmitting data, which corresponds to a transmitting device, is configured as described below. That is, the input buffer IC 101 for inputting a signal from the transmission input terminal 106 outputs the output signal to the positive driver amplifying section 102 and the logical inverter IC 10.
Output to 2.

The positive driver amplifying section 102, which has received a signal from the input buffer IC 101 through a terminal 102a, transmits a control signal from a fail determination circuit 104, which will be described later, to a terminal 1a.
02c, the gain is switched according to the control signal, and the input signal is amplified and output from the terminal 102b.

The NPN transistor TR101 has a base side and a terminal 102b of the positive driver amplifying section 102.
Is connected, and a signal from the positive electrode driver amplifying unit 102 is transmitted through a positive electrode output terminal 113 by an emitter follower.
The signal is output to the positive signal line 2 corresponding to the second transmission line.

[0020] Incidentally, this on the emitter side of the transistor is connected to a protective resistor resistor R101, the collector-side voltage V _CC (eg, 5V) the transistor TR
The power supply voltage to be supplied to 101 is connected. further,
A pull-down resistor R103 having one end connected between the resistor R101 and the positive signal line 2 and the other end grounded is provided to secure a reference potential (GND) of the positive signal line 2.

The logic inverter IC102 to which the signal from the input buffer IC101 is inputted inverts the logic of the inputted communication signal and outputs it. Logical inverter IC102
The negative driver amplifying section 103 which has input a signal from the terminal 103a (that is, a signal having a logic opposite to that of the output signal from the input buffer IC 101) from a terminal 103a inputs a control signal from a fail determination circuit 104 to be described later from a terminal 103c. The gain is switched according to the control signal, and the input signal is amplified and output from the terminal 103b.

The PNP transistor TR102 is connected to the base side of the transistor TR102 and the terminal 103b of the negative electrode driver amplifier 103.
And outputs the signal from the negative electrode driver amplifier 103 to the negative signal line 1 corresponding to the first transmission line via the negative signal output terminal 114 by the emitter follower.

[0023] Note that has resistor R102 serving as the protection resistor to the emitter side of the transistor is connected, to the collector side when the power supply voltage supplying voltage V _CC to the transistor TR102 is connected. Furthermore, one end has a resistor R10
A pull-up resistor R104, which is connected between the second signal line 2 and the negative signal line 1 and has the other end connected to the power supply, is provided to supply a current to the negative signal line 1.

Subsequently, a receiver 101 for receiving data, which corresponds to a receiving apparatus, is configured as described below. Capacitor C101 and capacitor C102
Are provided on the transmission line 3 connected to the negative input terminal and the transmission line 4 connected to the positive input terminal of the demodulator IC 101, and connect the negative signal line 1 and the positive signal line 2 via the terminals 109 and 110. AC coupling.

The offset adjustment circuit 105 is a circuit for adding a DC component to the communication signal from which the DC component has been removed by the capacitors C101 and C102.
In 5, the communication signal to which the DC component is added is input from the positive input terminal and the negative input terminal and demodulated, and the demodulated signal is output to the reception output terminal 107.

The fail determination circuit 104 is provided with a demodulator I
It is determined whether or not the transmission line 3 and the transmission line 4 connected to C103 are in a fail state, and according to the determination result, the positive driver amplifier 102 and the negative driver amplifier 103 via the terminals 111 and 112, respectively. And the judgment result is output to the failure output terminal 10.
8 is output.

Next, a specific circuit configuration of the fail determination circuit 104 and the offset adjustment circuit 105 of the receiver 101 will be described with reference to FIG. In FIG.
The offset adjustment circuit 105 includes voltage clamp circuits 203 and 204 described below.

The voltage clamp circuit 203 is connected to the transmission line 3, and a circuit in which a resistor R204 and a resistor R205 are connected in series and a circuit in which a resistor R206 and a PNP transistor TR202 are connected in series are connected in parallel. , One end of which is connected to the power supply voltage V _CC and the other end is grounded.

The divided voltage of the resistors R204 and R205 is applied to the base of the transistor TR202, and the emitter of the transistor TR202 is connected to the transmission line 3.

On the other hand, the voltage clamp circuit 204 is connected to the transmission line 4 and includes a resistor R202 and a resistor R201.
Are connected in series, and an NPN transistor TR
A circuit in which a resistor 201 and a resistor R203 are connected in series is connected in parallel, one end of which is connected to the power supply voltage V _CC and the other end is grounded.

The divided voltage of the resistor R202 and the resistor R201 is applied to the base of the transistor TR201, and the emitter of the transistor TR201 is connected to the transmission line 4.

The transmission input terminal 10 of the driver 100
6 is given a communication signal of logic “0”, and the driver 10
When 0 is in the communication stop state, the DC component added to the transmission line 3 or the transmission line 4 of the receiver 101 is based on the voltage of the positive input terminal of the demodulator IC 103 based on the divided voltage of the resistors R201 and R202. −Specified voltage V _OS ⁺ which is lower by the emitter-to-emitter voltage, and the voltage at the negative input terminal is based on the divided voltage of the resistors R203 and R204.
Only emitter voltage of high specified voltage V _OS ^- is.

The failure determination circuit 104 is configured as described below. That is, the buffer IC 201
The positive input terminal of the buffer IC 202 is connected to the transmission line 4, the threshold voltage V _th1 is input to the negative input terminal, and the threshold voltage V th is input to the positive input terminal of the buffer IC 202.
_{While th2} is input, the negative input terminal is connected to the transmission line 3. Then, the buffer IC 201 and the buffer IC 202 convert the level of the communication signal on the transmission line into an amplitude suitable for the internal circuit of the fail determination circuit 104.

The counter 201 counts up at the rising edge of the output signal from the buffer IC 201 input via the CK terminal (clock terminal), and performs CLR.
Buffer IC2 input via terminal (reset terminal)
When the falling edge of the output signal from 02 coincides with the predetermined number m, the counter is cleared.

If the count value matches a predetermined value n (where n> m), the negative signal line 1
, The CRY terminal is activated (logic '0'), and the gain of the positive electrode driver amplifying section 102 is switched from G1 to G2, which will be described later.

Similarly, the counter 202 counts up at the rising edge of the output signal from the buffer IC 202 input via the CK terminal, and counts up at the falling edge of the output signal from the buffer IC 201 input via the CLR terminal. Clear the counter. Then, when the count value matches the predetermined value, it is determined that a failure of the positive electrode signal line 2 has been detected, and the gain of the negative electrode driver amplifier 103 is switched from G1 to G2 described later by the CRY terminal. The clearing of the counter by the CLR terminal may be performed by level detection. Further, the buffer IC 201 and the counter 202 correspond to a first determination unit, and the buffer IC 202 and the counter 201 correspond to a second determination unit.

The gate IC 203 calculates the logical sum of the CRY terminals of the counter 201 and the counter 202 and indicates via the fail output terminal 108 that a failure has been detected on either the negative signal line 1 or the positive signal line 2. The user is notified by a device or the like.

Next, a specific circuit configuration of the negative electrode driver amplifier 103 will be described with reference to FIG. The positive electrode driver amplifying section 102 has the same circuit configuration as that shown in FIG.

[0039] In FIG. 3, the negative input terminal of the comparator IC301 is connected to the terminal 103a, the resistor in the positive input terminal connected to a power supply voltage V _CC R301 and R3
02 is applied. This comparator IC3
Reference numeral 01 is provided for adjusting the logic inverted by the inverting amplifier IC 302 at the next stage and for setting the output level of the comparator IC 301 to be the input of the inverting amplifier IC 302.

[0040] The positive input terminal of the inverting amplifier IC302 is connected to the power supply voltage V _CC resistors R306 and R307
The divided voltage is applied to the negative input terminal.
c (a failure determination circuit 10)
4), the resistor 304 and the resistor 305 are selectively connected by the analog switch SW301 which is turned on / off in response to the signal. The output side of the inverting amplifier IC 302 is connected to the terminal 103b.

Here, the gain of the inverting amplifier IC 302 is switched by turning on / off the analog switch SW301 as described above. For example, when the control signal from the fail determination circuit 104 is a signal of logic “1”, the analog switch SW301 is turned on,
Conversely, when the control signal is a signal of logic '0', the analog switch SW301 is turned off.

Then, when the analog switch SW301 is on, the gain G1 is

[0043]

(Equation 1) Becomes

On the other hand, when the analog switch SW301 is off, the gain G2 is

[0045]

## EQU2 ## G2 = R304 / R303. Thus, the gain of the inverting amplifier IC 302 can be increased by turning off the analog switch SW301.

The switching of the gain of the inverting amplifier IC 302 is performed in response to the control signal from the fail determination unit 104 as described above.
If no failure is detected in any of the positive and negative signal lines 2, the analog switch SW301 is turned on to have the gain G1, and if a failure is detected in either the negative signal line 1 or the positive signal line 2, the analog switch SW301 is turned on.
301 is turned off and becomes the gain G2. The method of detecting a failure will be described later.

[0047] Then, the voltage (offset voltage) V _o applied to the positive input terminal of the inverting amplifier IC302 is by a resistor R306 and the resistor R307, the comparator I
Because it is set to an intermediate value of the output voltage range of the C 301, the relationship between the input voltage V _in and the output voltage V _out of _the negative electrode driver amplifier 103 when the analog switch SW301 is turned on is expressed by the following formula . However, the input voltage V _in is the voltage of the signal input from the terminal 103a, the output voltage V
_out is the voltage of the signal output from the terminal 103b.

[0048]

(Equation 3) On the other hand, the input voltage V _in and the output voltage V of the negative electrode driver amplifier 103 when the analog switch SW301 is off
The relationship with _out is represented by the following equation.

[0049]

Equation 4] _{V out = -G2 × (V in} ─V O) + V O = - (R304 / R303) × (V in ─V O) + V O will now be described the operation in the above configuration.

First, the operation of the driver 100 will be described with reference to FIGS.
This will be described with reference to FIG. In FIG. 1 to FIG.
A digital signal represented by logic “0” or logic “1” is supplied to the transmission input terminal 106 of “0”. The communication signal of logic "0" is represented by a zero potential, and the communication signal of logic "1" is represented by a predetermined potential (for example, 5 V). When no signal is applied, the communication signal is represented by logic "0".

The digital signal input through the transmission input terminal 106 passes through the input buffer IC 101, and then is input to the terminal 102a of the positive driver amplifying section 102, and the logic is inverted by the logical inverter IC 102 and the negative driver is used. The signal is input to the terminal 103a of the amplifier 103. In addition,
The potential of the signal output from the buffer IC 101 (logical inverter IC102 as well), zero potential in the communication signal of the logic "0", the V _CC potential communication signal of logic '1'.

The digital signal input to the negative driver amplifying section 103 is amplified by the gain G1 or G2 according to the on / off state of the analog switch SW301.
The signal is output to the base side of the transistor TR102. Then, since the transistor TR102 is used as an emitter follower, the output voltage _Vout of the negative electrode driver amplifying unit 103 is applied to the transistor TR102 from the emitter side of the transistor.
The signal obtained by adding the base-emitter voltage V _BE of 102 is
The signal is output to the negative signal line 1 via the resistor R102 and the negative signal output terminal 114. However, this operation is logic '1'
For the communication signal of logic '0', since the potential is zero potential, the transistor TR102 is turned off and no communication signal is output.

Similarly, the digital signal input to the positive driver amplifying section 102 is output to the base of the transistor TR101. Then, since the transistor TR101 is used as an emitter follower, the output voltage V
A signal obtained by subtracting the base-emitter voltage V _BE of the transistor TR101 from _out is output to the positive signal line 2 via the resistor R101 and the positive output terminal 113. This operation also has the logic “1” as in the case of the negative electrode driver amplifier 103.
No communication signal is output for a communication signal of logic '0'.

Accordingly, the level of the communication signal on the positive signal line 2 is set by the divided voltage of the resistors R101 and R103, and the level of the communication signal on the negative signal line 1 is
It is set by the divided voltage of the resistor 102 and the resistor R104.

Next, the operation of the receiver 101 will be described with reference to FIGS. 1 and 2, the receiver 101 is connected via the negative input terminal 114 and the terminal 110.
The communication signal on the transmission line 3 input to the receiver 101 and the communication signal on the transmission line 4 input to the receiver 101 via the positive input terminal 113 and the terminal 109 are connected to the capacitor C10.
1. Offset adjustment circuit 1 via capacitor C102
05 is input.

[0056] Then the offset adjustment circuit 105, the specified voltage V _OS ^+, V _OS ^- in clamps the communication signals of each transmission line, is input to the fail decision circuit 104 and a demodulator IC 103.

In the fail determination circuit 104, the transmission line 3
And whether the transmission line 3 (negative signal line 1) or the transmission line 4 (positive signal line 2) has failed based on the communication signal input from the transmission line 4, and outputs the result of the determination as a failure. The signal is output to the outside via a terminal 108, and the positive driver amplifier 102 and the negative driver amplifier 103 via terminals 111 and 112.
The gain of FIG. 3 is changed. The detailed operation of the fail determination circuit 104 will be described later.

The demodulator IC 103 compares the respective communication signals input to the positive input terminal and the negative input terminal, and
The comparison result is output to the reception output terminal 107. next,
The operation related to the failure detection performed by the receiver 101 will be described.

First, the operation relating to the failure detection when both the negative signal line 1 and the positive signal line 2 are normal is shown in FIG.
This will be described with reference to the time chart of FIG.
When both the negative signal line 1 and the positive signal line 2 are normal, the communication signal appears on the negative signal line 1 and the positive signal line 2 as waveforms of opposite polarities. When this communication signal passes through capacitors C101 and C102, it is output to fail determination circuit 104 and demodulator IC103.

In the fail determination circuit 104, the transmission line 4
The upper communication signal is the threshold voltage V _th1 set by the buffer IC 201, and the communication signal on the transmission line 3 is the buffer I
The value is compared with the threshold voltage V _th2 set by C 202 and output to the counter 201 and the counter 202.

Here, in the buffer IC 202, logical inversion is performed to unify the logic of the output of the buffer IC 201 and the output of the buffer IC 202. For example, the driver 100
When the logic of the input signal to the transistor changes from “0” to “1”, the transistors TR101 and TR10
2 is switched from the off state to the on state, and the buffer IC 2
01, the output logic of the buffer IC 202 also changes from '0' to '1'. Conversely, when the logic of the input signal to the driver 100 changes from “1” to “0”, the output logic of the buffer ICs 201 and 202 also changes from “1” to “0”.

The input signal to the driver 100 is logic '0'
, The driver 100 is in a communication pause state,
As shown in FIG. 4, after transmitting one message, the signal always returns to the logical "0" signal. That is, buffer I
When viewed from the output waveforms of C201 and the buffer IC 202,
When the logic changes from '0' to '1' (a rising edge from zero potential to V _CC potential), the logic always changes from '1' to '0' (from V _CC potential to zero potential). Falling edge) always exists.

Therefore, for example, when detecting a failure state of the positive signal line 2, the output of the buffer IC 202 in which the communication signal on the negative signal line 1 is inverted is supplied to the CK terminal which is a trigger terminal for counting up of the counter 202. A buffer IC buffering a communication signal on the positive signal line 2 is provided at a CLR terminal which is a trigger terminal for count clear.
The output of 201 is given.

Then, the negative signal line 1 and the positive signal line 2
Are normal, one fall of the output signal of the buffer IC 201 always occurs once for each rise of the output signal of the buffer IC 202. Therefore, in the counter 202, the count value is cleared every predetermined number m described above, so that the count value of the counter 202 is counted up only to "m" smaller than the predetermined value n, and the output signal of the CRY terminal is also a logical signal Keep maintaining 1 '. In addition, the negative electrode driver amplifying unit 10
3 does not output a control signal to the analog switch S.
W301 is off, and the negative electrode driver amplifying unit 103
Remains at G1.

The operation of the counter 201 for detecting a failure of the negative signal line 1 is the same as that of the counter 202 described above, and a description thereof will be omitted. Next, the operation related to the failure detection when either the negative signal line 1 or the positive signal line 2 is abnormal will be described with reference to the time chart of FIG. 5 and FIGS. Here, the operation when the negative signal line 1 is short-circuited to zero potential will be described.

When the negative signal line 1 is fixed (failed) to zero potential as shown in FIG. 5, the output voltage of the buffer IC 202 for comparing the communication signal on the negative signal line 1 with the threshold voltage V _th2 is As shown in the waveform of the CLR terminal of the counter 201 or the waveform of the CK terminal of the counter 202, after a short time elapses after failing to zero potential, the logic "1" is inverted from "1" to "0". The logic "0" is held until the failure is released.

Here, the negative signal line 1 fails to zero potential, and immediately the CLR terminal waveform of the counter 201 or the CK terminal waveform of the counter 202 changes from logic “1” to “0”.
Not inverted to, the potential of the communication signal on the negative signal line 1, though the negative signal line 1 is reduced to the zero potential moment that fail to zero potential, resistance until exceeding the threshold voltage V _th2 R206 and This is because the time set by the time constant of the capacitor C101 is required, and thus it takes time until the logic is inverted.

In the meantime, the communication signal on the positive signal line 2 in the normal state passes through the buffer IC 201 and passes through the buffer IC.
The output of the counter 201 is input to the CK terminal of the counter 201 and the CLR terminal of the counter 202. At this time, the output of the buffer IC 202 is given to the CLR terminal of the counter 201, and the negative signal line 1 remains fixed at logic '0' due to the fail state. Therefore, in the counter 201, since the falling edge does not exist in the input signal of the CLR terminal, the count value is not cleared.
The rising edge of the CK terminal is caught and counting is continued, and this count value is set to a predetermined value n (FIG. 5).
, The CRY terminal is switched from logic '1' to '0' when n = 4) is reached. The counter 20
In the case of 2, the CK terminal is fixed at logic '0', so that the count-up is not performed, and the CRY terminal keeps holding logic '1'.

The output signal from the CRY terminal of the counter 201 is ANDed by the gate element IC 203,
The ND output is output to the outside via the fail output terminal 108 to notify the one-sided abnormality of the communication signal line.

On the other hand, the output signal from the CRY terminal of the counter 201 is also output as a control signal to the analog switch SW301 of the negative driver amplifier 103 of the driver 100 via the terminal 112, and the gain of the negative driver amplifier 103 is output. From G1 to G2. The point at which the gain of the amplifier section of the driver is switched from G1 to G2 when a failure occurs will be described later.

Thereafter, when the negative signal line 1 is released from the zero potential short circuit and returns to the normal state, a communication signal appears on the negative signal line 1 and the output signal of the buffer IC 202 also appears as shown in FIG. Then, in the counter 201, the falling of the output signal of the buffer IC 201 is performed a predetermined number of times m.
When (m = 2 in FIG. 5) is reached, the count value is cleared, whereby the output of the CRY terminal is also inverted from logic “0” to “1”.

Then, the output of the gate element IC 203 is also inverted from logic “0” to “1” to notify that the communication signal line has been released from failure, and to make the driver 100
The gain of the negative electrode driver amplifier 103 is also switched from G2 to G1.

When the positive signal line 2 fails, the counter 201 operates in the same manner as the counter 202 to notify that one side of the communication progress line has failed and to switch the gain of the positive driver amplifier 102. .

As described above, in the fail determination circuit according to the present embodiment, the communication signals (digital signals demodulated by a predetermined threshold voltage value) of the negative signal line 1 and the positive signal line 2 are converted to the CK terminals of the two counters and the CLR. Since the signals are input to the terminals, respectively, and the failure detection of the negative signal line 1 and the positive signal line 2 is performed in parallel, the time required for the failure determination can be minimized.

When the communication device is, for example, a vehicle-mounted communication device, a large current flowing through a lamp or the like easily causes a difference in zero potential between the ECUs (electronic control devices). Compared with the conventional method in which the fail determination is performed based on the potential of the communication signal on the line, the conventional method is different in that the failure determination is performed using a communication signal which is clamped by the offset adjustment circuit 105 and is irrelevant to the fluctuation of the zero potential. It is possible to perform a fail determination with higher reliability than the method.

In the above-mentioned operation, the predetermined value n of the rising edge of the CK terminal is 2 and the predetermined number m of the falling edge of the CRY terminal is 4, but these values are changed depending on the circuit configuration inside the counter. It can be changed arbitrarily.

Next, the reason why the gain of the driver amplifier of the driver 100 is switched from G1 to G2 when a failure is detected will be described with reference to FIG. FIG. 6 shows input signal waveforms at the transmission input terminal 106 of the driver 100, input signal waveforms at the positive and negative input terminals of the demodulator IC 103 of the receiver 101, and output signal waveforms at the reception output terminal 107 of the receiver 101. FIG. It should be noted that in this waveform diagram, the driver 100 does not fail even after the failure as shown in the above embodiment.
Is not switched.

In FIG. 6, the region is a waveform diagram when both the negative signal line 1 and the positive signal line 2 are normal.
The communication signal (positive communication signal) on the positive signal line 2 is the voltage V _OS
The communication signal (negative electrode communication signal) on the negative signal line 1 is shifted based on the voltage V _OS ^- from the reference point ⁺ . The noise margin when the input signal waveform of the transmission input terminal 106 of the driver 100 is logic “1” is V _NM1 .

The region is a waveform diagram showing a situation where the positive signal line 2 has failed. The potential of the positive input terminal of the demodulator IC 103 is fixed at the voltage V _OS ⁺ , and only the communication signal on the negative signal line 1 is in the region. It has been shaken similarly. In the state shown in the area, the negative communication signal crosses the voltage V _OS ⁺ , which is the potential of the positive communication signal, so that the demodulated signal appears at the reception output terminal 107 of the receiver 101. However, the noise margin at the time of the input signal waveform of the transmission input terminal 106 of the driver 100 is a logic '1' will become apparent from the V _NM1 less _{V NM2 (V NM1> V NM2} ).

However, if the communication device is, for example, a communication device mounted on a vehicle, a large current flowing through a lamp or the like tends to cause a difference in zero potential between the ECUs. For this reason, if a difference occurs in the zero potential between the ECUs mounted with the communication device when the positive signal line 2 fails, the amplitude of the communication signal is suppressed to be lower than when there is no difference in the zero potential. Therefore, as shown in the area, since the amplitude of the communication signal on the negative signal line 1 is insufficient, the signal cannot cross the voltage V _OS ⁺ , which is the potential of the positive communication signal, and the demodulator IC
There is a problem that demodulation cannot be performed at 103.

Therefore, in the above embodiment, when a failure of one of the signal lines is detected by the failure determination circuit 104, the gain of the driver amplifier of the driver 100 is switched from G1 to G2 to increase the amplification. As a result, the amplitude of the communication signal output from the driver 100 is increased, and even if a difference occurs in the zero potential between the ECUs equipped with the communication device, the voltage crosses the voltage of the failed signal line accurately and demodulates. I can do it.

As described above, in the communication apparatus having the fault tolerance, as a countermeasure to be taken by detecting that one of the transmission lines has failed, the user is notified that there is a failed transmission line as described above. In addition to the countermeasure, there is also a countermeasure that the amplitude of the transmission signal is increased by switching the gain of the driver amplifying section to accurately demodulate the received data.

As described above, the communication driver / receiver according to the above-described embodiment alternately monitors the edges of the respective communication signals on the negative signal line 1 and the positive signal line 2 so that each conventional signal line is monitored. Compared to the method in which the voltage level is determined to be within the specified value every time, it is possible to accurately determine the failure while having a simple circuit configuration.

When a failure is detected, by increasing the gain of the communication signal by increasing the gain of the driver on the signal line side that operates normally, the zero potential between each ECU equipped with the communication driver / receiver can be reduced. Even if a difference occurs and the amplitude of the communication waveform is suppressed, normal demodulation can be guaranteed.

Further, the negative signal line 1 and the positive signal line 2
By performing fail detection using each of the above communication signals, a highly versatile communication device can be configured.
That is, in the circuit shown in FIG. 7 described in the related art, the count value of the counter 24 that counts at a constant speed is reset by the demodulated signal from the comparator 20, so that the network system method and the access cycle are different for each mounted device. If they are different, the predetermined value of the count value which is the basis of the abnormality determination must be changed, and there is a problem that the versatility is poor. However, by using each communication signal on the negative signal line 1 and the positive signal line 2 as in the above embodiment, a highly versatile communication device compatible with a communication system can be provided.

Next, another embodiment will be described. In the above-described embodiment, as a countermeasure against abnormalities performed by detecting that one of the transmission lines has failed, a countermeasure for notifying the user that there is a failed transmission line, a driver amplification to accurately demodulate received data, and the like. has been exemplified measures that increase the amplitude of the transmission signal by switching the gain of the parts, ⁺ specified voltage V _OS of the voltage clamp circuit 203 clamps, V _OS ^- is switched to the event of a failure detection, failure has been detected The signal level of the received signal on the transmission line may be switched. That is, as shown in FIG.
The voltage clamp circuits 403 and 404 include the counter 20
The switches SW401 and SW40 are used to change the signal level of the received signal on the transmission line based on the determination results from the first and second 202.
2 is provided, and when the counters 201 and 202 detect a failure in the transmission line to be detected, the terminal 11
1 and 112, a signal indicating failure detection is output to the switches SW401 and SW402, and the switch SW4
01, SW 402 is closed, whereby the signal level of the received signal of the failed transmission line is changed (reduced).

The circuit configuration of the voltage clamp circuits 403 and 404 is the same as that of the voltage clamp circuit 20 of the above-described embodiment.
3, 204, a PNP transistor TR402 and an NPN transistor T forming a temperature compensation circuit.
R401, PNP transistor TR403 and NP
N-type transistor TR404 (PNP type and N-type
Both transistors of the PN type have a complementary relationship), and are configured to be able to perform accurate demodulation by accurately clamping even when the use environment temperature changes.

Next, the operation in the above configuration will be described. FIG. 9 shows the operation of the fail judgment circuit and the demodulator IC 10 when the negative signal line fails in another embodiment.
6 is a timing chart showing an input state to No. 3;

8 and 9, when the transmission line 3 (negative signal line 1) and the transmission line 4 (positive signal line 2) are both normal, the communication signal on the positive signal line 2 (positive communication signal) ) And the communication signal (negative electrode communication signal) on the negative signal line 1 are respectively applied based on the voltages Va and Vb.

If for some reason the transmission line 3 (negative signal line 1) fails to zero potential over the region, the voltage clamp circuit 403 fixes the input signal waveform at the negative input terminal of the demodulator IC 103 to the voltage Va. Is done. Note that in the area and the area described later, the capacitor C is not used for a predetermined time after the transmission line 3 fails or after the failure is released.
Voltage Va immediately due to the influence of the resistor 101 and the resistor R406.
It does not become.

Then, counting is performed at the rising edge of the output signal from the buffer IC 201 input via the CK terminal, and the counter is cleared at the falling edge of the output signal from the buffer IC 202 input via the CLR terminal. In the counter 201, the count value is reset immediately after the communication signal on the transmission line 3 becomes the post-failure voltage Va. However, when the communication signal on the transmission line 3 is fixed at the voltage Va, the counter 201 counts without being reset. Keep up.

The count value is equal to a predetermined value (4 in FIG. 9).
Counter), the counter 201 determines that a failure has been detected, notifies the outside via the fail output terminal 108 of a one-sided abnormality of the communication signal line, and activates the CRY terminal (signal indicating failure detection) to switch SW.
402 is closed (corresponding to a region in FIG. 9). As a result, the communication signal on the transmission line 3 fixed to the voltage Va becomes a voltage slightly lower than the voltage Va (preferably, an intermediate voltage of the voltage amplitude of the communication signal on the transmission line 4 that normally operates), and the demodulator IC 103 And crosses the input signal waveform at the positive input terminal.

Thereafter, if the failed transmission line 3 (negative signal line 1) returns to a normal state (corresponding to the area) for some reason, the counter 201 sets
When the number of falling edges of the input signal to the LR terminal reaches a predetermined number of times (two times in FIG. 9), the count value is cleared, the failure is released, and the communication signal line is returned to the normal state via the failure output terminal 108 to the outside. At the same time, the CRY terminal is set to a passive state (a signal indicating that the fail is released), and the switch SW402 is opened (corresponding to a region in FIG. 9).

As described above, in the other embodiment, by changing the specified voltage to be clamped by the voltage clamp circuit in accordance with the result of the failure detection, accurate demodulation can be performed even when one of the transmission lines fails. It is possible to do.

That is, the receiver 101 has the fault tolerance by the voltage clamp circuit that can demodulate even when one of the transmission lines fails, but depending on the failed potential, as shown in FIG. In some cases, the waveform of the communication signal on the transmission line does not intersect with the waveform of the communication signal on the normal transmission line. May intersect at different locations.

In the latter case, although the signal is demodulated, the signal width of the demodulated signal is slightly different from the normal signal, so that an inaccurate portion may occur. However, as in the other embodiments described above, By changing the specified voltage to be clamped by the voltage clamp circuit according to the result of the failure detection, the waveform of the communication signal on the failed transmission line crosses in the middle of the amplitude of the waveform of the communication signal on the normally operating transmission line. By doing so, more accurate demodulation can be performed.

[0097]

As described above, according to the present invention, the failure judgment of the first transmission line and the failure judgment of the second transmission line can be performed in parallel, so that the communication signal is received and the first judgment is made. The failure determination of the transmission line and the second transmission line is performed in parallel, and there is an excellent effect that the time required for failure determination can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a detailed configuration of a fail determination circuit and an offset adjustment circuit in the embodiment.

FIG. 3 is a circuit diagram illustrating a detailed configuration of a negative electrode driver amplifying unit in the embodiment.

FIG. 4 is a timing chart showing the operation of the fail determination circuit when both the positive signal line and the negative signal line are normal in the embodiment.

FIG. 5 is a timing chart showing the operation of the fail determination circuit when the negative signal line fails in the embodiment.

FIG. 6 is a signal waveform diagram for explaining gain switching of a receiver performed when a failure is detected in the embodiment.

FIG. 7 is a block diagram illustrating a configuration of a fail determination circuit according to the related art.

FIG. 8 is a circuit diagram illustrating a detailed configuration of a fail determination circuit and an offset adjustment circuit according to another embodiment of the present invention.

FIG. 9 shows the operation of the fail determination circuit and the demodulator IC1 when the negative signal line fails in the other embodiment.
6 is a timing chart showing an input state to the input unit 03.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Negative signal line 2 Positive signal line 100 Driver 101 Receiver 104 Failure judgment circuit 201, 202 Counter

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-108243 (JP, A) JP-A-3-41842 (JP, A) JP-A-4-70234 (JP, A) JP-A-3- 41841 (JP, A) JP-A-5-300155 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/40

Claims (3)

(57) [Claims] 1. A balanced transmission line comprising first and second transmission lines for transmitting first and second communication signals having different polarities, and said first and second transmission lines via said balanced transmission line. A transmission device that transmits the communication signal of the above, a reception device that receives the first and second communication signals via the balanced transmission line, and a failure that determines whether the balanced transmission line has failed. In the communication device having a determination circuit, the failure determination circuit monitors the second transmission line with the first communication signal, resets the monitoring state with the second communication signal, and resets the second communication line. A first determination unit that determines whether or not the transmission line has failed based on whether or not the monitoring state of the second transmission line has reached a predetermined period; and Monitoring a transmission line, the first communication signal; A second determining means for resetting the monitoring state by a signal and determining whether or not the first transmission line has failed based on whether or not the monitoring state of the first transmission line has reached a predetermined period. A communication device having fault tolerance, comprising: 2. The method according to claim 1, wherein the first determination unit counts the number of occurrences of the first communication signal on the first transmission line, and counts the number of occurrences of the first communication signal based on the second communication signal on the second transmission line. A first counting means for resetting the count value and outputting a signal for notifying an abnormality of the second transmission line when the count value reaches a predetermined value, the second determination means Counts the second communication signal, resets the count value by the first communication signal, and, when the count value reaches a predetermined value, notifies an abnormality of the first transmission line. 2. A communication apparatus having a fault tolerance according to claim 1, further comprising: a second counting means for outputting a signal indicating the occurrence of a fault. 3. The first communication signal and the second communication signal each include a combination of data corresponding to data “1” and data “0”. Demodulating means for inputting and demodulating the first communication signal and the second communication signal respectively from the transmission line, a capacitor inserted into the balanced transmission line, and passing through the capacitor from the balanced transmission line. And a voltage clamp circuit that clamps a communication signal input to the demodulation means with a predetermined voltage of a communication signal corresponding to data '0', and the voltage clamp circuit passes through the capacitor. 3. The method according to claim 1, wherein the predetermined voltage for clamping a communication signal input to the demodulation means is changed according to a result of the determination by the fail determination circuit.
A communication device comprising the described fault tolerance.