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JP3036249B2 - Chip mounting structure and test method - Google Patents
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JP3036249B2 - Chip mounting structure and test method - Google Patents

Chip mounting structure and test method

Info

Publication number
JP3036249B2
JP3036249B2 JP4218109A JP21810992A JP3036249B2 JP 3036249 B2 JP3036249 B2 JP 3036249B2 JP 4218109 A JP4218109 A JP 4218109A JP 21810992 A JP21810992 A JP 21810992A JP 3036249 B2 JP3036249 B2 JP 3036249B2
Authority
JP
Japan
Prior art keywords
bare chip
bump
chip
substrate
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4218109A
Other languages
Japanese (ja)
Other versions
JPH0669280A (en
Inventor
敏弘 草谷
和久 ▲角▼井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4218109A priority Critical patent/JP3036249B2/en
Publication of JPH0669280A publication Critical patent/JPH0669280A/en
Application granted granted Critical
Publication of JP3036249B2 publication Critical patent/JP3036249B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07251Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、基板に固着されたベア
チップが必要に応じて、取り外しが行われるように形成
されたベアチップの実装構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of a bare chip formed such that a bare chip fixed to a substrate can be removed as required.

【0002】基板に半導体素子を実装することで電子機
器を形成する場合、通常、半導体素子を高温状態に保持
させるバーインテスト、および、テスト信号の入出力に
よる機能チエックを行うフアンクションテストによる単
体試験が行われ、単体試験によって良品と判定された半
導体素子が所定の基板に実装されることが行われる。
When an electronic device is formed by mounting a semiconductor element on a substrate, a unit test is usually performed by a burn-in test for holding the semiconductor element at a high temperature state and a function test for performing a function check by inputting and outputting test signals. Is performed, and the semiconductor element determined to be non-defective by the unit test is mounted on a predetermined substrate.

【0003】一方、このような半導体素子の実装は、高
密度実装化により、近年、ベアチップを基板に直接実装
することが行われるようになった。したがって、このよ
うなベアチップを基板に直接実装する構成では、ベアチ
ップの単体試験が容易に行えるようにすることが必要と
なった。
On the other hand, in mounting such a semiconductor element, a bare chip has recently been directly mounted on a substrate due to high-density mounting. Therefore, in a configuration in which such a bare chip is directly mounted on a substrate, it is necessary to easily perform a unit test of the bare chip.

【0004】[0004]

【従来の技術】従来は図4の従来の説明図に示すように
構成されていた。図4の(a)(b)は側面図である。
2. Description of the Related Art Conventionally, the configuration is as shown in the conventional explanatory diagram of FIG. FIGS. 4A and 4B are side views.

【0005】図4の(a) に示すように、ベアチップ4 の
電極5 にはバンプ10を固着し、ソケット14にベアチップ
4 を装着する場合は、ソケット14に配列されたパッド3
にバンプ10を溶着することで行われていた。
As shown in FIG. 4A, a bump 10 is fixed to an electrode 5 of a bare chip 4 and a bare chip is
4 If you want to install
The welding was performed by welding the bumps 10.

【0006】また、ソケット14は、セラミック材より成
る絶縁部材12の一面12A にコンタクトピン13を配列し、
他面12B にパッド3 を配列し、コンタクトピン13とパッ
ド3との間にはパターン11が接続され、所定のコンタク
トピン13が所定のパッド3 に電気導通を有するように形
成されていた。
In the socket 14, contact pins 13 are arranged on one surface 12A of the insulating member 12 made of a ceramic material.
The pads 3 are arranged on the other surface 12B, the pattern 11 is connected between the contact pins 13 and the pads 3, and the predetermined contact pins 13 are formed so as to have electrical conduction with the predetermined pads 3.

【0007】そこで、ベアチップ4の単体試験を行う場
合は、ソケット14にベアチップ4を装着し、例えば、
コンタクトピン13を所定の試験装置のコネクタに接続
し、コンタクトピン13を介してテスト信号Sの入出力
を行うことで単体試験が行われていた。
Therefore, when performing a unit test of the bare chip 4, the bare chip 4 is attached to the socket 14, and for example,
The contact pins 13 connected to the connector of a given test apparatus, a single test by inputting and outputting test signals S through the contact pin 13 has been performed.

【0008】したがって、単体試験後、ベアチップ4 を
ソケット14から取り外す場合は、図4の(b) に示すよう
に、加熱することでバンプ10を溶融させ、矢印A に示す
ように、ベアチップ4 を剥離させることが必要となる。
Therefore, when the bare chip 4 is removed from the socket 14 after the unit test, the bump 10 is melted by heating as shown in FIG. 4B, and the bare chip 4 is removed as shown by an arrow A. It is necessary to peel it off.

【0009】[0009]

【発明が解決しようとする課題】しかし、パッド3 にバ
ンプ10を溶着させることでベアチップ4 がソケット14に
装着される構成では、ベアチップ4 をソケット14から取
り外す場合は、図4の(b) に示すように、ベアチップ4
を剥離させるよう外力を加えることになり、更に、パッ
ド3 およびベアチップ4 の電極5 には溶融されたバンプ
10が付着することになる。
However, in a configuration in which the bare chip 4 is mounted on the socket 14 by welding the bump 10 to the pad 3, when the bare chip 4 is removed from the socket 14, the state shown in FIG. As shown, bare chip 4
An external force is applied so as to peel off the pad 3 and the electrode 5 of the bare chip 4.
10 will adhere.

【0010】したがって、単体試験後、ベアチップ4 を
ソケット14から取り外す場合、外力を加えること、およ
び、付着したバンプ10を除去することでベアチップ4 を
損傷させる問題を有していた。
Therefore, when the bare chip 4 is removed from the socket 14 after the unit test, there is a problem that the bare chip 4 is damaged by applying an external force and removing the attached bumps 10.

【0011】そこで、本発明では、ベアチップの取り外
しを容易にすることを目的とする。
Accordingly, an object of the present invention is to facilitate removal of a bare chip.

【0012】[0012]

【課題を解決するための手段】図1は本発明の原理説明
図で、図1の(a)(b)の側面図に示すように、電極
5を有するベアチップ4と、バンプ7を介して該電極5
と電気的に接続されるパッド3を有する基板8と、所定
の温度で硬化し該所定の温度より高い温度で軟化する絶
縁層6とを備え、該電極5と該バンプ7間あるいは該バ
ンプ7と該パッド3間のいずれか一方が、非固着状態で
接続されるよう構成する。
Figure 1 [Means for Solving the Problems] In principle illustration of the present invention, as shown in the side view of FIG. 1 (a) (b), the electrode
5 and the electrodes 5 via bumps 7.
A substrate 8 having pads 3 electrically connected to
Hardens at a temperature of above and softens at a temperature higher than the predetermined temperature.
An edge layer 6 between the electrode 5 and the bump 7 or
Either the pump 7 or the pad 3 is in a non-fixed state.
Configure to be connected .

【0013】このように構成することによって前述の課
題は解決される。
The above-mentioned configuration solves the above-mentioned problem.

【0014】[0014]

【作用】即ち、基板8とベアチップ4との間に熱可塑性
の合成樹脂材より成る絶縁層6を形成し、単体試験時に
は、絶縁層6によってベアチップ4を固着させ、単体試
験の終了後は、所定温度に加熱し、絶縁層6を軟化させ
ることで容易にベアチップ4の取外しが行えるように
する共に、ベアチップ4の電極5に密接させるバンプ
7をパッドに固着させるようにしたものである。
In other words, an insulating layer 6 made of a thermoplastic synthetic resin material is formed between the substrate 8 and the bare chip 4, and at the time of the unit test, the bare chip 4 is fixed by the insulating layer 6; heated to a predetermined temperature, when the allow is removed Ri taken easily bare chip 4 by softening the insulating layer 6 together, which was so as to secure the bump 7 to be close contact with the electrodes 5 of the bare chip 4 to pad is there.

【0015】そこで、絶縁層6によってベアチップ4を
固着させ、ソケット8にベアチップ4を装着することで
バンプ7をベアチップ4の電極5に密接させることが行
え、ベアチップ4をソケット8から取り外す場合は、バ
ンプ7がソケット8側に固着された状態で取り外しが行
われるようにすることができる。
[0015] Thus, by fixing the bare chip 4 by an insulating layer 6, the bumps 7 by mounting the bare chip 4 to the socket 8 can be closely electrode 5 of the bare chip 4, out to field takes bare chip 4 from the socket 8 In this case, the removal can be performed with the bump 7 fixed to the socket 8 side.

【0016】したがって、前述のような取り外し際し
て、ベアチップ4に大きな外力が加わること、および、
電極5に付着されたバンプを除去することが不要とな
り、ベアチップ4を損傷させることが避けられ、しか
も、着脱が容易に行え、単体試験に於ける試験工数の削
減を図ることができる。
[0016] Therefore, Te <br/> Saishi removal as described above, to join a large external force to the bare chip 4, and,
It is not necessary to remove the bumps attached to the electrodes 5, and it is possible to avoid damaging the bare chip 4, and furthermore, it is possible to easily perform attachment and detachment, and to reduce the number of test steps in a unit test.

【0017】[0017]

【実施例】以下本発明を図2および図3を参考に詳細に
説明する。図2は本発明による一実施例の説明図で、
(a) は側面図,(b1) 〜(b5)はベアチップの取付, 取外説
明図, 図3は本発明の他の実施例の説明図で、(a) は平
面図,(b)は側面図である。全図を通じて、同一符号は同
一対象物を示す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to FIGS. FIG. 2 is an explanatory diagram of an embodiment according to the present invention.
(a) is a side view, (b1) to (b5) are views for attaching and removing a bare chip, FIG. 3 is an explanatory view of another embodiment of the present invention, (a) is a plan view, and (b) is a plan view. It is a side view. Throughout the drawings, the same reference numerals indicate the same objects.

【0018】図2の(a) に示すように、引出パターン9
に接続されるパッド3 を絶縁部材1に配列することで形
成された基板8 に熱可塑性の合成樹脂材より成る絶縁層
6 を形成することでベアチップ5 の実装が行われ、ベア
チップ5 の電極5 がバンプ7を介してパッド3 に接続さ
れるように形成され、更に、引出パターン9 の一方に形
成された接続パッド2 にはコンタクトピン2Aが接続され
ることで形成されるようにしたものである。
As shown in FIG. 2A, the drawing pattern 9
An insulating layer made of a thermoplastic synthetic resin material is formed on a substrate 8 formed by arranging the pads 3 connected to the
6, the bare chip 5 is mounted, the electrodes 5 of the bare chip 5 are formed so as to be connected to the pads 3 via the bumps 7, and the connection pads 2 formed on one of the lead-out patterns 9 are formed. Are formed by connecting the contact pins 2A.

【0019】また、バンプ7 は熱硬化性のパラジウム系
導電樹脂材によって形成され、パッド3 に固着され、ベ
アチップ4 の電極5 には密接されるように形成されてい
る。このようなベアチップ4 の実装は、図2の(b1)に示
すように、先づ、絶縁部材1 に配列されたバッド3 にマ
スキングによって熱硬化性のパラジウム系導電樹脂材を
塗布し、加熱することでパラジウム系導電樹脂材を硬化
させ、バンプ7 の形成を行い、次に、図2の(b2)に示す
ように、バッド3 が配列された所定面1Aには常温でゲル
状となる熱可塑性の合成樹脂材6-1 を盛りつけ、ベアチ
ップ4 の電極5 をバンプ7 に位置決めすることで矢印B
のように絶縁部材1 にベアチップ4 を押圧させる。
The bumps 7 are formed of a thermosetting palladium-based conductive resin material, are fixed to the pads 3, and are formed so as to be in close contact with the electrodes 5 of the bare chip 4. In mounting such a bare chip 4, as shown in FIG. 2 (b1), a thermosetting palladium-based conductive resin material is applied to the pads 3 arranged on the insulating member 1 by masking and heated. Thus, the palladium-based conductive resin material is cured to form the bumps 7, and then, as shown in FIG. 2 (b2), the predetermined surface 1A, on which the pads 3 are arranged, becomes a gel at room temperature. An arrow B is formed by placing the plastic synthetic resin material 6-1 and positioning the electrode 5 of the bare chip 4 on the bump 7.
The bare chip 4 is pressed against the insulating member 1 as described above.

【0020】このようにベアチップ4 を押圧することで
所定温度T1の加熱、例えば、温度110 〜150 ℃の加熱を
行い、図2の(b3)に示すように、ゲル状の合成樹脂材6-
1 を硬化させ、絶縁層6 を形成し、ベアチップ4 を絶縁
部材1 の所定面1Aに固着させ、同時にバンプ7 が電極5
に密着させるようにベアチップ4 を絶縁部材1 に実装さ
せることができる。
By pressing the bare chip 4 in this manner, heating at a predetermined temperature T1, for example, heating at a temperature of 110 to 150 ° C., is performed, and as shown in FIG.
1 is cured to form an insulating layer 6, and the bare chip 4 is fixed to the predetermined surface 1A of the insulating member 1, and at the same time, the bump 7 is
The bare chip 4 can be mounted on the insulating member 1 so as to be in close contact with.

【0021】そこで、コンタクトピン2Aに所定のテスト
信号S を入出力し、単体試験の終了後は、絶縁部材1 か
らベアチップ4 を取り外しを行う。この場合は、前述の
加熱温度T1より高い温度T2の加熱、例えば、温度150 〜
200 ℃で再度加熱し、図2の(b4)に示すように、絶縁層
6 を軟化させ、図2の(b5)に示すように、ベアチップ4
を矢印A のように剥離させることで取り外しを行うこと
ができる。
Therefore, a predetermined test signal S is input to and output from the contact pin 2A, and after the unit test is completed, the bare chip 4 is removed from the insulating member 1. In this case, heating at a temperature T2 higher than the above-mentioned heating temperature T1, for example, at a temperature of 150 to
Heat again at 200 ° C, and as shown in Fig. 2 (b4),
6 is softened, and as shown in FIG.
Can be removed by peeling off as shown by arrow A.

【0022】この場合、バンプ7はッド3に固着され
ているため、バンプ7と、電極5との間が切り離され
る。したがって、従来ような取り外したベアチップ4の
電極5に溶融したバンプ10が付着することなく、しか
も、取り外しに際して、ベアチップ4に大きな外力を加
えることなく容易にベアチップ4の取り外しを行うこと
ができる。
[0022] In this case, since the bump 7 is secured to the Pas head 3, the bump 7, between the electrodes 5 are separated. Therefore, the bare chip 4 can be easily removed without the molten bump 10 adhering to the electrode 5 of the bare chip 4 which has been removed as in the related art, and without applying a large external force to the bare chip 4 at the time of removal.

【0023】更に、従来では、試験すべきベアチップ4
に対しては必ずバンプ10を形成することが必要であった
が、このようなベアチップ4 にバンプ10を形成する手間
が不要となり、しかも、入手したベアチップ4 を直ちに
試験することが可能となり、試験工数の削減を図ること
ができる。
Furthermore, conventionally, bare chips 4 to be tested
However, it was necessary to form the bumps 10 on the bare chip 4, but the labor for forming the bumps 10 on the bare chip 4 became unnecessary, and the obtained bare chip 4 could be tested immediately. The man-hour can be reduced.

【0024】また、図3の(a)(b)に示す場合は、絶縁部
材1 の所定面1Aにパッド3 と、パッド3 に引出パターン
9 を介して接続される接続パッド2 を設けることで基板
8 を形成し、ベアチップ4 は絶縁層6 を介して基板8 の
所定面1Aに固着させ、ベアチップ4 の電極5 がバンプ7
を介してパッド3 に接続されることでベアチップ4 の実
装を行い、テスト信号S の入出力による試験は、接続パ
ッド2 によって行われるようにしたものである。
In the case shown in FIGS. 3A and 3B, the pad 3 is provided on the predetermined surface 1A of the insulating member 1, and the lead pattern is provided on the pad 3.
9 and the connection pad 2 connected via
The bare chip 4 is fixed to the predetermined surface 1A of the substrate 8 via the insulating layer 6, and the electrodes 5 of the bare chip 4 are
The bare chip 4 is mounted by being connected to the pad 3 through the connection pad, and the test by inputting and outputting the test signal S is performed by the connection pad 2.

【0025】この場合も前述と同様に、絶縁層6 は温度
T1の加熱によって硬化され、温度T2の加熱によって軟化
するように形成され、また、バンプ7 はパッド3 に固着
されるように形成されている。
Also in this case, as described above, the insulating layer 6
The bump 7 is formed so as to be hardened by heating at T1 and softened by heating at temperature T2, and the bump 7 is fixed to the pad 3.

【0026】したがって、基板8 にベアチップ4 を実装
し、所定の単体試験の終了後は、基板8 からベアチップ
4 を取り外すことが容易に行える。
Therefore, after the bare chip 4 is mounted on the substrate 8 and the predetermined unit test is completed, the bare chip 4 is removed from the substrate 8.
4 can be easily removed.

【0027】[0027]

【発明の効果】以上説明したように、本発明によれば、
基板と、ベアチップとの間に熱可塑性の合成樹脂材より
成る絶縁層を形成することでベアチップを固着させ、ベ
アチップを基板から取り外す場合は、絶縁層を軟化させ
ることで容易に取り外しが行うことができ、また、基板
側にバンプを固着させ、ベアチップにバンプを形成する
ことなく、ベアチップの実装を行うことができる。
As described above, according to the present invention,
The bare chip is fixed by forming an insulating layer made of a thermoplastic synthetic resin material between the substrate and the bare chip, and when the bare chip is removed from the substrate, it can be easily removed by softening the insulating layer. Further, the bump can be fixed to the substrate side, and the bare chip can be mounted without forming the bump on the bare chip.

【0028】したがって、従来に比較して、ベアチップ
の実装, 取外が容易となり、試験工数の削減が図れ、し
かも、ベアチップに対する損傷を避けることができ、実
用的効果は大である。
Accordingly, as compared with the conventional case, the mounting and detaching of the bare chip becomes easier, the number of testing steps can be reduced, and the damage to the bare chip can be avoided, so that the practical effect is large.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の原理説明図FIG. 1 is a diagram illustrating the principle of the present invention.

【図2】 本発明による一実施例の説明図FIG. 2 is an explanatory view of an embodiment according to the present invention.

【図3】 本発明の他の実施例の説明図FIG. 3 is an explanatory view of another embodiment of the present invention.

【図4】 従来の説明図FIG. 4 is a conventional explanatory view.

【符号の説明】[Explanation of symbols]

1 絶縁部材 2 接続パッド 3 パッド 4 ベアチップ 5 電極 6 絶縁層 7 バンプ 8 基板 1A 面 DESCRIPTION OF SYMBOLS 1 Insulation member 2 Connection pad 3 Pad 4 Bare chip 5 Electrode 6 Insulating layer 7 Bump 8 Substrate 1A surface

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 電極を有するチップと、 バンプを介して該電極と電気的に接続されるパッドを有
する基板と、 所定の温度で硬化し該所定の温度より高い温度で軟化す
る絶縁層とを備え、 該電極と該バンプ間あるいは該バンプと該パッド間のい
ずれか一方が、非固着状態で接続されていることを特徴
とするチップの実装構造。
1. A chip having electrodes, a substrate having pads electrically connected to the electrodes via bumps, and an insulating layer which is hardened at a predetermined temperature and softened at a temperature higher than the predetermined temperature. A chip mounting structure, wherein one of the electrode and the bump or the bump and the pad is connected in a non-fixed state.
【請求項2】 チップの電極を基板のパッドに接続して
電気的試験を行なう試験方法において、 該パッドと該電極の間を電気的に接続するバンプを形成
する工程と、 該基板に所定温度で硬化する絶縁層を塗布する工程と、 前記所定温度まで加熱することで、該チップを該基板に
対して該電極と該バンプ間あるいは該バンプと該パッド
間のいずれか一方を非固着状態にて搭載する工程と、 該チップの電気試験後に、前記所定温度よりも高い温
度まで加熱し、前記絶縁層を軟化させ、該チップを該基
板から取り外す工程とからなるチップの試験方法。
2. A test method for performing an electrical test by connecting an electrode of a chip to a pad of a substrate, the method comprising: forming a bump electrically connecting the pad and the electrode; Applying an insulating layer that cures at a predetermined temperature, and heating the chip to the predetermined temperature so that the chip is in a non-fixed state between the electrode and the bump or between the bump and the pad with respect to the substrate. a step of mounting Te, after electrical test of the chip, the predetermined temperature and heated to a temperature higher than said softening the insulating layer, a chip testing method comprising the step of removing the chip from the substrate.
JP4218109A 1992-08-18 1992-08-18 Chip mounting structure and test method Expired - Fee Related JP3036249B2 (en)

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Application Number Priority Date Filing Date Title
JP4218109A JP3036249B2 (en) 1992-08-18 1992-08-18 Chip mounting structure and test method

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Application Number Priority Date Filing Date Title
JP4218109A JP3036249B2 (en) 1992-08-18 1992-08-18 Chip mounting structure and test method

Publications (2)

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JPH0669280A JPH0669280A (en) 1994-03-11
JP3036249B2 true JP3036249B2 (en) 2000-04-24

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6316528B1 (en) 1997-01-17 2001-11-13 Loctite (R&D) Limited Thermosetting resin compositions
US6274389B1 (en) 1997-01-17 2001-08-14 Loctite (R&D) Ltd. Mounting structure and mounting process from semiconductor devices
EP1153980B1 (en) 1999-02-18 2003-11-05 Three Bond Co., Ltd. Epoxy resin composition
US20050288458A1 (en) 2002-07-29 2005-12-29 Klemarczyk Philip T Reworkable thermosetting resin composition
US7012120B2 (en) 2000-03-31 2006-03-14 Henkel Corporation Reworkable compositions of oxirane(s) or thirane(s)-containing resin and curing agent
US7108920B1 (en) 2000-09-15 2006-09-19 Henkel Corporation Reworkable compositions incorporating episulfide resins
US6936664B2 (en) 2000-10-04 2005-08-30 Henkel Corporation Reworkable epoxidized 1-(cyclo) alkenyl ether/polycarboxylic acid product
US6572980B1 (en) 2001-08-13 2003-06-03 Henkel Loctite Corporation Reworkable thermosetting resin compositions
US6916890B1 (en) 2001-10-09 2005-07-12 Henkel Corporation Thermally reworkable epoxy resins and compositions based thereon
JP2007258207A (en) * 2006-03-20 2007-10-04 Three M Innovative Properties Co Bumped chip or package mounting method

Also Published As

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