JP3040033B2 - Output circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit device capable of flowing current into and discharging current from a capacitive load.

[0002]

2. Description of the Related Art FIG. 4 shows the configuration of a conventional output circuit device of this type. In FIG. 4, reference numeral 2 denotes a current supply switch for supplying a current to the capacitive load 1 connected to the output terminal.
N-type MOS transistor 3 is an N-type MOS transistor which is a current release switch for discharging charges accumulated in a capacitive load 1 connected to an output terminal, and 8 is a predetermined delay from a signal transmitted to P-type MOS transistor 2. This is a delay means for transmitting a signal to the N-type MOS transistor 3 with time. The input and output of the delay means 8 have the same phase, and the P-type MOS transistor 2 and the N-type MOS transistor 3 operate alternately. Reference numeral 9 denotes a driving unit for driving the P-type MOS transistor 2 and the delay unit 8, which has a necessary and sufficient driving capability with respect to the driving speed.

FIG. 5 is a diagram showing a specific circuit example of the output circuit device shown in FIG. 4. In FIG. 5, a P-type MOS transistor 2 as a current supply switch and an N-type MOS transistor 3 as a current discharge switch are shown. Inverter 1
1, 12 constitute the delay means 8, and the inverters 13, 1
The driving capability is increased by configuring the driving means 34 with 4, 15 and 16 to overlap the number of inverter stages.

On the other hand, in the figure, a, b, c, d denote each circuit portion, a is an input terminal, b is a gate of the P-type MOS transistor 2, c is a gate of the N-type MOS transistor 3, and d is an output terminal. Is shown. Voltage waveforms of these circuit portions are shown in FIGS. 6A to 6D in correspondence with each other. Hereinafter, FIG.
The operation will be described with reference to FIG.

First, as a first state, a state in which the circuit portion a as an input terminal is at a low level with respect to the inverter 13 will be considered. The output voltages of the inverters 13, 14, 15, 16 are sequentially output at a high level, a low level, a high level, and a low level. Therefore, the circuit portion b is given a low level at this time, and the P-type MOS transistor 2 is in an operating state.

On the other hand, the inverter 11 to which a low level is given outputs a high level, and the inverter 1 receiving this outputs a high level.
Since 2 outputs a low level, the circuit portion c is at a low level, whereby the N-type MOS transistor 3 is in a cutoff state. As described above, the capacitive load 1 connected to the output terminal receives the supply of the current from the P-type MOS transistor 2, and the circuit portion d, which is the output terminal, becomes high level.

Next, a state where the input terminal a is at a high level with respect to the inverter 13 is considered as a second state. Considering the same as in the first state, the inverters 13, 14, 1
The output voltages 5 and 16 become low level, high level, low level, and high level, respectively. That is, since the circuit portion b is at high level, the P-type MOS transistor 2 is turned off.

On the other hand, the inverter 11 receiving the high level input outputs a low level, and the inverter 12 outputs a high level.
The type MOS transistor 3 is activated. From the above,
The capacitive load connected to the output terminal releases charges by the N-type MOS transistor 3, and the output terminal d becomes low level.

[0009] While the above has considered a static state that does not include a temporal change, a dynamic state change that includes a temporal change will be described below. First, consider a state change in which the input terminal a, which is the first state, is at a low level, and the input terminal a, which is a second state, is at a high level. When the input terminal a changes from the low level to the high level, the inverters 13, 14,.
The signal is transmitted with a delay amount determined by the sizes of the devices 15 and 16, the manufacturing method, and the voltage applied to the power supply terminal. Similarly, since the signal is transmitted from the circuit part b to the circuit part c with a delay, the transition from the conductive state to the cut-off state of the P-type MOS transistor 2 (the circuit part b changes from a low level to a high level) occurs quickly. , Inverter 11, 1
After the delay made by step 2, the N-type MOS transistor 3 transitions from the cut-off state to the operating state (the circuit portion c changes from low level to high level).

Therefore, the P-type MOS in the first state is
Transistor 2 is operating, N-type MOS transistor 3
Is turned off, and the P-type MOS transistor 2 and the N-type M
After a state where both OS transistors 3 are shut off,
The state shifts to a second state in which the P-type MOS transistor 2 is turned off and the N-type MOS transistor 3 is turned on. Therefore, during the transition from the first state to the second state, the P-type MOS
The transistor 2 and the N-type MOS transistor 3 do not conduct simultaneously. The reason why the delay means 8 is provided is to prevent the simultaneous conduction.

Next, consider a state change in which the input terminal a, which is the second state, is at a high level, and the input terminal a, which is a first state, is at a low level. When the input terminal a changes from high level to low level, the inverter 16
Is transmitted with a delay amount to the output circuit portion b. Similarly, since the signal is transmitted from the circuit part b to the circuit part c with a delay amount, the transition from the cutoff state to the operating state of the P-type MOS transistor 2 (the circuit part b goes from high level to low level) occurs quickly. , Inverter 11, 1
After the delay performed by step 2, a transition from the operating state of the N-type MOS transistor 6 to the cutoff state (the circuit portion c changes from high level to low level) occurs.

Therefore, the P-type MOS in the second state
Transistor 2 cut-off state, N-type MOS transistor 3
From the operation state of P-type MOS transistor 2 and N-type MO
After both S transistors 3 are operating, P
The state shifts to the second state where the type MOS transistor 2 is in the operating state and the N-type MOS transistor 3 is in the cutoff state. Therefore, as shown in FIG. 6D, a period occurs in which the P-type MOS transistor 2 and the N-type MOS transistor 3 are simultaneously turned on during the transition from the first state to the first state.

[0013]

As described above, in the conventional configuration, when the output changes from the high level to the low level, the P-type MOS transistor 2 as the current supply switch and the N-type MOS transistor as the current release switch are used. 3 can be dealt with simultaneously, but when the output goes from low to high, the P-type MOS transistors 2 and N
There is a problem that a simultaneous conduction period of the type MOS transistor 3 occurs.

Even if the delay means is replaced by the P-type MOS transistor 2, simultaneous conduction occurs when the output switches from the high level to the low level. The simultaneous conduction period is between the P-type MOS transistor 2 and the N-type MOS transistor.
Since the current determined by the current supply capability of the transistor 3 flows from the power supply terminal to the ground terminal, the heavy capacitive load 1
To drive the P-type MOS transistor 2 or the N-type M
As the size of the OS transistor 3 increases, the current consumption increases. Further, when the high-frequency operation is to be performed, the current consumption increases with the operation frequency, so that there is a problem that a large amount of heat is generated.

Accordingly, an object of the present invention is to eliminate a simultaneous conduction period of a P-type MOS transistor as a current supply switch and an N-type MOS transistor as a current supply switch, thereby reducing output current and realizing high-frequency operation. It is to provide a circuit device.

[0016]

An output circuit device according to the present invention comprises a driving signal having a high level and a low level.
And a switch driving means for outputting a No. hand switch drive
Delayed drive signal obtained by delaying the signal output from the stage for a fixed time
Delay means for outputting a signal , and a control terminal to which a drive signal is given.
One main terminal is connected to the first power supply terminal,
When the drive signal is high between one and the other main terminals
Current supply switch to shut off
Switch, and a control terminal to which a drive signal is applied.
One main terminal is connected to the power supply terminal, and one and the other
When the drive signal is high between the main terminals,
Current emission off switch that shuts off at the time of bell and delay drive
A control terminal to which a signal is applied;
One main terminal is directly connected, and one and the other main terminal
Between the delay drive signal is high level and cut off
A current discharge on switch to conduct during the delay drive signal
Is provided, and one of the control terminals is provided to the second power supply terminal.
The main terminals are directly connected, and the connection between one and the other main terminals
Conduct when the delay drive signal is high level and when low
Switch off current supply and switch on current supply
Switch is connected and the current supply is turned off.
A control terminal to which the other main terminal of the switch is directly connected is provided.
One main terminal is connected to the first power supply terminal.
Between the other main terminal and the control terminal.
Current supply that shuts off when the
Supply switch and the other main terminal of the current release on switch
Directly connected and the other of the
It has a control terminal to which the main terminal is connected, and a second power supply terminal.
One main terminal is connected between one and the other main terminal
Is turned on when the signal applied to the control terminal is at a high level.
And a current release switch that cuts off at low level,
The other main terminals of the current supply switch and the current discharge switch
And a common load connected to drive the capacitive load.
I do.

[0017]

SUMMARY OF] According to the present invention, the current supply ON switch and the current discharge off switch is operated by the driving motion signal that is output from the switch driving means, the output current supply off switch and the current discharge-on switch from the delay means To
Since the operation is performed by using the delay signal, the current supply switch and the current emission switch can be alternately operated, and a period in which both the current supply switch and the current emission switch are in a cutoff state can be provided. The current supply switch and the current release switch do not conduct at the same time.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of an output circuit device according to an embodiment of the present invention. The same reference numerals as those in FIG. In FIG. 1, a P-type MOS transistor 2 is a current supply switch for supplying a current to a capacitive load 1 connected to an output terminal, and an N-type MOS transistor 3 is a current supply switch for discharging a charge stored in the capacitive load 1. Release switch. P-type MOS transistor 4 is
The P-type MOS transistor 5 is a current release on-switch for turning on the N-type MOS transistor 3. N
The type MOS transistor 6 is a current supply off switch for turning off the P-type MOS transistor 2, and the N-type MOS transistor 7 is a current release off switch for cutting off the N-type MOS transistor 3.

A P-type MOS transistor 4 serving as a current supply ON switch and an N-type MOS transistor serving as a current release OFF switch
The inputs of the transistor 7, that is, the gates are connected in common, and both are driven by an on / off drive signal output from a third drive unit 9 described later. The P-type MOS transistor 5 serving as a current release switch and the N-type MOS transistor 6 serving as a current supply off switch have their inputs, that is, gates connected in common, and are output from the switch driving means 9 via the delay means 8. Driven by an on / off drive signal. Where each of the above switches
And the correspondence between the MOS transistors will be described. M
Gate terminal of OS transistor becomes control terminal of switch
Equivalent, the source terminal of the MOS transistor is
One of the main terminals corresponds to the drain of the MOS transistor
The terminal corresponds to the other main terminal of the switch. Also,
Is the first power supply terminal in the description of
The second power terminal is referred to as a ground terminal.

The switch driving means 9 includes a P-type MOS transistor 4 serving as a current supply ON switch, an N-type MOS transistor 7 serving as a current release OFF switch, and a P-type MOS transistor
It drives the type MOS transistor 6 and has a necessary and sufficient driving capability with respect to the driving speed. FIG.
2 has a configuration as shown in FIG. 2, and the same reference numerals as those in FIG. As in the conventional example, the inverters 11 and 12 constitute the delay means 9, and the inverters 13, 14, 15, and 16 constitute the third drive means 9 to increase the drive capability by increasing the number of inverter stages. I have.

In the figure, A, B, C, D, E, and F indicate circuit parts, A is an input terminal, and B is a P-type MO.
Gate of S transistor 4 and N-type MOS transistor 7
, C is the gate of the P-type MOS transistor 5 and N
D is the gate of the N-type MOS transistor 3, D is the gate of the N-type MOS transistor 3, and E is the P-type MOS transistor 21.
And F indicates an output terminal. Voltage waveforms of these circuit portions are shown in correspondence with FIGS.

The operation of the above embodiment will be described below with reference to FIGS. First, in a state where the input terminal A is at a low level with respect to the inverter 13 as a first state,
The outputs of the inverters 13, 14, 15, 16 are sequentially output at a high level, a low level, a high level, and a low level. Therefore, the circuit portion B is given a low level,
The P-type MOS transistor 4 is in the operating state, and the N-type MOS transistor 7 is in the cutoff state.

On the other hand, the inverter 11 to which the low level is applied outputs a high level, and the inverter 1 receiving this outputs the high level.
Since 2 outputs a low level, the circuit portion C is at a low level, whereby the P-type MOS transistor 5 is turned on and the N-type MOS transistor 6 is turned off.
Therefore, the circuit parts D and E become high level,
Therefore, the P-type MOS transistor 2 is turned off, and the N-type
The S-transistor 3 enters an operating state, the charge accumulated in the capacitive load 1 connected to the output terminal F by the N-type MOS transistor 3 is discharged, and the output terminal F becomes low level.

Next, when the input terminal A, which is the input voltage, is at a high level with respect to the inverter 13 as the second state, the inverters 13 and 13 are considered in the same manner as in the first state.
The outputs 14, 15, and 16 become low level, high level, low level, and high level, respectively. Since the circuit portion B is at high level, the P-type MOS transistor 4 is turned off and the N-type MOS transistor 7 is turned on. .

On the other hand, the inverter 11 receiving the high level input outputs a low level, and the inverter 12 outputs a high level.
The type MOS transistor 5 is turned off, and the N-type MOS transistor 6 is turned on. Therefore, the circuit parts D,
Since E becomes low level, the P-type MOS transistor 2
Is in the operating state, the N-type MOS transistor 3 is in the cut-off state, and the capacitive load 1 connected to the output terminal F is
The charge is supplied by the S transistor 2 and the output terminal F
Becomes high level.

While the above description has considered a static state that does not include a temporal change, a dynamic state change that includes a temporal change will be described below. First, consider a state change in which the input terminal A, which is the first state, is at a low level, and the input terminal A, which is a second state, is at a high level. When the input terminal A changes from low level to high level, FIG.
As shown in (B), the output circuit portion B of the inverter 16
Are transmitted with a delay while increasing the driving capacity.

Since the delay is transmitted from the circuit portion B to the circuit portion C with a delay amount, the transition from the operating state of the P-type MOS transistor 4 to the cut-off state and the transition of the N-type MOS transistor 7 from the cut-off state to the operating state are performed. The transition from the operating state of the P-type MOS transistor 5 to the cut-off state and the transition of the N-type MOS transistor 6 from the cut-off state to the operating state after the delay previously determined by the circuit part B and performed by the inverters 11 and 12. It is determined by the circuit part C. Therefore, as shown in FIGS. 3D and 3E, the transition of the circuit portion D from the high level to the low level is early, and the transition of the circuit portion E from the high level to the low level occurs with a delay. .

Therefore, from the first state in which the P-type MOS transistor 2 is in the cutoff state and the N-type MOS transistor 3 is in the operating state, the P-type MOS transistor 2 and the N-type
After the state where both S transistors 3 are shut off, P
The state shifts to the second state in which the type MOS transistor 2 is in the operating state and the N-type MOS transistor 3 is in the cutoff state. For this reason, there is no case where the P-type MOS transistor 2 and the N-type MOS transistor 3 are simultaneously turned on during the transition from the first state to the second state.

Next, consider a state change in which the input terminal A, which is the second state, is at the high level, and the input terminal A, which is the first state, is at the low level. When the input terminal A changes from high level to low level, the inverter 16
Is transmitted with an amount of delay up to the output immediate circuit portion B.
Similarly, since the signal is transmitted from the circuit portion B to the circuit portion C with a delay amount, the transition from the cut-off state of the P-type MOS transistor 4 to the operation state and the transition from the operation state of the N-type MOS transistor 7 to the cut-off state are made. The transition from the cut-off state of the P-type MOS transistor 5 to the operating state and the shift of the N-type MOS transistor 6 from the operating state to the cut-off state occur after the delay caused by the circuit portion B and caused by the inverters 11 and 12. Caused by circuit part C. Therefore, as shown in FIGS. 3D and 3E, the transition of the circuit portion E from the low level to the high level is early, and the transition of the circuit portion D from the low level to the high level occurs with a delay.

Therefore, from the second state in which the P-type MOS transistor 2 is in the operating state and the N-type MOS transistor 3 is in the cut-off state, the P-type MOS transistor 2 and the N-type MOS
After the state where both S transistors 3 are shut off, P
The state shifts to the second state in which the type MOS transistor 2 is in the cut-off state and the N-type MOS transistor 3 is in the operating state. Therefore, there is a period during which the P-type MOS transistor 2 and the N-type MOS transistor 3 are simultaneously cut off during the transition from the first state to the second state.

When the output terminal voltage shifts from a low level to a high level or from a high level to a low level, both the P-type MOS transistor 2 of the current supply switch and the N-type MOS transistor 3 of the current release switch It can be seen that the state changes to the next state after being temporarily shut off. As described above, according to the embodiment of the present invention, the current supply switch and the current discharge switch are simultaneously set when the output changes from the high level to the low level or when the output changes from the low level to the high level. Since the conduction period can be prevented, the current consumption does not increase even if the size of the current supply switch or current release switch is increased in order to drive a heavy capacitive load. Can be suppressed.

[0032]

According to the output circuit device of the present invention, a period in which both the current supply switch and the current emission switch are in the cutoff state is provided during the switching period in which the current supply switch and the current emission switch are alternately operated. It is possible,
Since the current supply switch and the current discharge switch do not conduct at the same time, current consumption can be reduced. In addition, since the amount of heat generated can be reduced by reducing the current consumption, high-frequency operation can be performed. Ma
In addition, between the control terminal of the current supply switch and the second power supply terminal.
The switch connected between them is the current supply off switch
And the control terminal of the current release switch and the first power supply terminal.
The switch connected between the
Switch only when the current supply off switch is conducting.
Between the control terminal of the current supply switch and the second power supply terminal
The resistance component of the
A control terminal of the current release switch and a first power supply during normal operation
Since the resistance component between the terminals is small, the current supply switch
Large drive current to drive the
Easy to get flow. Therefore, even with a small chip size,
Sufficient driving capability can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a specific circuit configuration in the embodiment.

FIG. 3 is a diagram showing operation waveforms at various parts in FIG. 2;

FIG. 4 is a diagram showing a circuit configuration of a conventional example.

FIG. 5 is a diagram showing a specific circuit configuration of a conventional example.

FIG. 6 is a diagram showing operation waveforms at various parts in FIG. 5;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 capacitive load 2 P-type MOS transistor (current supply switch) 3 N-type MOS transistor (current release switch) 4 P-type MOS transistor (current supply on switch) 5 P-type MOS transistor (current release on switch) 6 N-type MOS Transistor (current supply off switch) 7 N-type MOS transistor (current emission off switch) 8 Delay means 9 Switch driving means 11-16 Inverter

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 17/00-17/693

Claims (1)

(57) [Claims] 1. A high level and a low level state are provided.
Switch driving means for outputting the obtained driving signal, and a signal outputted from the switch driving means being delayed for a predetermined time.
A first power supply , comprising: delay means for outputting an extended delay drive signal; and a control terminal to which the drive signal is applied.
One main terminal is connected to the terminal, and one and the other main terminal
When the drive signal is at a high level,
A second power supply , comprising: a current supply on switch for conducting at the time of a bell; and a control terminal to which the drive signal is supplied.
One main terminal is connected to the terminal, and one and the other main terminal
When the drive signal is at a high level, the
A current release off switch that shuts off at the time of a bell, and a control terminal to which the delayed drive signal is supplied,
One main terminal is directly connected to one power supply terminal.
When the delay drive signal is at a high level
Current release switch that shuts off
Switch, and a control terminal to which the delayed drive signal is applied,
One main terminal is directly connected to the power
When the delay drive signal is at a high level
Current supply switch that conducts when
And pitch, the other main terminal of the current supply on switch is connected
With the other main terminal of the current supply off switch
A control terminal connected to the first power supply terminal;
One main terminal is connected, and the connection between one and the other main terminal
When the signal applied to the control terminal is high level,
And the other main terminal of the current release on switch is directly connected.
And the other main terminal of the current emission off switch
Is connected to the second power supply terminal.
One main terminal is connected, and the connection between one and the other main terminal
When the signal applied to the control terminal is high,
A current release switch for interrupting at the time of a low level, and the other of the current supply switch and the current release switch.
An output circuit device wherein a capacitive load is driven by connecting a main terminal in common .