JP3040211B2 - Manufacturing method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a Bi-CMOS integrated circuit in which a bipolar transistor and a MOS transistor are integrated on the same semiconductor substrate, and more particularly to a method of manufacturing a semiconductor integrated circuit such as a method of forming an isolation region of a bipolar transistor. About the method.

[0002]

2. Description of the Related Art In recent years, as the speed of semiconductor integrated circuits and the coexistence of analog and digital circuits have progressed, Bi-CMOS integrated circuits in which bipolar transistors and CMOS transistors are integrated on the same substrate have become increasingly important. Is increasing.

A method of manufacturing a conventional Bi-CMOS integrated circuit device will be described below with reference to the process sectional views shown in FIGS.

In FIG. 2A, reference numeral 1 denotes a P-type single-crystal silicon substrate, which is a P-type single-crystal silicon substrate in which N-type buried regions 2a and 2b and P-type buried regions 3a and 3b are selectively formed through a mask process. The specific resistance is 1 to 5 on the crystalline silicon substrate 1.
An N-type or P-type silicon epitaxial layer 4 having a thickness of 0.5 to 5 μm and a thickness of Ωcm is formed.
2b, N well regions 5a and 5b connected thereto
A P-type isolation region 6 is formed on the P-type buried region 3a, and a P-well region 7 is formed on the P-type buried region 3b. Further, a thick silicon oxide film 8 having a thickness of 300 to 800 nm is grown by a selective oxidation method. At this time, the CMOS transistor formation region 9
a, 9b, base formation region 10 of NPN transistor,
The silicon surface other than the collector contact formation region 11 and the P-type isolation region 6 is covered with a thick silicon oxide film 8.

Next, as shown in FIG. 2B, the collector wall region 12 of the NPN transistor reaching the buried region 2a is formed by selectively implanting phosphorus and then performing thermal diffusion. Further, boron is selectively ion-implanted to form a base region 13 of the NPN transistor.
To form Thereafter, a thin silicon oxide film 14 serving as a gate oxide film is formed, and the emitter region of the NPN transistor is opened. A gate electrode 15, an emitter electrode 16 and a polysilicon line 17 are formed thereon by selectively forming a polysilicon film or the like doped with arsenic at a high concentration. Thereafter, impurities are introduced from the emitter electrode 16 by thermal diffusion to form the emitter region 18.

Next, as shown in FIG. 2C, arsenic is selectively ion-implanted to form a source region 19a and a drain region 19b of the N-channel MOS transistor. Further, BF ₂ is selectively ion-implanted to form the source region 20a and the drain region 20b of the P-channel MOS transistor, and at the same time, a high-concentration P-type diffusion layer 22 is formed on the external base region 21 and the isolation region of the NPN transistor. Form.

[0007]

In such a conventional structure, when the polycrystalline silicon wiring 17 is arranged so as to cross over the P-type isolation region 6, the P-type isolation region 6 just below the polycrystalline silicon wiring 17 is formed. The polycrystalline silicon wiring 17 serves as a mask, and the high-concentration P-type diffusion layer 22 is not formed. Therefore, when the polysilicon wiring 17 is formed on the P-type isolation region 6, the polysilicon wiring 17 is used as a gate electrode, the thin silicon oxide film 14 is used as a gate oxide film, and the P-type isolation region 6 is formed.
Is the substrate, the N well region 5a is the source, and the N well region 5b is
Is formed as a drain. The surface concentration of the P-type isolation region 6 is N channel M
It is equal to the surface concentration of the P-well region 7 immediately below the gate of the OS transistor, that is, about 5 × 10 ¹⁶ cm ⁻³ , and when the thickness of the thin silicon oxide film 14 is 20 to 30 nm, the inversion voltage becomes about 1 V and 5 V Under the use of a power supply, a leak current easily flows from N well region 5b to N well region 5a. Therefore, since the polycrystalline silicon wiring 17 cannot be arranged so as to cross the P-type isolation region 6, there is a disadvantage that the degree of freedom of the wiring layout is reduced and the chip size is increased.

When the P-type isolation region 6 is covered with a thick silicon oxide film 8, the inversion voltage of the parasitic N-channel MOS transistor can be increased.
No P-type diffusion layer 22 is formed thereon, and the resistance of the P-type isolation region 6 increases. Therefore, it is necessary to increase the number of substrate contacts provided for stabilizing the substrate potential, and there is a disadvantage that the layout of the aluminum wiring is restricted.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and provides a semiconductor integrated circuit capable of increasing the degree of freedom in the layout of a polycrystalline silicon wiring region, reducing the restrictions on the layout of aluminum wiring, and reducing the chip size. It is intended to provide a manufacturing method.

[0010]

In order to achieve this object, a method of manufacturing a semiconductor integrated circuit according to the present invention comprises a region for forming a bipolar transistor and an insulated gate field effect transistor, and a region for separating one conductivity type junction of the bipolar transistor. Forming an insulating film on the semiconductor substrate excluding the formation surface, and simultaneously forming a high-concentration one-conductivity-type diffusion layer on the surface of the one-conductivity-type active base region and the one-conductivity-type junction isolation region of the bipolar transistor; Forming a thin insulating film on the semiconductor substrate, forming an opening for forming an emitter region of the bipolar transistor in the thin insulating film, and forming a predetermined portion on the opening and the thin insulating film. By depositing a conductive film, the gate electrode of the insulated gate field effect transistor, the emitter electrode of the bipolar transistor and the conductive Simultaneously forming a wiring made of a film, heat-treating the semiconductor substrate, introducing impurities from the conductive film by diffusion to form an emitter region of the bipolar transistor, and forming a reverse conductive type insulated gate field effect transistor. Forming a source region and a drain region; and simultaneously forming a high concentration one conductivity type diffusion layer on the source and drain regions of the one conductivity type insulated gate field effect transistor and the surface of the one conductivity type junction isolation region. And at least the step of performing

[0011]

With this structure, a high-concentration one-conductivity-type diffusion layer is formed on the surface of the one-conductivity-type junction isolation region in a base region forming step of the bipolar transistor before forming a wiring made of a conductive film such as polycrystalline silicon. Since the surface concentration of the one-conductivity-type junction isolation region is sufficiently high and the inversion voltage is higher than the used power supply voltage, a wiring made of a conductive film such as polycrystalline silicon is formed on the one-conductivity-type junction isolation region. Also, the N-channel MOS transistor having the wiring as the gate electrode, the thin insulating film as the gate oxide film, the one conductivity type isolation region as the substrate, and the N well region as the source and drain does not operate, and no leak current flows.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention is shown in FIGS.
This will be described with reference to the process sectional view shown in FIG. FIG. 1A is the same as FIG. 2A of the conventional example, and the description is omitted. The N-type buried regions 2a and 2b have a maximum impurity concentration of about 1 × 10 ¹⁸ cm ⁻³ and a sheet resistance of about 100Ω /.
□, the P-type buried regions 3a and 3b have a maximum impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ and a sheet resistance of about 300Ω /
□. The N well regions 5a and 5b, the P type isolation region 6 and the P well region 7 each have a surface concentration of about 5 × 1
0 ¹⁶ cm ^-3 and the sheet resistance is about 5 kΩ / □ each.

Next, in FIG. 1 (b), phosphorus is selectively ion-implanted at about 5 × 10 ¹⁵ cm ^{−2 in the same} manner as in the conventional example.
By performing thermal diffusion at 000 ° C. or 1100 ° C.
The collector wall region 12 of the PN transistor is formed. Further, boron is selectively ion-implanted to about 5 × 10 ¹³ cm ⁻² , and a high concentration of P on the P-type isolation region 6 is simultaneously formed with the base region 13 of the NPN transistor having a surface concentration of about 5 × 10 ¹⁸ cm ^−3. Forming the mold diffusion layer 23 is a feature of the present invention. Thereafter, a silicon oxide film 14 having a thickness of 20 to 30 nm is formed as a gate oxide film as in the conventional example, and an emitter region of the NPN transistor is opened. On this, arsenic is doped at a high concentration, and the specific resistance is about 4 × 10 ⁻³ Ω.
A gate electrode 15, an emitter electrode 16, and a polycrystalline silicon wiring 17 are formed by selectively forming a polycrystalline silicon film having a thickness of 200 to 500 nm in cm. Thereafter, impurities are introduced from the emitter electrode 16 by thermal diffusion to form the emitter region 18.

Next, in FIG. 1 (c), about 4 × 10 ¹⁵ cm ⁻² of arsenic is selectively ion-implanted into N
A source region 19a and a drain region 19b of the channel MOS transistor are formed. Furthermore, BF ₂ is about 3
× 10 ¹⁵ cm ^-2 P-channel MOS with selective ion implantation
Source region 20a and drain region 2 of transistor
At the same time as forming Ob, a high-concentration P-type diffusion layer 24 is formed on the external base region 21 and the P-type isolation region 6 of the NPN transistor.

According to this manufacturing method, the surface concentration is about 5 × 10 ¹⁸ cm ⁻ on the P-type isolation region 6 in the step of forming the base region of the NPN transistor before the step of forming the gate electrode 15 and the polysilicon wiring 17. the ^third high-concentration P-type diffusion layer 23 formed to have a high surface concentration of the P-type isolation region 6. Therefore, a gate oxide film having a thickness of 2
Even if the polysilicon wiring 17 is formed via the thin silicon oxide film 14 of 0 to 30 nm, the polysilicon wiring 1
7 is a gate electrode, the thin silicon oxide film 14 is a gate oxide film, the P-type isolation region 6 is a substrate, the N well region 5a is a source, and the N well region 5b is a drain. Therefore, at a power supply voltage of 5 V, the parasitic N-channel MOS transistor does not operate and no leak current flows. As described above, the method for manufacturing a semiconductor integrated circuit according to the present invention allows the polysilicon wiring 17 to be arranged on the P-type isolation region 6, and can eliminate the restrictions on the layout. Although the same effect can be obtained by covering the P-type isolation region 6 with the thick silicon oxide 8, the resistance of the P-type isolation region 6 increases. However, according to the present invention, a high-concentration P-type diffusion layer 24 is formed on the surface of the P-type isolation region 6 other than immediately below the polysilicon wiring 17.
Since the impurity concentration is increased by forming a high-concentration P-type diffusion layer 23 on the surface of the P-type isolation region 6 directly below the P-type isolation region 6, the resistance of the P-type isolation region 6 is low, and in order to stabilize the substrate potential. The distance between the provided substrate contacts can be increased, and the restriction on the layout of the aluminum wiring can be reduced.

In the embodiment of the present invention, a polycrystalline silicon film is used as the conductive film for the gate electrode 15, the emitter electrode 16, and the polycrystalline silicon wiring 17, but a metal silicide film or a high melting point metal film can be used. Needless to say.

[0017]

As described above, according to the present invention, a high-concentration one-conductivity-type diffusion layer is formed on the surface of a one-conductivity-type junction isolation region when a base region is formed before forming a gate electrode and a wiring made of a conductive film such as polycrystalline silicon. Manufacturing of a semiconductor integrated circuit capable of increasing the degree of freedom in the layout of a wiring region made of a conductive film such as polycrystalline silicon, reducing the restrictions on the layout of aluminum wiring, and reducing the chip size. We can provide a method.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a method of manufacturing a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 2 is a process sectional view of a conventional method for manufacturing a semiconductor integrated circuit.

[Explanation of symbols]

Reference Signs List 1 P-type single-crystal silicon substrate (semiconductor substrate) 2 a, 2 b N-type buried region 3 a, 3 b P-type buried region 4 P-type silicon epitaxial layer 5 a, 5 b N-well region 6 P-type separation region (one conductivity type junction separation region) Reference Signs List 7 P well region 8 Silicon oxide film (insulating film) 9a, 9b CMOS transistor forming region 10 Base forming region of NPN transistor 11 Collector contact forming region 12 Collector wall region 13 Base region 14 Silicon oxide film 15 Gate electrode 16 Emitter electrode 17 Many Crystal silicon wiring (wiring made of conductive film) 18 Emitter region 19a Source region (source region of insulated gate field effect transistor of reverse conductivity type) 19b Drain region (drain region of insulated gate field effect transistor of reverse conductivity type) 20a Source region( 20b Drain region (drain region of one-conductivity-type insulated gate field-effect transistor) 21 External base region 23, 24 High-concentration P-type diffusion layer (high-concentration Conductive diffusion layer)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/06 H01L 21/8222 H01L 21/8249 H01L 21/768

Claims (1)

(57) [Claims] 1. A method for manufacturing a semiconductor integrated circuit, comprising : forming a bipolar transistor and a complementary insulated gate field effect transistor on a semiconductor substrate;
After forming a junction separation region of one conductivity type, the bipolar
One conductive type active base region of the transistor and the junction
Simultaneously forming a high concentration one conductivity type diffusion layer on the surface of the isolated region,
Thereafter, a conductive film is deposited on the semiconductor substrate, and the conductive film is deposited.
An emitter electrode of the bipolar transistor,
Gate of the complementary insulated gate field effect transistor
An electrode and a wiring straddling at least the junction isolation region
Is formed at the same time, then one conductivity type insulated gate field effect
Self-aligned to the gate electrode of the transistor
Source and drain regions formed and surface of the junction isolation region
Forming a high-concentration one-conductivity-type diffusion layer at the same time .