JP3041930B2 - Synchronous signal reproduction circuit - Google Patents

Description

Description of the Related Art [0001] The present invention relates to a synchronous signal reproducing circuit for reproducing a synchronous signal in a television receiver, a monitor device, or the like.

2. Description of the Related Art Conventionally, in a television receiver or the like, a horizontal synchronizing signal (hereinafter, referred to as an Hsync signal) and a vertical synchronizing signal are used by using a countdown circuit in order to ensure stable operation of a deflection circuit when an input signal is interrupted. The synchronization signal (hereinafter, referred to as Vsync signal) is re-created and supplied to the deflection circuit. This countdown circuit generates a clock phase-locked to a Hsync signal input from the outside by a phase-locked loop (hereinafter, referred to as a PLL), counts this clock, and when the count value reaches a predetermined value, reproduces the Hsync signal. A signal and a reproduced Vsync signal are generated.

When the external Vsync signal is within a predetermined range in relation to the external Hsync signal, the count is set to the external Vsyn.
The counter is initialized each time by the c signal, and when the external Vsync signal is out of the range or is interrupted, the counter itself repeats the initialization to perform the counting operation, and the decoding circuit generates the reproduced Vsync signal. Even if the external Hsync signal is interrupted, the PLL generates a clock in a free running state, so the reproduced Hsync signal and the reproduced Vsy
The nc signal is supplied to the deflection circuit without interruption.

[Problems to be Solved by the Invention] In a television receiver, in the case of an unstable reception state such as a weak electric field condition, depending on the position of the external Vsync signal output from the synchronization separation circuit before this countdown circuit. , (For example, when the external Vsync signal portion of the composite signal is being crushed by noise, etc.),
In the worst case, even a slight jitter in period A as shown in FIG. 13 (b) may be detected as a jitter (about 1H width) in period B as shown in FIG. 13 (c). is there.

That is, in the conventional countdown circuit, the external Vsync
If the signal is within a predetermined range in relation to the external Hsync signal, it is used as is for initializing the counter, so it is necessary to detect and deal with slight fluctuations in the external Vsync signal that may cause jitter. However, there is a problem that it appears on the screen as vertical jitter of 1H width.

The present invention has been made in view of such a situation, and provides a synchronous signal reproducing circuit which is hardly affected by jitter.

[Means for Solving the Problems] In order to solve such problems, a synchronization signal reproducing circuit according to the present invention is initialized by a counter initialization signal generated based on an external horizontal synchronization signal and an external vertical synchronization signal. In the synchronous signal reproducing circuit for reproducing the reproduced vertical synchronizing signal in accordance with the count value of the counting section, the timing of occurrence of the change point of the external vertical synchronizing signal is close to the generation timing of the external horizontal synchronizing signal, or the intermediate timing. External vertical synchronizing signal phase detecting means for detecting whether or not the clock signal is present, clock generating means for generating two-phase clock signals having phases different from each other by 180 degrees synchronized with the external horizontal synchronizing signal, and external vertical synchronizing signal phase detecting means. A clock selecting means for selecting one of the two-phase clock signals according to the detection result, and detecting a change point of the external vertical synchronizing signal with the selected clock signal Initializing signal generating means for generating the count initializing signal in response to the change point, wherein the clock selecting means includes a hysteresis means for giving a hysteresis to the detection result of the external vertical synchronizing signal phase detecting means. And selecting the clock signal in accordance with the output of the hysteresis means.

[Operation] In the synchronization signal reproducing circuit having the above configuration, the external vertical synchronization signal phase detection means determines whether the timing of occurrence of the change point of the external vertical synchronization signal is near or intermediate to the generation timing of the external horizontal synchronization signal. Is detected. One of the two-phase clock signals is selected according to the detection result, and the change point of the external vertical synchronization signal is detected by the selected clock,
A count initialization signal is generated corresponding to this change point.
This makes it possible to reproduce a reproduced vertical synchronizing signal which is less affected by jitter. In addition, since the detection result of the phase of the external vertical synchronization signal has hysteresis, the influence of local jitter can be suppressed.

Embodiment FIG. 2 is a block diagram showing a configuration of an embodiment of a television receiver using a countdown circuit as a synchronization signal generation circuit according to the present invention.

The EDTV processing circuit 2 performs processing for ghost cancellation on the input NTSC video signal, and converts Hsync to 2 in order to convert from an interlace system to a line sequential system.
Perform double speed processing to generate Hsync. Sync separation circuit 1
Separates the synchronization signal from the input NTSC video signal and supplies it to the EDTV processing circuit 2.

The video signal processed by the EDTV processing circuit 2 is converted into an aspect suitable for CRT9 by the aspect conversion circuit 3,
After being supplied to the amplifier 7 through the contact a of the switch 5 and amplified, it is output to the CRT 9 and displayed. On the other hand, the synchronization signal (2Hsync, Vsync, etc.) output from the EDTV processing circuit 2 is input to the countdown circuit. The countdown circuit 4 generates a new synchronization signal (reproduction synchronization signal) in synchronization with the input synchronization signal (external synchronization signal), and a contact a of the switch 6
Is supplied to the deflection circuit 8. The deflection circuit 8 controls deflection scanning of the CRT 9 according to the input synchronization signal.

When displaying an image of the HDTV system such as high definition, the switches 5 and 6 are switched to the contact b side. The video (luminance signal) is supplied to the amplifier 7 via the switch 5 and the synchronization signal is supplied to the deflection circuit 8 via the switch 6.

The countdown circuit 4 is configured, for example, as shown in FIG. This circuit is roughly divided into a jitter removing unit 11 and a countdown unit 12, and the jitter removing unit 11 has doubled Hs
a new 2Hsync signal (hereinafter, referred to as a reproduction 2Hsync signal), a VJTW signal as a reference signal for phase comparison, an HCLK signal for timing, and a phase of 180 A timing generator 31 for generating different XHCLK signals, a falling edge phase determiner 32 for determining a falling edge appearance position of an input (external) Vsync signal, and selecting an HCLK signal and an XHCLK signal which are two-phase clock signals. The clock switching unit 33 sets the falling edge of the Vsync signal to 1 by the differentiation clock signal (the HCLK signal or the XHCLK signal selected by the clock switching unit 33).
It comprises a differentiator 34 that generates a counter initialization pulse Vinit with no jitter by differentiating with a clock width.

The countdown unit 12 has a built-in counter (35 in FIG. 11).
a) A window timing generator 35 that generates a window signal necessary for correctly performing the initialization, a window processor 36 that ensures stable operation even in the case of an unstable Vsync signal, and a new Vsync signal , A playback Vsync signal).

(A) Jitter Removal Unit 11 FIG. 3 is a circuit diagram showing a more detailed configuration of the jitter removal unit 11, and FIG. 4 shows the timing of a signal generated by the timing generation unit 31. The timing generator 31 outputs a clock CK (fourth clock) oscillated by a voltage controlled oscillator (hereinafter, referred to as VCO) 31c.
The phase comparator 31a, the low-pass filter (LPF) 31b, the VCO 31c, the counter 31d, the decoder 31e, the free-running resistor 31f, so that the frequency becomes a 455-fold frequency synchronized with the external 2Hsync signal as shown in FIG. It comprises a PLL consisting of 31g and an initial value setting circuit 31h. The falling edge phase determination unit 32 includes a NAND circuit 32a for generating a Vdwn signal (a signal for detecting a falling edge of an external Vsync signal), a D-type flip-flop 32b, a 4-bit up / down counter 32c,
It is composed of an RS type flip-flop 32d.
The differentiator 34 includes D-type flip-flops 34a and 34b and a NOR circuit 34c.

Note that the decoder 31e, flip-flop 32b, flip-flop 34a, and NAND circuit 32a are connected to an external vertical synchronization (Vsync).
An external vertical synchronizing signal phase detecting means for detecting whether the signal change point is near the external horizontal synchronizing (2Hsync) signal or near the center of the external horizontal synchronizing signal period.

The counter 31d counts the clock CK output from the VCO 31c, and outputs the count value to the decoder 31e.
When the count value of the counter 31d becomes -1, the decoder 31e outputs a load signal LD so that the initial value -455 output from the initial value setting circuit 31h is loaded into the counter 31d at the next timing. As a result, the counter 31d becomes −455
The counting operation from to -1 is repeated.

When the count value of the counter 31d reaches the predetermined value shown in FIG. 4, the decoder 31e outputs the HREF signal (4th
In addition to FIG. 4 (b), a reproduced 2Hsync signal (FIG. 4 (f)), a two-phase clock signal HCLK signal (FIG. 4 (d)) synchronized with this 2Hsync signal and having a phase difference of 180 degrees from each other and XHCLK A signal (FIG. 4 (e)) and a VJTW signal (FIG. 4 (g)) for determining the phase of the falling edge of the Vsync signal are generated.

The HREF signal having a falling edge when the count value is -455 and a rising edge when the count value is -227 is supplied to a low-pass filter 31b via a phase comparator 31a constituted by a switch. The phase comparator 31a is turned on while 2Hsync (FIG. 4A) is at a low level. When the phase of 2Hsync and HREF signal match, the falling edge of HREF signal is 2Hsy
Located in the middle of the low level period of NC. Therefore, when the phase comparator 31a is turned on, the high-level and low-level periods (lengths) output are equal. On the other hand, when the phase changes, a difference occurs between the high-level period and the low-level period. Therefore, this difference is smoothed by the low-pass filter 31b, and the VCO 31c
, The phase of the clock CK output from the VCO 31c is synchronized with the phase of the 2Hsync signal.

2 When the Hsync signal is not input, the reference voltage Vcc is
The VCO 31c is driven by the voltage divided by 1f and 31g, so the VCO
The oscillation operation of 31c does not stop.

As described above, even when there is no signal, the reproduction 2Hsync signal can be continuously output by the free running operation of the PLL. The HCLK signal used in the countdown unit 12 is also output in the same manner, so that stable operation including the countdown unit 12 is guaranteed.

5B to 8 show the phase of the HCLKS signal, which is the signal selected by the clock switching unit 33, and the VJT signal with the Vdwn signal.
6 is a time chart classified according to a phase as a result of latching a W signal.

An outline of the operation of the circuit shown in FIG. 3 will be described. The flip-flop 32b uses the Vdwn signal to output the VJTW signal (as shown in FIG. 4 (g), the count value of the counter 31d is -331 to -10).
Is low during the period up to 5).
Level, the falling edge of the Vsync signal is 2Hsync
It exists near the signal (within the range indicated by the symbol A in FIG. 5B), and when at the L level, exists at the center (within the range indicated by the signal B in FIG. 6B). The output of the flip-flop 32b switches the up-count and the down-count of the counter 32c, counts the frequency of occurrence of the falling position of the Vsync signal, and, according to the frequency of occurrence, the flip-flop 32d
Generates the XHCLK signal and the signal for selecting the HCLK signal.

When the Vsync signal falls continuously 16 times or more in the section indicated by the symbol A of the VJTW signal in FIG. 5 (b), the XHCLK signal is used as the differentiation clock HCLKS signal, and the VH signal is used for the 7th or more times. The HCLK signal is used in the section shown by the signal B in FIG. This allows Vsync
Even if there is a jitter component in the signal, sufficient margin can be obtained and Vs
The ync signal is not expanded to 1H width.

The above is the outline of the operation of the circuit in FIG. 3, and the detailed operation will be described below.

When the power is turned on, the counter of the timing generator 31
31d loads -455 data from the initial value setting circuit 31h and generates a clock signal shown in FIG.
Count up CK. When the count value becomes -1 by counting up, the operation of loading data with -455 data is repeated.

The decoder 31e corresponds to the count value of the counter 31d,
The HREF signal, the clock HCLK signal, the XHCLK signal having the opposite phase to the HREF signal, and the reproduction 2Hsync signal shown in FIGS. 4 (b), (d), (e) and (f) are generated. All of these signals are external
Synchronized with the 2Hsync signal (Fig. 4 (a))
Even when the nc signal is not supplied, the signal is generated because the VCO 31c performs a free running operation. The HCLK signal and the XHCLK signal have the same frequency as the external 2Hsync signal.

The decoder 31e also generates a phase comparison reference VJTW signal shown in FIG. 4 (g). This signal is a signal whose count value is L level between -331 and -105, and which is H level at other count values. As described later, the generation timing of the Vsync signal is near the external 2Hsync signal, The user recognizes whether the part is near the part.

The circuit of FIG. 3 uses the state of the falling edge of the Vsync signal to determine the state of FIG. 5 (this state is defined as state a).
Alternatively, it starts from the state shown in FIG. 6 (this state is defined as state b). The state of FIG. 5, ie, state a
, The rising edge of the Vdwn signal (FIG. 5 (e)) generated by the external Vsync signal and the differentiation clock HCLKS signal is the symbol of the phase comparison reference VJTW signal (FIG. 5 (b)). Since it is in the section of H level indicated by A, the output of the flip-flop 32b for up / down (U / D) selection becomes H level, and the counter 32c counts up.

Since the output of the flip-flop 32d has already been set to the H level by the power-on setting, the XHCLK signal is selected as the HCLKS signal (FIG. 5 (d)) at this time. Therefore, the HCLK
The Vinit signal (FIG. 5 (f)) output at the rising of the S signal is sufficiently far from the falling point of the Vsync signal (FIG. 5 (c)). The signal is not affected by the jitter. The state shown in FIG. 5 is a stable state.

When starting from the state of FIG. 6, that is, state b, the rising of the Vdwn signal (FIG. 6 (e)) starts from the section indicated by the symbol A of the VJTW signal for phase comparison reference (FIG. 6 (b)). Since it has moved to the section indicated by the signal B, the output of the flip-flop 32b for U / D selection becomes L level and the counter 32c
Count down. HCLKS signal (Fig. 6 (d))
Since the XHCLK signal is still selected, the timing of the rising edge of the HCLKS signal and the timing of the falling edge of the external Vsync signal are close to each other, and there is a possibility that the effect of jitter appears on the Vinit signal generated in the differentiator 34. is there. V
When the position of the sync signal (FIG. 6 (c)) continues continuously, the count value of the counter 32c that continues counting down becomes zero, the borrow output (BO) becomes H level, and the output of the flip-flop 32d is output. Let Q be L level. At this time, the switching unit 33 is switched, and the HCLKS signal becomes H level.
When the CLK signal is selected, the state shown in FIG.
Defined).

However, before the count value of the counter 32c becomes zero, Vsy
When the position of the nc signal moves to the section indicated by the symbol A, the fifth
Returning to the state shown in the figure, the counter 32c switches from down counting to up counting. H depending on the position of the Vsync signal
By not switching the CLKS signal immediately and switching the HCLKS signal when the count value of the counter 32c becomes 0 or less, the temporary jitter of the external Vsync signal causes the entire system to not respond. We are taking measures.

In the state shown in Fig. 6, there is a possibility that 1H-width jitter may occur.
After the jitter occurs during the field (about 0.26 seconds), the state is shifted to the state shown in FIG. 7 which is a stable state. The state shown in FIG. 6 is a transition state.

In the state of FIG. 7, that is, state c, the Vdwn signal (FIG. 7 (e)) is a VJTW signal for phase comparison reference (FIG. 7 (b)).
And the counter 32c counts down. Since the HCLK signal is selected for the HCLKS signal (FIG. 7 (d)), there is sufficient margin in the differentiator 34 (the timing of the rising edge of the HCLKS signal and the timing of the falling edge of the external Vsync signal are sufficiently separated. A), the effect of jitter on the Vinit signal is small. This state is a stable state.

The state in FIG. 8 (this state is defined as state d) is Vdwn
Since the signal (FIG. 8 (e)) has moved from the section of symbol B to the section of symbol A of the VJTW signal for phase comparison reference (FIG. 8 (b)), the counter 32c starts counting up. The HCLKS signal (FIG. 8 (d)) still selects the HCLK signal, and there is a possibility that jitter will occur if this is not done.

If the position of the Vdwn signal continues continuously, the count value becomes 16, the carry output (CO) becomes H level,
The flip-flop 32d is set, and its output Q is set to H
At this time, the switching unit 33 selects the XHCLK signal as the HCLKS signal, and shifts to the stable state shown in FIG. If the Vdwn signal returns to the section indicated by the symbol B of the VJTW signal on the way, the seventh
The state returns to the state shown in FIG. The state shown in FIG. 8 is a transition state.

FIG. 9 summarizes the above operation in a state transition diagram, and the symbols a, b, c, and d represent the states a to d in FIGS. 5 to 8, respectively. That is, depending on whether the falling timing of the Vsync signal is in the section A or B, whether the state is on the right side (section B) or the state on the left side (section A), that is, whether the countdown is performed,
It is determined whether the count up is performed. Whether the state is the upper state or the lower state in the figure is determined depending on whether a carry output is generated (upper side) or a borrow output is generated (lower side).

FIG. 10 is an example showing the relationship between each of the states a to d and the count value of the counter 32c. Since the XHCLK signal is initially selected in the state a, the counter 32c
As a result of counting up to state b, the state shifts to state b and counts down. However, state a and state b are repeated, the count result eventually reaches zero, the state changes to state c, and HCLK
It has switched to a signal. Then, the counter 32c counts up again, and when the count reaches 15 while repeating the state c and the state d, the state shifts to the state a and is switched to the XHCLK signal.

As described above, it is practically important to use the counter 32c to give hysteresis to the transition between states and to cope with a local jitter tendency change. In this example, a 4-bit counter has been described. However, in an actual circuit, an appropriate one is selected and used according to the characteristics of the synchronization separation circuit. As described above, the influence of jitter can be reduced, and a Vinit signal for initializing the subsequent countdown unit 12 can be generated stably.

The initialization signal Vinti ((f) in FIGS. 5 to 8)
In any of the states a to d, the previous differentiation clock
The level of the Vsync signal is H at the timing of the HCLKS signal (the output of the flip-flop 34b is L), and the level of the Vsync signal is L at the timing of the current differentiation clock HCLKS signal (the output Q of the flip-flop 34a is H ) Is generated such that the edge rises in synchronization with the rising edge of the differentiation clock HCLKS signal.

(B) Countdown unit 12 This part comprises a window timing generation unit 35, a window processing unit 36, and a Vsync signal generation unit 37, as shown in FIG. The window timing generator 35 is reset by a Vinit signal input at a predetermined timing and counts up a clock HCLK signal.
35a, inverter 35b, OR circuits 35c, 35d, RS type flip-flop 35e, decoder 35f, which outputs a WO signal when the count result of counter 35a is -64 and generates an LD2 signal when the count result is -71. It is composed of a flip-flop 35g of the type and an initial value setting circuit 35f.

The window processing unit 36 includes an AND circuit 36a.

The Vsync generating section 37 is a decoder 37 for generating the reproduced Vsync while the count result of the counter 37a, the inverter 37b, and the counter 37a for generating the reproduced Vsync signal is between -5 and -1.
c, an initial value setting circuit 37d.

The operation of this circuit will be described with reference to the time chart of FIG. The portion (1) in FIG. 12 is an unstable section after the power is turned on. As shown in FIG. 12 (b), when the power-on reset is performed at time t0, the OR circuit 35c
, The counter 35a loads the data of −525 from the initial value setting circuit 35f, and starts counting up the HCLK signal (FIG. 12 (a)). . When the count value reaches -71, the decoder 35f outputs the counter 37a at time t2 as shown in FIG.
Generates a load LD2 signal, and the counter 37a of the Vsync generator 37 to which the signal is supplied is supplied to the initial value setting circuit 37.
The initial value -71 is loaded from d, and counting up of the HCLK signal is started (FIG. 12 (i)).

The counter 37a uses the HCLK signal as a clock similarly to the counter 35a, and the decoder 37c decodes the count value of the counter 37a between -5 and -1 as a reproduced Vsync signal as shown in FIG. 12 (k). And output. When the count value becomes 0 at time t4, the twelfth
As shown in FIG. 7I, the carry output (CO2) is input via the inverter 37b, and the counter 37a is in a non-operating state until the next LD2 signal is supplied.

On the other hand, at time t3, the count value of the counter 35a becomes -6.
4, the decoder 35f outputs an H-level window signal WO as shown in FIG.
As shown in FIG. 12 (h), the window signal V
The wdw signal is supplied to the AND circuit 36a. As a result, the AND circuit 36a validates the Vinit signal, which is a counter initialization signal, while the window signal Vwdw is being supplied.

At this time, the Vsync signal input from the outside (therefore, the Vinit signal) and the count operation are irrelevant (in this example, at time t1 in FIG.
nit signal is generated). When the count value of the counter 35a reaches -1, a carry output CO1 is output as shown in FIG. 12 (f), which is input via the OR circuit 35c, the counter 35a is initialized, and the flip-flop 35e is set. Therefore, as shown in FIG. 12 (e), the window signal W1 (output of the flip-flop 35e) is output via the OR circuit 35d as an H level Vwdw signal as shown in FIG. 12 (h). .

As shown in FIG. 12 (c), this H level Vwdw signal is output until the Vinit signal is input at time t5 (the output of the flip-flop 35g becomes H by the Vinit signal, and the H output resets the flip-flop 35e). Continue until done). In this example, as shown in FIG.
When the count value of the counter 35a is -400, the Vinit signal is input as the LD1 signal via the AND circuit 36a and the OR circuit 35c, so that the data of -525 is taken into the counter 35a,
As shown in FIGS. 12 (e) and (h), the window signal
The W1 and Vwdw signals are reset.

From this point, the counter 35a starts a count operation synchronized with the Vinit signal. That is, the counter 35a starts counting down when data of -525 is taken in by the Vinit signal, and starts a counting operation synchronized with the Vinit signal.

The power-on unstable section can be up to two fields (3
4.4ms). A similar operation is performed in a discontinuous section such as when switching channels.

The section shown in Fig. 12 (1) is the Vsyn with the correct period (525H).
This is the section where the c signal is supplied. Vsync signal ie
When the Vinit signal is input with a period of exactly 525H, the operation of the counter 35a is accurately synchronized with the input of the Vinit signal. Therefore, the Vinit signal shown in FIG. 12 (c) and the carry output CO1 shown in FIG. 12 (f) are simultaneously generated at the time point t6, so that the Vwdw signal shown in FIG.
It is dominated by the output generation period of the WO signal. And the decoder 37
The phase of the reproduced Vsync signal generated by c and the phase of the external Vsync signal input to the jitter removing unit 11 substantially match.

The section (1) in FIG. 12 has a short period (for example, 505H)
Is a section where the Vsync signal is supplied. Counter 35a
Is between -64 and -1 corresponding to the last 12% of the Vsync signal period, the decoder 35f outputs an H level signal as the window signal WO as shown in FIG. 12 (d). I do. This is as shown in FIG. 12 (h).
The signal becomes a dw signal, and only the first Vinit signal input in this section is used for initializing the counter 35a. Fig. 12 (c)
At time t7, the Vinit signal is input and the counter 3
When 5a is initialized, the window signal WO changes to the state shown in FIG.
As shown in the figure, the level immediately becomes L level.
Even if t signals occur frequently, double initialization is prevented.

In this example, when the count value of the counter 35a reaches -20, the Vinit signal is input and becomes the LD1 signal as shown in FIG. 12 (g).
Initialized without using 1). The counter 35a may be initialized with a period of 525H or less, or may be initialized twice in a short period of time as in the section described later. A counter 37a for counting is provided, and a window signal WO is provided.
The count is started just before turning on, and it is decoded to generate a reproduced Vsync signal.

Thus, even if the counter 35a changes the maximum count value in accordance with the length of the cycle of the Vsync signal, the reproduced Vsync signal will be exactly 520-52 from the time when the counter 35a was previously initialized.
It is output at the position of 5H (in the section of the count value -5 to -1). In this example, the period of the vertical synchronization signal is short and the counter 35a
Is initialized when the count value reaches -20,
The reproduced Vsync signal output by decoding the count value of the counter 37a is output at an accurate cycle.

The section shown in Fig. 12 (1) has a long cycle (for example, 535H).
This is a section where the Vsync signal is supplied. in this case,
Even if the count value of the counter 35a reaches -1 (maximum value), V
Since the init signal is not input, the counter is initialized by the carry output CO1 signal output by the counter itself shown in FIG. At the same time, the window signal WO is turned off as shown in FIG. 12 (d), but the RS flip-flop 35e is set by the CO1 signal, and the window signal W1 is turned on as shown in FIG. 12 (e). Is Fig. 12 (h)
And the AND circuit 36a is set to Vinit
It will be in a signal waiting state.

In this example, 535H (count value is -51 after carry output)
The Vinit signal is input to 5), the counter 35a is initialized again, the RS flip-flop 35e is reset, and the Vwdw signal is turned off. Thus, when the cycle of the Vsync signal is long, the counter 35a is initialized twice for a short period as shown in FIG. 12 (g).

At time t8 in FIG. 12 (c), a malfunction occurs due to the weak electric field, and an invalid Vinit signal is generated. At this time, since the Vwdw signal is not generated, this Vinit signal is LD1.
Does not output a signal. Therefore, the counter 35a detects V
It is not initialized by the init signal.

The section of FIG. 12 (l) shows a free-run state. At this time, since the input of the Vinit signal is interrupted,
The counter 35a keeps operating while repeating initialization by itself using the carry output CO1. Vwdw signal is Vinit
It turns on until a signal is input. Even in this case, the reproduced Vsync signal generated by the counter 37a is output at a correct cycle, and stable operation is guaranteed.

[Effects of the Invention] As described above, the synchronization signal reproducing circuit according to the present invention converts two types of clock signals, which are phase-synchronized with the external horizontal synchronization signal and are 180 degrees out of phase from each other, into the phase fluctuation state of the external vertical synchronization signal. , And the counter initialization signal is generated based on the selected signal, so that there is an effect that a reproduced vertical synchronization signal with less influence of jitter can be obtained. In addition, since the detection result of the phase of the external vertical synchronization signal is provided with hysteresis, it is possible to cope with a local change in the tendency of jitter.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a synchronization signal reproducing circuit of the present invention, FIG. 2 is a block diagram showing a configuration of an example of a device to which a countdown circuit of the present invention is applied,
FIG. 3 is a block diagram showing a detailed configuration of the jitter removing unit in FIG. 1, FIG. 4 is a timing chart of a signal waveform generated by the timing generating unit in FIG. 3, and FIGS.
9 is a timing chart showing various operation states of the circuit of FIG. 3, FIG. 9 is a state transition diagram for explaining the operation state of the circuit of FIG. 3, and FIG. 10 is a state where the operation state of the circuit of FIG. 3 changes. Is a diagram showing the relationship with the count value of the counter,
FIG. 11 is a block diagram showing a detailed configuration of the countdown unit, FIG. 12 is a timing chart showing the operation of the circuit of FIG. 11, and FIG. 13 is a diagram for explaining a state where jitter occurs in the vertical synchronization signal. It is. 31 timing generator, 31e, 35f, 37c decoder, 3
2 Falling edge phase determination section, 32c, 35a, 37a Counter, 33 Clock switching section, 34 Differentiator section, 35 Window timing generation section, 36 Window processing section,
37 …… Vsync generator.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N ^5/ 04-5/12

Claims (1)

(57) [Claims] A synchronous signal reproducing circuit for reproducing a reproduced vertical synchronizing signal corresponding to a count value of a counting section initialized by a counter initializing signal generated based on an external horizontal synchronizing signal and an external vertical synchronizing signal. External vertical synchronizing signal phase detecting means for detecting whether or not the generation timing of the change point of the external vertical synchronizing signal is near or in between the generation timing of the external horizontal synchronizing signal, and the external horizontal synchronizing signal Clock generating means for generating two-phase clock signals having phases different from each other by 180 degrees synchronized with each other; and clock selection for selecting one of the two-phase clock signals in accordance with a detection result of the external vertical synchronizing signal phase detecting means. Means for detecting a change point of the external vertical synchronizing signal with the selected clock signal, and the count initialization signal corresponding to the change point. The clock selection means has hysteresis means for giving a hysteresis to the detection result of the external vertical synchronization signal phase detection means, and the clock selection means corresponds to an output of the hysteresis means. A synchronous signal reproducing circuit for selecting a clock signal.