JP3042468B2 - Semiconductor device bonding method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bonding method for a semiconductor device, and more particularly, to a chip size package (CSP) having the same size as a semiconductor chip.
ege) is preferably used in the manufacturing process, and a semiconductor chip and a TAB (Tape Automated Bo
The present invention relates to a bonding method of a semiconductor device for electrically connecting a tape for nding).

[0002]

2. Description of the Related Art In recent years, new types of semiconductor devices have been developed one after another in order to respond to the demands of electronic devices that are smaller, lighter, faster and more sophisticated. In addition, the demand for more pins due to higher integration of semiconductor chips and for smaller and thinner semiconductor devices are becoming more stringent. In order to make these both compatible, it is inevitable to reduce the pad pitch of the Al electrodes of the semiconductor chip.

At present, wire bonding is mainly used for electrical connection between a semiconductor chip and leads, that is, so-called inner lead connection. TA that can respond to narrow pad pitch
The B method is receiving attention. In this TAB connection method, an inner lead of a gold layer foil is formed on an insulating polyimide film by etching, and this inner lead is bonded to an aluminum (Al) electrode pad of a semiconductor chip. This is a system that has advantages.

[0004] Further, recently, miniaturization and high density have been realized, for example, in Japanese Patent Application Laid-Open No. 7-32157.
There is a semiconductor device disclosed in Japanese Patent Application Laid-Open No. Hei 6-110857. This semiconductor device includes a semiconductor chip having an Al electrode pad on its surface as a small BGA,
A wiring layer is formed on the front surface, conductive protrusions (inner bumps) are formed on the back surface, and the wiring layer and the protrusions are connected to the electrodes via through holes formed in the insulating polyimide film. A TAB tape;
The projection of the tape is electrically connected to the Al electrode of the semiconductor chip.

Generally, such a package is a chip size package having substantially the same size as a semiconductor chip to be mounted. Here, a single point bonding method (inner lead bonding) of sequentially bonding inner leads of a TAB tape and Al electrode pads of a semiconductor chip, which is a conventional general bonding method, will be described.

FIG. 3 is a process diagram showing a conventional single point bonding method, and FIG. 4 is an enlarged sectional view of a region A in FIG. 3, where 1 is a semiconductor chip and 2 is electrically connected to the semiconductor chip 1. The connected TAB tape 3 is a bonding stage which incorporates a heater (not shown) and heats the mounted semiconductor chip 1 to a predetermined temperature, and 4 is a bonding tool of an ultrasonic combined heat weight application bonding method. The semiconductor chip 1 has an Al electrode pad 11 at a predetermined position on the upper surface.
Is formed, and a chip cover 12 made of polyimide is formed on the entire surface except for the Al electrode pads 11 on the upper surface.

The TAB tape 2 has device holes 14 formed at predetermined positions on an insulating polyimide tape 13, and copper (Cu) is formed on the upper surface of the polyimide tape 13.
The foil wiring pattern 15 is formed by etching, and the inner lead 15a, which is a part of the Cu foil wiring pattern 15, protrudes toward the center of the device hole. Further, a cover coat 16 is applied on the Cu foil wiring pattern 15.

Next, the single point bonding method will be described. First, each of the Al electrode pads 11 of the semiconductor chip 1 and these Al electrode pads 1
1 each inner lead 1 of TAB tape 2 corresponding to each
5a is positioned while maintaining a constant interval (hereinafter referred to as bonding height) in the vertical direction (FIG. 3A).
Next, the inner lead 15a of the TAB tape 2 and the Al electrode pad 11 of the semiconductor chip 1 are successively joined by the bonding tool 4 (FIG. 3B).

Here, the bonding tool 4 is made of Al
An electrode pad having a diameter smaller than that of the Al electrode pad 11 is used so that the contact between the electrode pad 11 and the inner lead 15a is sufficient. The bonding stage 3 is heated to about 280 ° C. At this time, since the bonding stage 3 is at a high temperature (280 ° C.), as shown in FIG.
Are thermally expanded in the direction of arrow E in FIG. 4, and the inner leads 15a are bonded in a state of extending to the center of the device hole 14. However, when the bonding stage 3 is separated after bonding is completed, the inner leads 15a are cooled in the opposite direction and are cooled in the direction indicated by the arrow in FIG. It contracts in the direction of S.

FIG. 5 shows a conventional CSP single-point bonding method using a TAB tape having a structure in which a wiring layer and inner bumps are connected by through holes (inne bonding method).
FIG. 6 is an enlarged cross-sectional view of a region B in FIG. 5, in which 21 is a semiconductor chip 1.
The TAB tape 22 electrically connected to the bonding tool 22 is a bonding tool of an ultrasonic combined heat weight application type.

The TAB tape 21 has a Cu foil wiring pattern 15 formed on the upper surface of the insulating polyimide tape 13 by etching, and a cover coat 16 is applied on the Cu foil wiring pattern 15. An adhesive tape 23 for sealing with the upper surface of the semiconductor chip 1 is attached to the lower surface of the polyimide tape 13. Then, through holes 24 are formed in the polyimide tape 13 and the adhesive tape 23 at positions corresponding to the Al electrode pads 11 of the semiconductor chip 1.

An inner bump (projection) 25 formed by growing and filling a metal material by electrolytic plating or the like is formed in the through hole 24 to connect to the wiring pattern 15. On the other hand, holes 26 having a larger diameter than the inner bumps 25 are formed in the cover coat 16 at positions corresponding to the inner bumps 25.

Next, the single point bonding method of the CSP will be described. First, the semiconductor chip 1
The respective Al electrode pads 11 and the inner bumps 25 of the TAB tape 21 corresponding to the respective Al electrode pads 11 are positioned while maintaining the bonding height in the vertical direction (FIG. 5A). Next, the bonding stage 3 is raised to bring the respective Al electrode pads 11 of the semiconductor chip 1 into contact with the respective inner bumps 25 of the TAB tape 21, and the inner bumps 25 of the TAB tape 21 and the semiconductor chip 1 are bonded by the bonding tool 22. (FIG. 5)
(B)).

The bonding height at the time of bonding is such that the lower surface of the adhesive tape 23 and the upper surface of the chip cover 12 on the upper surface of the semiconductor chip 1 are in contact with each other. The bonding tool 22 has a tip that has a diameter substantially equal to or smaller than that of the inner bump 25 so that the contact between the Al electrode pad 11 and the inner bump 25 is sufficient. The bonding stage 3 is heated to about 300 ° C.

[0015]

In the conventional single-point bonding method for sequentially bonding inner leads and electrode pads, the single-point bonding method is overwhelming in comparison with the thermal expansion of the polyimide tape 13 due to the high temperature atmosphere during bonding and the shrinkage due to cooling after bonding. Long inner lead 15a
Are the Al electrode pads 11 of the semiconductor chip 1 which is the bonding portion.
The stress between the semiconductor chip 1 and the polyimide tape 13 due to the difference in expansion coefficient between the semiconductor chip 1 and the polyimide tape 13 is dispersed and absorbed by the inner lead 15a being bent.

However, in the single point bonding method of the CSP, as shown in FIGS. 6 and 7, the polyimide tape 13 and the Al electrode pad 11 of the semiconductor chip 1 which is the bonding portion are bonded only by the inner bump 25. Therefore, the bonding region C is equal to the metal bonding region M to which the inner bump 25 is bonded, and the difference in the expansion coefficient cannot be absorbed and dispersed, so that the stress is directly applied to the A1 electrode 11 as the bonding portion.

In general, the coefficient of thermal expansion of the adhesive tape 23 is higher than the coefficient of thermal expansion of the polyimide tape 13. Therefore, as shown in FIG. 8, the unit area due to the thermal expansion / cooling shrinkage of the polyimide tape 13 is determined from the adhesion strength σ1 per unit area between the Al electrode pad 11 of the semiconductor chip 1 and the interlayer film 28 below the Al electrode pad 11. When the stress ρ per contact is large (ρ> σ1), the thermal expansion and cooling contraction of the polyimide tape 13 causes the Al electrode pad 1
There is a problem in that a problem such as 1 being peeled off from the interlayer film 28 is caused.

When the response ρ due to thermal expansion and cooling contraction of the polyimide tape 13 is larger than the bonding force σ 2 per unit area of silicon (Si) crystal, which is the main material of the semiconductor chip 1 (ρ> σ 2), Si There is also a problem that the crystal itself is destroyed.

The present invention has been made in view of the above circumstances, and is provided on a semiconductor chip even when a flexible wiring board is subjected to stress due to its thermal expansion and cooling contraction. It is an object of the present invention to provide a bonding method capable of preventing peeling of a pad and destruction of a Si crystal which is a main material of a semiconductor chip.

[0020]

In order to solve the above-mentioned problems, the present invention provides the following semiconductor device bonding method. That is, by bonding the electrodes of the semiconductor chip and the bumps formed in the through holes of the flexible wiring board by bonding, the electrodes of the semiconductor chip and the bumps of the wiring board are simultaneously bonded, This is a method of joining the periphery and the periphery of the bump.

The periphery of the electrode of the semiconductor chip is covered with a first resin, the periphery of the bump of the wiring board is covered with a second resin, and the first resin and the second resin are joined. Is also good. Further, the wiring board may be a TAB tape, and the second resin may be an adhesive tape.

Further, the bonding between the electrodes of the semiconductor chip and the bumps of the wiring board and the bonding between the periphery of the electrodes and the periphery of the bumps are performed by using a bonding tool of an ultrasonic combined heat weight application bonding system. You may. The area of the tip of the bonding tool that contacts the wiring board may be larger than the area of the electrodes of the semiconductor chip.

In the method for bonding a semiconductor device according to the present invention, the semiconductor chip and the wiring board are joined together by joining the electrodes of the semiconductor chip and the bumps of the wiring board and simultaneously joining the periphery of the electrodes and the periphery of the bumps. Is the sum of the bonding area between the electrode of the semiconductor chip and the bump of the wiring board plus the surrounding bonding area, and the bonding area is greatly increased. As a result, the stress due to the thermal expansion / cooling shrinkage of the wiring board is applied to both the bonding area between the electrode of the semiconductor chip and the bump of the wiring board and the bonding area around them, and the stress is applied to the entire bonding area. Widely dispersed, the stress ρ per unit area is reduced, and the separation of the pads of the semiconductor chip and the Si which is the main material of the semiconductor chip
Prevents crystal destruction.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a bonding method for a semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view illustrating a bonding method according to an embodiment of the present invention, and FIG. 2 is a plan view illustrating a bonding region. In the drawing, reference numeral 31 denotes a bonding tool of a heat weight application bonding method using ultrasonic waves. The semiconductor chip 1 has an Al electrode pad 11 formed at a predetermined position on the upper surface, and a chip cover (first resin) 12 made of polyimide is formed on the entire surface of the upper surface except for the Al electrode pad 11.

TAB tape (flexible wiring board) 2
Numeral 1 denotes a CSP TAB tape having a through-hole structure. A Cu foil wiring pattern 15 is formed on the upper surface of an insulating polyimide tape 13 by etching, and a cover coat 16 is formed on the Cu foil wiring pattern 15. An adhesive tape 23 for sealing with the upper surface of the semiconductor chip 1 is attached to the lower surface of the polyimide tape 13. Then, through holes 24 are formed in the polyimide tape 13 and the adhesive tape 23 at positions corresponding to the Al electrode pads 11 of the semiconductor chip 1.

In the through hole 24, an inner bump 25 formed by growing and filling a metal substance by electrolytic plating or the like is formed for connection with the wiring pattern 15.
On the other hand, the cover coat 16 has a hole 2 having a diameter larger than that of the inner bump 25 corresponding to the position of the inner bump 25.
6 are formed. The area of the tip 31 a of the bonding tool 31 that contacts the Cu foil wiring pattern 15 is larger than the area of the Al electrode pad 11 of the semiconductor chip 1.

Next, this bonding method will be described. First, the Al electrode pad 11 of the semiconductor chip 1
The inner bumps 25 of the TAB tape 21 corresponding to the Al electrode pads 11 are positioned while maintaining the bonding height in the vertical direction, and the bonding stage 3 is raised so that the Al electrode pads 11 of the semiconductor chip 1 are
The inner bump 25 of the B tape 21 is brought into contact.

Then, the Al electrode pad 11 of the semiconductor chip 1 and the TAB tape 2 are
At the same time as bonding the first inner bump 25, the chip cover 12a around the Al electrode pad 11 and the adhesive tape 23a around the inner bump 25 are bonded. In this case, the energy of ultrasonic waves, weight, and heat during bonding is also applied to the periphery of the inner bump 25, and the adhesive tape 23a on the lower surface of the polyimide tape 13 and the chip cover 12a on the upper surface of the semiconductor chip 1 are bonded and bonded. I do.

For this reason, the stress ρ due to the thermal expansion / cooling shrinkage of the TAB tape 21 is applied to the entire bonding region C ′ including the metal bonding region M and the adhesive bonding region R. Therefore, when the stress ρ is applied to the entire bonding region C ′, the stress ρ is dispersed, and the stress ρ ′ per unit area is increased by the adhesion strength σ1 between the Al electrode pad 11 and the interlayer film 28 and the semiconductor chip 1. Can be made smaller than the bonding force σ2 of the Si crystal which is the main material of (ρ ′ <σ1,
ρ ′ <σ2), the Al electrode pad 11 peels off,
Problems such as breakage of crystals are eliminated.

According to the bonding method of this embodiment,
The bonding tool 31 allows the Al of the semiconductor chip 1
Since the electrode pads 11 and the inner bumps 25 of the TAB tape 21 are joined together, the chip cover 12a around the Al electrode pads 11 and the adhesive tape 23a around the inner bumps 25 are joined together.
Problems such as peeling of the electrode pad 11 and destruction of the Si crystal as the main material of the semiconductor chip 1 can be prevented. Therefore, a semiconductor device having a highly reliable electrical junction can be obtained.

[0031]

As described above, according to the method of bonding a semiconductor device of the present invention, an electrode of a semiconductor chip is bonded to a bump of a wiring board, and simultaneously, a periphery of the electrode is bonded to a periphery of the bump. Therefore, the bonding area between the semiconductor chip and the wiring board can be greatly increased, and the stress due to thermal expansion / cooling contraction of the wiring board can be widely distributed over the entire bonding area to reduce the stress per unit area. . Therefore, peeling of the pads of the semiconductor chip and destruction of the Si crystal, which is the main material of the semiconductor chip, can be prevented, and a semiconductor device having highly reliable electrical bonding can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a bonding method according to an embodiment of the present invention.

FIG. 2 is a plan view showing a bonding region of a bonding method according to one embodiment of the present invention.

FIG. 3 is a process diagram showing a conventional single point bonding method.

FIG. 4 is an enlarged sectional view of a region A in FIG. 3;

FIG. 5 is a process diagram illustrating a conventional CSP single-point voiding method.

FIG. 6 is an enlarged sectional view of a region B in FIG. 5;

FIG. 7 is a plan view showing a bonding region in a conventional CSP single point bonding method.

FIG. 8 is a cross-sectional view showing a problem of a conventional CSP single point bonding method.

[Explanation of symbols]

 Reference Signs List 1 semiconductor chip 2 TAB tape 3 bonding stage 4 bonding tool 11 Al electrode pad 12 chip cover (first resin) 13 polyimide tape 14 device hole 15 Cu foil wiring pattern 15a inner lead 16 cover coat 21 TAB tape (has flexibility) 22 Wiring board 22 Bonding tool 23 Adhesive tape 24 Through hole 25 Inner bump (protrusion) 26 Hole 31 Bonding tool 31a Tip C Bonding area C 'Bonding area E Direction of thermal expansion M Metal bonding area R Adhesive bonding area S Shrinkage Direction

Claims (5)

(57) [Claims] 1. A bonding method for a semiconductor device, wherein an electrode of a semiconductor chip is bonded to a bump formed in a through hole of a flexible wiring board by bonding, wherein the electrode of the semiconductor chip and the bump of the wiring board are bonded. And bonding the periphery of the electrode and the periphery of the bump at the same time. 2. A method according to claim 1, wherein a periphery of the electrode of the semiconductor chip is covered with a first resin, a periphery of a bump of the wiring board is covered with a second resin, and the first resin and the second resin are joined. 2. The bonding method for a semiconductor device according to claim 1, wherein the bonding is performed. 3. A bonding method for a semiconductor device according to claim 2, wherein said wiring board is a TAB tape, and said second resin is a tape adhesive. 4. The bonding between the electrodes of the semiconductor chip and the bumps of the wiring board and the bonding between the periphery of the electrodes and the periphery of the bumps are performed using a bonding tool of an ultrasonic combined heat weight application bonding system. 2. The method according to claim 1, wherein
The bonding method of the semiconductor device according to the above. 5. The bonding method for a semiconductor device according to claim 4, wherein an area of a tip portion of said bonding tool in contact with said wiring board is larger than an area of an electrode of said semiconductor chip.