JP3047260B2 - Semiconductor laser driver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor laser driving apparatus, and more particularly, to a pulse width modulation technique in an apparatus for exposing and scanning a photosensitive material by pulse width modulating a semiconductor laser beam according to an input image signal. .

[0002]

2. Description of the Related Art Conventionally, a laser beam generated by a semiconductor laser (laser diode; LD) is intensity-modulated by an externally provided optical modulator to expose and scan a photosensitive material.
A laser printer or the like configured to obtain a gradation image is known, but the light output of the semiconductor laser is controlled by directly controlling a current value supplied to the semiconductor laser without using the external modulator, and a photosensitive material is provided. As a method of obtaining an image having continuous tones on the upper side, there are the following methods.

[0003] Since a semiconductor laser has a certain characteristic between a supplied current value and a generated optical output, if the current value is controlled by the required gradation, the optical output can be directly performed without using an external modulator. For example, in order to obtain 256 gradations, it suffices if the current can be decomposed into 256 steps (JP-A-2-175265, JP-A-63-184).
460, etc.).

[0004] In addition, continuous current can be obtained without using an external modulator, by making the current supplied to the semiconductor laser constant and keeping the optical output constant, and modulating the pulse width of the supplied current according to the image signal. For example, as disclosed in Japanese Unexamined Patent Publication No. Hei 3-16190, 256 modulation pulse widths corresponding to an 8-bit digital input image signal define a period of original oscillation of 20 ns and a recording time per pixel. When the period of the dot clock is 320 ns and this is used as the reference dot clock, the dot clock can be obtained as follows.

First, a first pulse width (20 to 320 ns) corresponding to the upper 4 bits of an 8-bit digital input image signal
Can be obtained as 16 pulse widths at intervals of 20 ns by counting one cycle of the original oscillation from 0 to 15. The second pulse width (1.25 to 20 ns) corresponding to the lower 4 bits of the digital input image signal is obtained by obtaining one cycle of the original oscillation as 16 pulse widths in 1.25 ns intervals using a delay line. Can be.

By synthesizing the first and second pulse widths obtained as described above with a pulse width synthesizing circuit, 256 modulation pulse widths corresponding to an 8-bit digital input image signal can be obtained. By supplying a current pulse (drive pulse signal) of the modulation pulse width to the semiconductor laser in synchronization with the dot clock and exposing and scanning the photosensitive material,
This means that each pixel can be reproduced at 256 levels.

In this case, the dot clock is one cycle of the original oscillation which is the same as that used to obtain the modulation pulse width.
It is obtained by dividing ns with a counter. Therefore, by setting the count number arbitrarily, it is possible to change the dot clock cycle in units of 20 ns.
A period reference dot clock can be obtained by counting one cycle of the original oscillation by 16 (divided by 16).
For example, a dock clock having a cycle of 340 ns can be obtained by setting the count number to 17, and a dot clock having a cycle of 300 ns can be obtained by setting the count number to 15.

[0008]

By the way, in a laser printer capable of performing multi-color recording using laser light of a plurality of wavelengths such as red, green, and blue, the refractive index of an imaging lens (fθ lens) depends on the wavelength. Because of the difference, there is a problem that chromatic aberration occurs.
It is disclosed in Japanese Patent Application Publication No. 3-148275. In this method, a dot position (beam position) is moved in a direction in which aberration is canceled by changing a period of a dot clock.

However, this technique is disclosed in Japanese Patent Laid-Open No. 3-16 / 1991.
When applied to the pulse width modulation by the method disclosed in Japanese Patent Publication No. 190, there is a fear that the image quality is reduced. The reason will be described below. For example, in pulse width modulation of semiconductor laser light based on a 320 ns period reference dot clock,
If a modulation pulse width of 20 ns is set, the dot clock cycle
The duty ratio of the modulation pulse width to 320 ns is 1/16. On the other hand, the dot clock cycle starts from 320ns
When the duty ratio changes to 300 ns, the duty ratio becomes 1/15, and also changes to 1/17 in the 340 ns cycle (see FIG. 12).

In general, the exposure energy of a pulse width modulated laser beam is proportional to the duty ratio. Therefore,
If the period of the dot clock is changed in order to correct the beam position while the modulation pulse width is constant, the duty of the modulation pulse width obtained as described above changes. Become. The present invention has been made in view of the above problems, and in pulse width modulation of a semiconductor laser, the duty ratio of the modulation pulse width is constant even if the period of the dot clock changes for the same input image signal. An object of the present invention is to provide a semiconductor laser driving device capable of performing accurate gradation expression by controlling.

[0011]

Therefore, a semiconductor laser driving device according to the present invention is a device for pulse width modulating a semiconductor laser beam in accordance with an input image signal, and is configured as shown in FIG. In FIG. 1, a dot clock generating means selectively generates a plurality of dot clocks having mutually different periods as dot clocks defining a recording time per pixel.

On the other hand, based on the period of the dot clock generated by the dot clock generating unit, the input image signal converting means converts the duty ratio of the modulation pulse width obtained for the input image signal to the dot clock cycle into the input image signal. The input image signal is converted so as to have a fixed relationship with respect to the input image signal. Then, the drive pulse signal generation means generates a semiconductor laser drive pulse signal having a pulse width corresponding to the signal converted by the input image signal conversion means with reference to the dot clock.

Here, it is preferable that the input image signal converting means converts the input image signal based on a ratio of a cycle of the dot clock generated by the dot clock generating means to a cycle of the reference dot clock. Further, the driving pulse signal generating means may include the following means indicated by a dotted line in FIG.

Here, the counting means counts the signal value converted by the input image signal converting means in synchronization with a fixed unit pulse signal. The pulse width setting means sets the pulse width of the semiconductor laser drive pulse signal based on the start and end of counting by the counting means. On the other hand, the delay means delays the end of counting by the counting means by a predetermined integer multiple of the cycle of the unit pulse signal when the input image signal exceeds a predetermined value.

[0015]

In the case where the period of the dot clock changes to a plurality of types, if the same modulation pulse width (pulse width of the driving signal) is given to a predetermined input image signal regardless of the period, the modulation pulse with respect to the dot clock period is obtained. The duty ratio of the width changes for the same input image signal. Therefore,
Even if the period of the dot clock changes, the input image signal is converted in accordance with the dot clock period so that the duty ratio obtained for the input image signal is constant, and a pulse is generated based on the converted signal. Width modulation was performed.

Here, if the input image signal is converted based on the ratio of the period of the actual dot clock to the period of the reference dot clock, the relationship between the duty ratio with respect to the input image signal and that of the reference dot clock can be obtained. Can be made to match. Further, in the configuration in which the converted signal value is counted in synchronization with a fixed unit pulse signal, and a modulation pulse width corresponding to the converted signal value is obtained based on the start and end of the counting, Is terminated by a predetermined integer multiple of the period of the unit pulse signal when the input image signal exceeds a predetermined value, whereby the maximum count number in the counting means when the input image signal exceeds the predetermined value A pulse width longer than the pulse width corresponding to the delay time by the delay time can be obtained.

[0017]

Embodiments of the present invention will be described below. The semiconductor laser driving device according to this embodiment is a semiconductor laser driving device applied to a laser printer or the like for obtaining a gradation image by exposing and scanning a semiconductor material on a photosensitive material. It is configured to perform pulse width modulation according to an input image signal. Here, the input image signal is 8
The original oscillation CLK for obtaining a dot clock PX which is a bit digital signal and defines the modulation pulse width and the recording time of one pixel is 50 MHz (20 ns cycle).

The hardware configuration of the first embodiment will be described with reference to FIG. A conversion table selection signal is input to a conversion table 1 as input image signal conversion means together with a digital input image signal. Further, the conversion table 1 includes a reference dot clock PX1 (320 ns cycle),
Two conversion tables LUT1 and LUT2 respectively corresponding to the dot clock PX2 (300 ns cycle) are preset, and one of the conversion tables LUT1 and LUT2 is selected according to a conversion table selection signal, and the selected conversion table is selected. Using the tables LUT1 and LUT2, an 8-bit digital input image signal is converted into an 8-bit image signal.

The conversion table 1 includes, for example, EP
Using a ROM, data conversion is performed by using an address as input data and a value designated by the address as output data. The dot clock generator 2 as a dot clock generating means is composed of a hexadecimal up counter, and by setting the count number of the original oscillation CLK to 15 or 16 in accordance with the input dot clock selection signal, a dot clock of 300 ns cycle PX2 and a reference dot clock PX1 having a period of 320 ns are selectively generated.

The 8-bit signal converted by the conversion table 1 is divided into upper 4 bits and lower 4 bits.
The upper 4 bits are input to the first pulse width generation circuit 3,
Sixteen first pulse widths corresponding to the upper four bits are output, and the lower four bits are input to the second pulse width generation circuit 4 to output sixteen second pulse widths corresponding to the lower four bits. .

The first pulse width and the second pulse width are input to the pulse width synthesizing circuit 5 and synthesized to obtain 16 × 16 = 256 kinds of modulation pulse widths. Is supplied to a semiconductor laser (not shown) to modulate the pulse width of the semiconductor laser light. The first pulse width generating circuit 3, the second pulse width generating circuit 4, and the pulse width synthesizing circuit 5 constitute a driving pulse signal generating means in this embodiment.

The first pulse width generating circuit 3 comprises a frequency divider 6 as a counting means, a load signal generating circuit 7, and a first pulse width generator 8 as a pulse width setting means. The frequency divider 6 is composed of a hexadecimal down counter, and the upper four bits of the 8-bit signal converted by the conversion table 1 are input to a load input terminal thereof.
A load signal L generated by a load signal generation circuit 7 described later.
By D, the value is loaded into the frequency divider 6 and counted down at 50 MHz. When the hexadecimal down counter finishes counting, the carry signal CARRY
Generate.

The load signal generating circuit 7 is a D flip-flop (DF / F) that changes at the rise of the original oscillation CLK.
7a and an AND circuit (AND circuit) 7b. Here, the logical product of the inverted output of the signal PX 'obtained by delaying the dot clock PX generated by the dot clock generator 2 by one pulse (20 ns) of the original oscillation by the DF / F 7a and the dot clock PX is obtained. Thus, a load signal LD which rises in synchronization with the rise of the dot clock PX is output.

The first pulse width generator 8 has the original oscillation CLK
JK flip-flop (J
KF / F), a carry signal CARRY from the frequency divider (hexadecimal down counter) 6 is input to a J input terminal (set terminal) of the J · KF / F, and a K input terminal The (reset terminal) receives the load signal LD from the load signal generation circuit 7, rises in synchronization with the fall of the load signal LD, and synchronizes with the fall of the carry signal CARRY. A first pulse width corresponding to the upper 4 bits of the falling input image signal is generated (see FIG. 3).

On the other hand, the second pulse width generating circuit 4 is also constituted by substantially the same components as the first pulse width generating circuit 3, and detailed description is omitted in this embodiment. 3 uses the original oscillation CLK as a unit pulse signal and counts the unit pulse signal, so that every 20 ns
While the 16 first pulse widths are generated, the second pulse width generation circuit 4 generates one pulse 20 of the original oscillation CLK.
ns is divided into 16 by using a delay line, and 16 second pulse widths are obtained at intervals of 1.25 ns based on a unit pulse signal having a pulse width of 1.25 ns obtained by dividing the ns into 16, The operation of starting the count in synchronization with the dot clock PX and setting the second pulse width based on the count start and end is performed by the first pulse width generation circuit 3.
Shall be performed in the same manner.

Next, conversion table 1 which is a feature of the present invention is described.
Image signal conversion using (input image signal conversion means) will be described in detail. In this embodiment, since the minimum unit pulse width for incrementing the modulation pulse width is set to 1.25 ns (20 ns / 16) based on the original oscillation CLK 50 MHz, the reference dot clock PX1 and the dot clock PX2 are set to the minimum unit pulse width. , The pulse widths correspond to 256 and 240 gradation levels, respectively. That is, in the reference dot clock PX1, 256 modulation pulse widths can be given by changing the pulse width in steps of 1.25 ns, so that the conversion table LUT1 outputs the input image signal as it is. Configuration is good. still,
Since the LUT 1 does not perform data conversion, when the PX 1 is selected as the dot clock, the input image signal is directly input to the first and second pulse width generation circuits without passing through the conversion table 1. Is also good.

On the other hand, when the dot clock PX2 having a shorter cycle than the reference cycle is used, if the input image signal is used without conversion, the modulation pulse width is given to the image signals of 0 to 239 at intervals of 1.25 ns. Therefore, the exposure energy, which is proportional to the duty ratio of the modulation pulse width to the dot clock cycle, changes more than in the case of the reference dot clock PX1 (see FIG. 4).

Therefore, even when the dot clock PX2 is used, the input image signal is converted by the conversion table LUT2 so that the duty ratio of the modulation pulse width obtained for the input image signal to the dot clock period is constant. Convert. As shown in FIG. 4, the exposure energy obtained for each input image signal has a normal value controlled by the reference dot clock PX1. For example, the input image signal d1
The exposure energy obtained by the reference dot clock P
Assuming a value p1 when X1 is used, the dot clock P
P2 when X2 is used becomes larger than p1 due to an increase in the duty ratio. Here, the dot clock P
When X2 is used, the signal at which the exposure energy becomes P1 is d2. Therefore, if the input image signal is d1 and this signal is converted to d2, the duty ratio at that time matches the case where the reference dot clock PX1 is used.

However, in this embodiment, since the signal to be handled is digital, it is actually set so as to be converted into an integer value close to d2. Specifically, FIG.
As shown in the figure, 256 kinds of input image signals from 0 to 255 are reduced to 240 to 0 to 239 by reducing the number of quantization steps.
If the image signal is converted into the same image signal, substantially the same gradation (duty ratio) as when the reference dot clock PX1 is used can be obtained even when the dot clock PX2 is used.

In the signal conversion characteristics shown in FIG. 5, when no conversion is performed using the reference dot clock PX1, the gradient (converted image signal / input image signal) is 1 while the dot clock PX2 is not converted. The conversion corresponding to
The inclination is 300 ns of the period of the dot clock PX2 / 320 ns of the period of the reference dot clock PX1 = 0.9375. Therefore, the input image signal is denoted by di (n), and the converted image signal is denoted by do.
(n), do (n) = 0.9375 × di (n) (n = 0-25
5) By performing the following calculation, conversion for making the exposure energy (duty ratio) constant can be performed.

However, since the input image signal di (n) and the converted image signal do (n) are digital values, the above operation is performed in advance to round down or round up the value after the decimal point. The conversion digital signal do (n) corresponding to the digital input image signal di (n) is set, and the conversion table LUT2 is determined based on the setting result.
In the conversion table LUT2, do (0) =
0, do (255) = 239.

FIG. 6 shows the conversion table LUT2 of the input image signal when the dot clock PX2 is used. In FIG. 6, a normal is a reference dot clock PX1 that outputs an input image signal as it is as a converted output.
The conversion output in the non-conversion table LUT1 for
When the reference dot clock PX1 is used, this normal signal is output for the input image signal.

The calculated values in FIG. 6 have nothing to do with the actual conversion, but are shown to explain how the conversion table is set, and the above-mentioned do (n) = 0.93
This is the calculation result of 75 × di (n). The calculated value is rounded off to the first decimal place. When the dot clock PX2 is used, the converted value is used to convert the input image signal into this converted value and output the converted value. The signals are converted to outputs 0-239. The reduction in the number of signals as described above is realized by assigning the same output signal to two adjacent input image signals in a hatched portion surrounded by a dotted line in FIG. By dispersing and setting the portions to be applied to 16 locations substantially uniformly, conversion that reduces the number of signals by 16 can be performed.

If the modulation pulse width is generated based on the value converted by the conversion table LUT2 as described above, the reference dot clock PX1 (320 ns) can be used even when the dot clock PX2 (300 ns) is used. Exposure energy approximately the same as when used can be obtained, and even if the period of the dot clock PX is changed, the exposure energy obtained for the input image signal can be kept constant and the image quality can be improved. .

In the above embodiment, the input image signal is 256
Since the gradation is a gradation, a dot clock with a period of 320 ns which can be decomposed into 256 gradations is used as a reference. However, a dot clock PX having three periods of 320 ns, 300 ns, and 280 ns is generated. The dot clock P having a longer period of 320 ns using the dot clock PX of
By properly using X and a shorter dot clock PX having a cycle of 280 ns, it is possible to perform correction to shift the beam position forward or backward with respect to a standard beam position using a dot clock PX having a cycle of 300 ns. .

In such a configuration, when a standard dot clock having a cycle of 300 ns or a shorter dot clock having a cycle of 280 ns is used, conversion for reducing the input image signal value di (n) (0-255 → 0-239, 280 ns at 300 ns) 0-255 → 0-223), and the converted image signal value do (n) in the dot clock having the 280 ns cycle.
Is calculated by the conversion formula do (n) = di (n) × (280 ns / 320 ns) (where n = 0 to 255), and an integer value close to this is renewed and the conversion table is set as do (n). However, when the reference is set to 300 ns, the standard gradation number is reduced as compared with the case where the reference is set to 320 ns, so that the image quality is slightly reduced.

In the above embodiment, the dot clock PX2 having a shorter period than the reference dot clock PX1 having a period of 320 ns is generated. However, the dot clock PX3 having a period longer than the reference dot clock PX1 is generated. The second embodiment will be described below. For example, longer than the reference dot clock PX1 having a period of 320 ns
If the dot clock PX3 having a period of 340 ns is generated, the minimum unit pulse width based on the original oscillation CLK is 1.25 ns.
1.25 within the period of the dot clock PX3.
272 pulse widths can be obtained every ns. However, since the input image signal is 8 bits and has 256 gradations, it is not possible to obtain the above-mentioned 272 pulse widths by using the input image signal as it is. Therefore, contrary to the above-described first embodiment, it is necessary to cause the conversion table 1 to perform a conversion for increasing the signal value from 256 to 272. Since the maximum count number in the frequency divider 6 is 16, As described above, the result of performing the conversion for increasing the signal value cannot be counted as it is.

That is, in the configuration of the first embodiment shown in FIG.
The first pulse width can be changed only within the range of 320 ns. When the dot clock PX3 having a period of 340 ns is used, the duty ratio of the modulation pulse width corresponding to the input image signal to the dot clock period is made constant. Therefore, it is impossible to convert the input image signal to obtain a modulated pulse width in the range of 0 to 340 ns.

FIG. 7 shows a second embodiment for solving this problem. 7, the same elements as those in FIG. 2 are denoted by the same reference numerals, and a detailed description thereof will be omitted. Here, the conversion table 1 includes two reference dot clocks PX1 (period of 320 ns) and dot clocks (period of 340 ms).
Two conversion tables LUT1 and LUT3 are set in advance, and are basically the same as in the first embodiment. However, in the second embodiment, the conversion table 1 converts and outputs the input image signal and simultaneously outputs the carry selection signal ER. The carry selection signal ER is output from the dot clock P
When the reference PX1 is selected as X, the level is always high. When PX3 is selected, the level is high when the input image signal is within a predetermined value (239) described later. When the value exceeds a predetermined value, the level is set to a low level.

In contrast to the first embodiment shown in FIG. 2, in the second embodiment shown in FIG. 7, a delay circuit 9 as a delay means and a selector circuit 10 are provided in the first pulse width generation circuit 3. And have been added. The delay circuit 9 is constituted by a D flip-flop. The delay circuit 9 receives the carry signal CARRY output when the frequency divider 6 finishes counting, and delays it by one cycle (20 ns) of the original oscillation CLK. The signal CARRY 'is output.

The selector circuit 10 includes two logical product (AND) circuits 10a and 10b and a logical sum (OR) circuit 10c.
It is constituted by and. The AND circuit 10a includes a delay carry signal CARRY 'delayed by the delay circuit 9;
The inverted output of carry select signal ER from conversion table 1 is input, and carry signal CARRY from frequency divider 6 and carry select signal ER from conversion table 1 are input to AND circuit 10b. It is like
The outputs of the AND circuits 10a and 10b are respectively input to the OR circuit 10c.

With the above configuration, the OR circuit 10c in the selector circuit 10 outputs the delayed carry signal CARRY 'when the carry select signal ER is at a low level, while the carry select signal ER
Is high level, CARRY is output as it is. Therefore, when the input image signal input to the conversion table 1 exceeds a predetermined value when using the dot clock PX3, the first pulse signal in the first pulse width generator 8 is based on the carry signal delayed by 20 ns. Is generated, and the pulse width of the first pulse signal is extended by 20 ns as compared with the case where the maximum count number 16 is counted by the frequency divider 6 (see FIG. 8).

Next, the delay characteristics and the conversion characteristics in the conversion table 1 will be described in detail. When the reference dot clock PX1 is used, as in the first embodiment described above, no conversion may be performed in which the input image signal is output as it is.
Further, the desired first pulse width can be obtained based on the carry signal CARRY output at the end of the counting in the frequency divider 6 without using the delay circuit 9.

However, when the dot clock PX3 is used without converting the input image signal, the period of the dot clock PX increases, contrary to the case where the PX2 is used. And the exposure energy obtained for the same input image signal decreases. Therefore, while the reference dot clock PX1 obtains a modulation pulse width of 0 to 320 ns for the input image signal 0 to 255, the input image signal is converted by the LUT 3 in response to the increase of the dot clock cycle. A new modulation pulse width of 0 to 340 ns is obtained. As a result, even when the dot clock PX3 is used, the duty ratio does not change, and proper exposure energy can be obtained. The method is described below.

In order to correct the deviation of the exposure energy between the case where the reference dot clock PX1 is used and the case where the dot clock PX3 is used, it is the same as the case where the dot clock PX2 having a shorter cycle than the reference is used. , A conversion satisfying the following equation may be performed. do (n) = {340 ns (272 gradations) / 320 ns (256 gradations)} × di (n) = 1.0625 × di (n) (n = 0-255) Here, the conversion table 1 Although it is sufficient that an image signal can be output, the present embodiment is based on an 8-bit signal, the maximum count number in the frequency divider 6 is 16, and only 0 to 255 image signals can be output from the conversion table 1. Can not. For this reason, it is not possible to cope with an image signal converted to a value exceeding 255 in the above equation.

Therefore, first, the conversion output value do (n)
When the input image signal di (n) whose maximum value is 255 is obtained, when the input image signal is 239, an output of 255 is obtained by the above equation. , And carry select signal ER is kept at high level. More specifically, the conversion equation do is used so that the deviation of the output value after the conversion is at least 1 and the portion where the deviation is 2 is provided (15 points in the input image signals 0 to 240) without deviation. (n) = 1.0625
The conversion value LUT3 is obtained by processing the decimal part of the calculated value in × di (n) (see FIGS. 9 and 10).

Next, signals 240 to 255 exceeding 239 of the input image signals will be described. This input image signal is 8
If there is no bit restriction, it is sufficient to convert to 256-271. However, since the conversion output is limited to 0 to 255 as described above, as shown in FIGS. 9 and 10, the conversion of this part is applied to the same value as the input image signals 224 to 239,
At the same time, carry select signal ER is set to low level. By doing so, the input image signals 240 to 255
, A modulation pulse width of 321.25 to 340 ns is allocated. Therefore, the first pulse width for the input image signals 0 to 255 can be changed to 20 to 340 ns.

With this configuration, even when the dot clock PX3 having a longer cycle than the reference dot clock PX1 is used, a large hardware change is not performed.
The same duty as when the reference dot clock PX1 is used can be obtained, so that substantially the same gradation can be obtained. In the second embodiment, as shown in FIG.
Although the portion where the deviation is 2 is evenly arranged as shown by the dotted line in the figure, when the density characteristic of the photosensitive material with respect to the exposure energy is as shown in FIG. 11, the portion corresponding to the hatched portion in FIG. Part where the change in density is slow with respect to the change in exposure energy)
It is good also as an arrangement | positioning which concentrates a deviation setting part.

Further, in the above embodiment, FIGS.
As shown in FIG. 10, as a conversion in the conversion table LUT3, the input image signal is
The same value as the conversion in the case of 224 to 239 is assigned, and at this time, the carry selection signal ER is set to the low level. However, as shown by the dotted line in FIG. 10, the input image signal to which the same value is to be assigned does not necessarily need to be 240 to 255. For example, when the input image signal is 0 to 15 with respect to the input image signal 16 to 31, The carry conversion signal ER may be set to a low level for the value of the input image signal of 16 or more.
, The same conversion value as when the input image signal is 16 to 31 is assigned, and the carry selection signal ER may be set to a low level for the input image signal having a value of 32 or more.
The signal range for delaying the ARRY signal can be set arbitrarily.

In the above embodiment, hardware is provided to delay the carry signal CARRY in order to delay the end of counting and obtain a modulation pulse width (340 ns) longer than 320 ns (divided by 16 of the original oscillation). I have. However, when the carry selection signal ER goes low, the count of the 16 frequency divider may be stopped for one cycle time of the original oscillation CLK. Further, a 17 divider may be used as the divider 6.

Further, compared to the reference dot clock PX1,
When generating a dot clock having a period of 360 ns longer by two periods of the original oscillation CLK, a delay circuit is further added to delay the carry signal by a maximum of 40 ns (two periods of the original oscillation CLK as a unit pulse signal). You can do it. In the first and second embodiments, the conversion tables LUT2 and LUT3 are set one by one for the predetermined dot clocks PX2 and PX3. However, the conversion values are continuous on the conversion table LUT2. Alternatively, a plurality of conversion tables in which the position of a portion where the conversion value jumps by one on the conversion table LUT3 is different are provided for one dot clock PX, and the plurality of conversion tables are randomly selected. In this way, it is possible to prevent the gradation reduction or the gradation jump for converting and using the input image signal from occurring regularly.

Further, in this embodiment, a case where a shorter dot clock PX2 is generated with respect to a reference dot clock PX1 having a period of 320 ns, and a case where a longer dot clock P
The case where X3 is generated has been described separately, but these are combined and a dot clock of 320 ns is used as a standard, and dot clocks PX3 of 340 ns and 300 ns are used.
A configuration may be used in which the beam position is corrected by selectively using PX2.

Further, in the pulse width modulation of the drive pulse signal (pulse current) of the semiconductor laser as shown in this embodiment, the current value is changed stepwise, and the pulse width modulation of the pulse current is performed for each current value. A configuration may be adopted.

[0054]

As described above, according to the present invention, when scanning exposure is performed by using a pulse width modulated semiconductor laser beam, even if the period of the dot clock changes, the modulated pulse width corresponding to the input image signal is changed. Has an effect that the duty ratio with respect to the dot clock cycle can be kept constant.

Further, when the modulation pulse width is obtained by counting the digital image signal values, it is easy to generate a pulse width exceeding the maximum count number by the above-mentioned counting. When the setting is longer than the above, there is an effect that an intended modulated pulse width can be obtained without making a significant change in hardware.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention.

FIG. 2 is a system block diagram of a first embodiment of the present invention.

FIG. 3 is a time chart showing characteristics of pulse width modulation in the first embodiment.

FIG. 4 is a diagram showing a state of a change in exposure energy due to a change in a cycle of a dot clock.

FIG. 5 is a diagram showing conversion characteristics of an input image signal in the first embodiment.

FIG. 6 shows conversion tables LUT1, LUT in the first embodiment.
The figure which shows the mode of UT2.

FIG. 7 is a system block diagram of a second embodiment of the present invention.

FIG. 8 is a time chart showing characteristics of pulse width modulation in the second embodiment.

FIG. 9 shows conversion tables LUT1, LUT in the second embodiment.
The figure which shows the mode of UT3.

FIG. 10 is a diagram illustrating conversion characteristics of an input image signal in the second embodiment.

FIG. 11 is a diagram illustrating an example of a relationship between exposure energy and density in a photosensitive material.

FIG. 12 is a diagram illustrating a change in a duty ratio when the cycle of a dot clock is changed.

[Explanation of symbols]

 Reference Signs List 1 conversion table 2 dot clock generator 3 first pulse width generation circuit 4 second pulse width generation circuit 5 pulse width synthesis circuit 6 frequency divider 7 load signal generation circuit 8 first pulse width generator 9 delay circuit 10 selector circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) B41J 2/44 H01S 5/042

Claims (3)

(57) [Claims] 1. A semiconductor laser driving device configured to modulate a pulse width of a semiconductor laser beam in accordance with an input image signal, wherein a plurality of dot clocks having different periods are provided as dot clocks for defining a recording time per pixel. A dot clock generating means for selectively generating a dot clock; and a duty ratio of a modulation pulse width obtained for an input image signal to a dot clock cycle based on a cycle of the dot clock generated by the dot clock generating means. Input image signal conversion means for converting an input image signal so as to have a fixed relationship with the image signal; and a semiconductor laser driving pulse signal having a pulse width corresponding to the signal converted by the input image signal conversion means, And a driving pulse signal generating means for generating the signal based on a clock. Semiconductor laser driving device. 2. The apparatus according to claim 1, wherein said input image signal converting means converts the input image signal based on a ratio of a cycle of a dot clock generated by said dot clock generating means to a cycle of a reference dot clock. The semiconductor laser driving device according to claim 1, wherein 3. A count means for counting the signal value converted by the input image signal converting means in synchronization with a fixed unit pulse signal, and a start and end of counting by the count means. Pulse width setting means for setting the pulse width of the semiconductor laser drive pulse signal based on the above, and when the input image signal exceeds a predetermined value, the counting of the counting means is terminated by a predetermined integer multiple of the cycle of the unit pulse signal. The semiconductor laser driving device according to claim 1, further comprising: a delay unit configured to delay.