JP3049852B2 - Successive conversion AD converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a successive conversion type analog-to-digital (hereinafter abbreviated as "AD") converter, and more particularly to a method for converting a variety of signals into various conversion forms (output or linear function proportional to the logarithm of an input signal). The present invention relates to an A / D converter (hereinafter, referred to as an ADC or an A / D converter) suitable for use in performing an A / D conversion using a device that outputs a high output.

[0002]

2. Description of the Related Art At present, various types of electronic devices are digitized (for example, digital multimeters, vehicle speed meters, level meters, etc.), and applications using an AD converter have increased. Among them, the digital multimeter has a plurality of conversion characteristics such as an AD conversion for obtaining an output proportional to the input voltage and an AD conversion for obtaining an output proportional to the logarithm of the input voltage in order to measure various input voltages. An AD converter has become necessary. Conventionally, in this type of application, an AD converter that obtains an output proportional to the input voltage is used, and when it is desired to obtain an output proportional to the logarithm, A
The digital signal after the D conversion is subjected to arithmetic processing by software to a signal proportional to the logarithm.

Here, a system using a conventional AD converter will be described with reference to the drawings.

FIG. 5 is a block diagram of a single-chip microcomputer (hereinafter referred to as a one-chip microcomputer) including a conventional AD converter. One-chip microcomputer 50
0 is a central processing unit (hereinafter referred to as CPU) 501
And read-only memory (hereinafter referred to as ROM) 502
And a successive conversion AD converter (hereinafter referred to as ADC)
503. CPU 501, ROM 502, and ADC 503
Are interconnected by a bus 504 and exchange information. ADC 503 is a reference voltage input terminal 506
And a voltage input terminal 505. Hereinafter, for simplification of description, it is assumed that the precision is 4 bits.

[0005] The ADC 503 has a conversion characteristic proportional to the input voltage as shown in FIG. 2.

[0006]

[Table 1]

FIG. 3 is a characteristic diagram in a case where logarithmic AD conversion is performed on an input voltage, and the numerical values are as shown in Table 2 below.

[0008]

[Table 2]

Next, a method of obtaining the logarithmic value of the input voltage by the one-chip microcomputer will be described below.

(1) The CPU 501 executes programs on the ROM 502.

(2) When the program needs a logarithmic value for the analog input voltage, the CPU 501
4 through the ADC 503 to the measurement voltage input terminal 505
Is commanded to A / D-convert the voltage input to.

(3) The ADC 503 is connected to the measurement voltage input terminal 50.
The voltage input to 5 is linearly converted to a digital value as shown in Table 1.

(4) The ADC 503 sends the conversion result to the bus 504
To the CPU 501.

(5) The CPU 501 executes A
The D conversion result is converted by a program so as to obtain the AD conversion result shown in Table 2, and a desired numerical value is obtained. The conversion table in this case is shown in Table 3 below.

[0015]

[Table 3]

As described above, the one-chip microcomputer obtains the logarithmic value of the input voltage.

[0017]

However, when performing A / D conversion requiring the logarithm of the magnitude of the input signal (Table 2 and FIG. 3), the logarithm of the A / D conversion that produces an output proportional to the input signal is obtained by software. As can be seen by comparing Table 1 and Table 2, the accuracy is degraded because the weight of one bit is different. Also, the result of the logarithmic conversion is as shown in Table 3, and the obtained digital values are discrete. Further, since the numerical value converted by the AD converter is converted again by software, it takes a long calculation time and consumes memory in a program and a work area. Conversely, when performing an A / D conversion requiring an output proportional to the input signal, the A / D conversion is performed to output the logarithm of the magnitude of the input signal, and this is converted into a proportional value of the input signal on software. The same is true at times.

[0018]

A sequential conversion type AD converter according to the present invention comprises a plurality of DA conversion circuits having different conversion characteristics.
A sampling and holding circuit for sampling and holding an analog signal to be converted, a selection circuit for selecting one of the outputs of the DA conversion circuit, and a sampling and holding circuit; A comparison circuit that compares an output of a circuit with an output of the selection circuit; and a control circuit that controls selection by the selection circuit and controls AD conversion in the comparison circuit.

[0019]

In the present invention, a plurality of Ds having different conversion characteristics are used.
The control circuit selects the DAC having the desired characteristics in the selection circuit in order to perform the desired AD conversion.
And outputs a signal for selecting the D.
One of the A conversion circuits is selected. Then, the output of the selected DA conversion circuit and the output of the sample & hold circuit are input to a comparison circuit and compared to perform AD conversion. Therefore, at the time of AD conversion, it can be directly converted into a digital value having desired characteristics.

[0020]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an ADC 100 according to an embodiment of the present invention. The ADC 100 includes a first DA converter (hereinafter, referred to as DAC) 101, a second DAC 102,
A control circuit 106, a selector 103, a comparator 104,
A sample and hold circuit (hereinafter abbreviated as S & H) 105. The ADC 100 has a measurement voltage input terminal 109 and a bus 108 for exchanging information with the reference voltage input terminal 117 and the outside. As is well known, the DACs 101 and 102 can be configured by a resistor ladder or a capacitor array.

From the control circuit 106, the first DAC 101 and the second DAC 101
A DAC input signal line 107 is connected to the DAC 102, a sample timing line 115 is connected to the S & H 105, and a DAC selection line 116 is connected to the selector 103. The first DAC 101 outputs a DA conversion output 110 to the selector 103. Also, the second DAC
From 102, a DA conversion output 111 is output to the selector 103. The selector 103 outputs a selector output 112 to the comparator 104. comparator
From 104, a comparator output 114 is output to the control circuit 106. From S & H 105, comparator 104
, An S & H output 113 is output.

The ADC 100 has a conversion characteristic proportional to the input as shown in FIG. 2 and Table 1 when the DAC 101 is used, and shown in FIG. 3 and Table 2 when the DAC 2102 is used.
It has a conversion characteristic proportional to the logarithm of the input as represented by.

Next, the operation of the ADC 100 will be described.

First, the operation when the ADC linearly converts an input signal into a digital value will be described.

(1) The control circuit 106 of the ADC 100 outputs a signal to the sample timing line 115 so that the voltage input to the measured voltage input terminal 109 is held by the S & H 105.

(2) The control circuit 106 outputs a signal to the DAC selection line 116 so as to perform AD conversion using the DAC 101.

(3) The control circuit 106 performs AD conversion by binary search while comparing the S & H output 113 and the selector output 112 with the comparator 104.

In this manner, the input voltage can be linearly converted into a digital value by the first DAC 101.

Next, the operation when the ADC 100 converts an input signal logarithmically into a digital value will be described.

(1) The control circuit 106 of the ADC 100 outputs a signal to the sample timing line 115 so that the voltage input to the measurement voltage input terminal 109 is held by the S & H 105.

(2) The control circuit 106 outputs a signal to the DAC selection line 116 so as to perform AD conversion using the DAC 102.

(3) The control circuit 106 performs AD conversion by binary search while comparing the S & H output 113 and the selector output 112 with the comparator 104.

In this manner, the input voltage can be logarithmically converted into a digital value by the second DAC 102. In the present embodiment, the control circuit 106 outputs a signal for causing the selector 103 to select a DAC having desired characteristics via the selector signal line 116, and outputs the output of the selected DAC to the S & H output 113 by the comparator 104. Since the AD conversion is performed by comparison, the conversion characteristic can be switched to a desired one at the time of the AD conversion.

Next, a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 4 is a block diagram showing an ADC 400 according to the present embodiment. Hereinafter, differences from the first embodiment will be mainly described. However, the first DAC 401 and the second DAC 4
02, the control circuit 400, the selector 403, the S & H 405, and the comparator 404 are the first DAC 101 and the second DAC
102, a control circuit 100, a selector 103, an S & H 105, and a comparator 104, which correspond to a DAC input signal line 407, a bus 408, a measurement voltage input terminal 409, DA conversion outputs 410 and 411, a selector output 412, an S & H output 413, a comparator output 414, and a sample. The timing line 415 and the DAC selection line 416
C input signal line 107, bus 108, measurement voltage input terminal 109, D
A conversion output 110, 111, selector output 112, S & H output 11
3, comparator output 114, sample timing line 115,
This corresponds to the DAC selection line 116.

In the first embodiment, the first DAC 101 and the first D
Although the reference voltage input terminal 117 of the AC 102 is common, in the second embodiment, the first DAC 401 is connected to the reference voltage input terminal 4.
17 and the second DAC 402 has a reference voltage input terminal 418.

In this embodiment, as described above, the DAC
Since 401 and 402 have separate reference voltage input terminals 417 and 418, not only can the conversion characteristics be cut off at the time of A / D conversion, but also the reference voltage at the time of A / D conversion can be independently switched, as in the first embodiment. This has the advantage of increased versatility.

[0039]

As described above, according to the present invention, the DAC is switched and used according to the desired conversion characteristic.
The numerical value obtained by AD conversion has desired characteristics.
This can be used as is. For this reason, there is no need to sacrifice conversion accuracy like logarithmic conversion in software,
High conversion accuracy. Further, since the vinegar is not necessary that converts the software, because the computation time in software is not required, it is possible to shorten the processing time, memory usage can be saved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an ADC according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram of a DAC used when performing linear AD conversion on an input voltage.

FIG. 3 is a characteristic diagram of a DAC used when performing logarithmic AD conversion on an input voltage.

FIG. 4 is a block diagram illustrating an ADC according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a conventional one-chip microcomputer.

[Explanation of symbols]

 ADCs 101, 102, 401, 402; DACs 103, 403; selectors 104, 404; comparators 105, 405; S & H 106, 406; control circuits 107, 407; DAC input signal lines 108, 408, 504; buses 109, 409, 505; Output 115,415; sample timing line 116,416; DAC selection line 117,417,418,506; reference voltage input terminal 500; one-chip microcomputer 501: CPU 502; ROM

Claims (3)

(57) [Claims] A plurality of DA conversion circuits having different conversion characteristics are provided.
A sampling and holding circuit for sampling and holding an analog signal to be converted, a selection circuit for selecting one of the outputs of the DA conversion circuit, and a sampling and holding circuit; A successive conversion A / D converter comprising: a comparison circuit that compares an output of a circuit with an output of the selection circuit; and a control circuit that controls selection by the selection circuit and controls AD conversion in the comparison circuit. vessel. 2. The successive conversion A / D converter according to claim 1, wherein said DA conversion circuit is constituted by a resistance ladder. 3. The successive conversion A / D converter according to claim 1, wherein said D / A conversion circuit is constituted by a capacitance array.