JP3052263B2 - Logic verification sufficiency evaluation method and system therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to verification of a logic circuit, and more particularly, to a sufficiency evaluation method and a sufficiency evaluation system in logic verification using logic simulation, and more particularly, to express the function of a logic circuit to be verified. The present invention relates to a logic verification sufficiency evaluation method and a logic verification sufficiency evaluation system based on the occurrence state of a functional event.

[0002]

2. Description of the Related Art In recent years, with the advance of high integration technology of semiconductors, the scale of logic devices and the scale of all LSIs have been advanced, and the prolonged development period and the increase in development man-hours have become important problems. I have. In order to shorten the development period and reduce the number of development steps for logic devices, it is essential to conduct logic verification to extract design logic failures of logic devices before manufacturing the logic device, that is, without using an actual device. Efficiency is an important issue. Recently, logic verification is mainly performed by logic simulation. However, the number of items to be verified increases due to the large-scale complexity of the logic device to be verified. The required computer time, man-hours, etc., increase, and as a result, the cost of the completed logic device as a whole increases.

Under such circumstances, conventionally, a logic verification sufficiency evaluation method has been proposed for the purpose of realizing more efficient logic verification. The logic verification sufficiency evaluation method refers to measuring the occurrence of a function, operation, state, and the like (hereinafter, simply referred to as a function) of a pre-registered logic device to be verified during execution of a logic simulation, and The measurement results are used to indicate unverified functions, to manage the progress of simulation, etc., and to provide feedback such as selection of test programs to be executed and creation of new test programs, so that efficient and efficient test programs can be used. It is intended to realize logic verification. The presence or absence of the occurrence of a specific function of these verification target logic devices is specifically measured by the presence or absence of the occurrence of a signal pattern corresponding to the particular function called a function event during simulation execution. FIG. 1 shows an example of a specific function event as a function event 100. This example is an example of bit patterns of four signals appearing at a fixed timing. This represents, for example, a race condition of a request signal, an instruction type, and the like generated in the verification target logic device. That is,
In the logic verification sufficiency evaluation method described above, whether or not the specific function of the verification target logical device represented by the functional event depends on whether or not the pattern of the specific functional event 100 occurs during the execution of the simulation. It is determined whether the verification has been performed. Evaluating the degree of progress of logic verification based on the occurrence of a functional event expressing the function of the verification target logical device in this way is sometimes referred to as “functional coverage”. As a logic verification sufficiency evaluation method based on functions in a conventional logic simulation, for example, as described in JP-A-3-62172, registration, measurement,
A logic verification sufficiency evaluation method for evaluating the occurrence of a function at each step of the result output, and as described in JP-A-63-123136, the number of function events to be measured is limited. For example, there is known a method of providing a special mechanism for evaluation and performing evaluation.

[0004]

In the above-described logic verification sufficiency evaluation method based on the occurrence of functional events, the number of functional events to be checked for occurrence is generally on the order of tens of thousands of orders for a logical device. Reach For these,
Every occurrence of the logic simulation must be checked for all occurrences. For example, when a simulation of several thousand cycles is executed by one test program, it is necessary to execute a process of checking occurrence several hundred million times. There are two ways to do this:
One is known. The first method is to output a waveform change of a signal for observing the occurrence of a functional event from a simulator to a file, read the file after execution of the simulation, and measure the occurrence of a given functional event by software. Is the way. In this method, the simulator does not need to be provided with a special mechanism, and can be realized relatively easily. However, when the number of measurement target function events is large, the file capacity for recording the waveform change of the observed signal increases, and the processing time becomes enormous if hundreds of millions of occurrence checks are executed by software. The second method is a method in which the simulation is interrupted every time one cycle simulation is performed during the execution of the simulation and a process of checking occurrence of a measurement target function event is executed. In this method, unlike the previous method, there is no need to output a signal waveform change, and no special file capacity increase is caused. However, since the simulation execution is interrupted every cycle and a function event occurrence check is performed, the overhead becomes extremely large.

As described above, in these two methods, the processing time spent for simulation and sufficiency evaluation by one test program becomes enormous, and a practical method as a sufficiency evaluation method for logic verification is required. Was not. That is, a measuring method for executing these at high speed is important for practical use, but no solution has been shown for this in, for example, the above-mentioned Japanese Patent Application Laid-Open No. 3-62172. Also, Japanese Patent Application Laid-Open No. 63-1231
As shown in Japanese Patent Publication No. 36, there is a system in which a special mechanism is provided in a simulator to measure the occurrence of a functional event at a high speed during execution of a simulation. However, there is a problem that a special processing mechanism is required in the simulator. Was. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and system for evaluating logic verification sufficiency based on the presence or absence of occurrence of a functional event. To provide a method and system that minimizes overhead for

[0006]

In order to achieve the above object, a logic verification sufficiency evaluation method according to the present invention firstly provides a function which expresses a function of a logic circuit to be verified which is defined in advance, prior to execution of a simulation. Inputs information about the pattern of the event, creates a virtual logic circuit that has the function of measuring the occurrence of the functional event to be measured and recording the number of occurrences, and then creates the virtual measurement circuit generated by this process A logic simulation is performed for the logic circuit for use and the logic circuit to be verified collectively. After the simulation is completed, the data on the number of occurrences of functional events held in the measurement logic circuit is read out,
The present invention is characterized in that the data in which the occurrence status data up to now is accumulated is updated and the occurrence status of the functional event is obtained. In addition, the logic verification sufficiency evaluation system of the present invention includes:
Logic verification sufficiency for inputting information on a pattern of a function event expressing a function of a logic circuit to be verified which is defined in advance, measuring the number of occurrences of the function event during a logic simulation, and outputting occurrence status data of the function event A first means (function coverage measurement preparation processing means) for creating a virtual measurement logic circuit having a function of measuring the number of occurrences of the function event based on information on the pattern of the function event; ), And simulating the virtual measurement logic circuit data and the verification target logic circuit data to be verified collectively to measure the number of occurrences of the function event and output the occurrence state of the function event. And (2) means.

[0007]

According to the logic verification sufficiency evaluation method and system of the present invention, prior to execution of a logic simulation and measurement of occurrence of a functional event, a function for checking occurrence of a functional event to be measured and holding the number of occurrences is provided. Generates a virtual logic circuit for measurement and simulates the logic circuit for measurement and the logic circuit to be verified at the same time, thereby interrupting the simulation without any special processing during the simulation. It is possible to obtain the number of occurrences of a functional event for one test program without doing so, and it is possible to quickly evaluate logic verification sufficiency based on the functional event.

[0008]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 13 is an example of a hardware configuration of a logic verification sufficiency evaluation system 200 for implementing the logic verification sufficiency evaluation method of the present invention. As shown in the figure, the hardware of the logic verification sufficiency evaluation system in the present embodiment includes a CPU 1, an output device 2, a keyboard 3, a main memory 4,
And an auxiliary storage device 5. In main memory 4,
Each program of the function coverage measurement preparation processing 1000, the logic simulator 201, and the result accumulation editing processing 202 is stored, and each is executed by the CPU 1. Although the logic simulator 201 is a program for executing a logic simulation, the logic simulation is executed by adding a simulation dedicated mechanism 6 which is a dedicated hardware instead of including the logic simulator 201 in the main memory 4. In some cases. The auxiliary storage device 5 includes logic circuit data 203 to be verified, which is an input for executing a logic simulation.
The test data 204 and the function event pattern data 300 which is an input for logic verification sufficiency evaluation are stored. The auxiliary storage device 5 also stores simulation result data 205, which is the output of the logic simulation.
And cumulative data 800 which is the output of the logic verification sufficiency evaluation
, The function coverage measurement result 900 is also stored.

FIG. 2 is a schematic diagram showing a processing procedure of a logic verification sufficiency evaluation system 200 according to an embodiment of the present invention. As shown in the figure, the processing procedure of the logic verification sufficiency evaluation system 200 is such that the function event pattern data 300 (see FIG. 3 for details) is input, and the measurement logic circuit data required for the function coverage measurement is input. 400 (see FIG. 4 for details)
1), connection information data 500 (see FIG. 5 for details), and function coverage measurement preparation processing 1000 (see FIG. 1 for details) for generating function event name data 600 (see FIG. 6 for details).
0), and the simulation result by the logic simulator 201 and the processing result of the function coverage measurement preparation processing are edited to output the accumulated data 800 (see FIG. 8 for details) and the function coverage measurement result 900 (see FIG. 9 for details). It is composed of a result accumulation editing process 202. In this specification, “processing” refers to processing itself performed by software (components of a method).
Or means having such a function (a component of the system).

The processing of the logic verification sufficiency evaluation system 200 will be described in more detail. (1) First, prior to execution of the logic simulation, the function coverage measurement preparation processing 1000 performs the function coverage pattern analysis based on the input function event pattern data 300 based on the function coverage pattern data 300. Measurement logic circuit data 400 and connection information data 5 required for measurement
00 and the function event name data 600 are generated. (2) Next, the logic simulator 201 converts the test data 204 including the measurement logic circuit data 400 and the connection information data 500 created by the function coverage measurement preparation processing 1000 to the verification target logic circuit data 203. Run the used logic simulation. (3) After completion of the logic simulation, cumulative memory data 700 recording the number of occurrences of functional events output by the logic simulator 201 by the result cumulative editing process 202
With the function event name data 600 previously created by the function coverage measurement preparation processing 1000 as an input, the cumulative data 800 is updated and the function coverage measurement results 900
Is output.

The logic verification sufficiency evaluation system 20 of the present invention
0 is newly added to the following processes (1) to (5) in the environment of “normal logic simulation” surrounded by a broken line 207 in FIG.
It is characterized by adding (3). Here, the “ordinary logic simulation” refers to the logic simulator 2
01 (or the simulation-dedicated mechanism 6 in FIG. 13) compares the test data 2
The simulation is performed by using the simulation result data 04, and the result is output as simulation result data 205. (1) First, the function coverage measurement preparation processing 1000 is executed. The function event pattern data 300 is input, and the measurement logic circuit data 400 having the function of checking occurrence of a function event and holding the number of occurrences, and the logic to be verified. The connection information data 500 indicating the connection between the circuit and the measurement logic circuit, and the function event name data 600 indicating the correspondence between the name of the function event and the name of the accumulation memory are created.

(2) Next, the logic simulator 201
The logic circuit data 203 to be verified using the connection information 500
And the logic circuit data 400 for measurement, and a normal logic simulation using the test data 204 is performed on them. Here, the measurement logic circuit data 40
By performing a logic simulation with respect to 0, the occurrence of a functional event is checked and the number of occurrences is recorded. After the simulation is completed, the value of the accumulation memory that records the number of occurrences in the measurement logic circuit is output to the accumulation memory data 700. That is, the cumulative memory data 700 records the number of occurrences of the function event during the simulation for one test data. (3) Finally, the result cumulative editing process 202 uses the contents of the cumulative memory data 700 to generate the function event name data 60 created by the function coverage measurement preparation process 1000.
With reference to 0, the accumulated data 800 is updated, and the content is output as the function coverage measurement result 900.
Here, since the cumulative memory data 700 is a table of the cumulative memory name and the retained data thereof, first, the functional event name data 600 is referred to, and is converted into the data of the functional event name and the number of occurrences. Update 800.

As described above, in the logic verification sufficiency evaluation system 200, the measurement of the occurrence of a functional event is performed during the execution of the logic simulation by implementing the function of measuring the occurrence of a functional event in the circuit to be simulated. It becomes possible. Therefore, it is not necessary to store the waveform change of the observation signal, and the capacity of the simulation result data 205 does not needlessly increase. Further, it is not necessary to add a special mechanism to the existing logic simulator 201, and it is not necessary to execute a special process for measuring the function coverage other than outputting the accumulated data during the execution of the simulation. Become.

Next, the process of the logic verification sufficiency evaluation system 200 will be described in more detail with reference to FIGS. In the logic verification sufficiency evaluation system 200, preparations for measuring a function coverage are first performed by a function coverage measurement preparation process 1000 prior to a logic simulation. FIG. 3 shows an example of function event pattern data that is input to the function coverage measurement preparation processing 1000. The function event pattern data is data for defining a pattern of a function event to be subjected to occurrence measurement during a logic simulation. The example illustrated in FIG. 3 is an example of the function event pattern data 300 for defining the function event 100 illustrated in FIG.
In the figure, “PAT EVENT1” on the first line indicates that this function event 100
To define the name "EVENT1". “ST CLOCK T0;” in the second line is for defining a clock “T0” which is a reference for defining a pattern of the functional event 100. The third to sixth lines indicate the function event 100
Are used to define the signal names, signal values, and timings that constitute the pattern. That is, “SIG SIGNAL_A: 1: 0;” in the third line defines that the signal value of the signal “SIGNAL_A” is “1” and the delay from the reference clock T0 is “0” cycle, Eye "SIG SIGNAL_B: 1: 1;"
Defines that the signal value of the signal “SIGNAL_B” is “1” and the delay from the reference clock T0 is “1” cycle,
“SIG SIGNAL_C: 0: 2;” on line 5 is a signal “SIGNAL_C”
Is "0" and the delay from the reference clock T0 is "2"
Cycle, and in line 6, "SIG SIGNAL_
"D: 1: 1;" defines that the signal value of the signal "SIGNAL_D" is "1" and the delay from the reference clock T0 is "1" cycle, and "END_PAT;" Pattern name "EVENT
This means the end of the definition of “1”. As described above, the function event pattern data 300 corresponds to the function event 100 shown in FIG.
Is uniquely expressed. As mentioned above,
The functional event pattern data 300 defines functional event patterns for which the number of occurrences is to be measured by logic simulation, for the number of target events. The method of expressing the function event pattern data 300 is not limited to the method illustrated in FIG.
Needless to say, DL (VHSIC Hardware Description Language) is also possible. The function coverage measurement preparation processing 1000 receives the function event pattern data 300 illustrated in FIG. 3 as an example, and uses the following measurement logic circuit data 400, connection information data 500, and function event name necessary for function coverage measurement. The data 600 is created.

The measurement logic circuit data 400 is a virtual function having a function of measuring the occurrence of a function event for each function event defined in the function event pattern data 300 and recording the number of occurrences of the function event. Logical circuit data. FIG. 4 shows a specific example of the present measurement logic circuit. Note that the clock signal is omitted in the figure for simplification. The measurement logic circuit 400 in FIG.
It has a function of checking occurrence of the functional event 100 shown in FIG. 1 and measuring the number of occurrences. That is, the measurement logic circuit 400 inputs a signal in the verification target logic circuit 401 and measures the number of times that the signal becomes a pattern indicated by the functional event 100. In FIG. 4, signal name conversion is performed to distinguish between the two. For example, SIGNAL_A
INPUT_A for SIGNAL_B and INPUT_B for SIGNAL_B
Correspond to each other. The general configuration of the measurement logic circuit 400 will be described in further detail. As shown in FIG. 4, the measurement logic circuit 400 includes a time adjustment logic 402, a pattern matching logic 403, and an accumulation memory 404. First, the timing of the signal input to the measurement logic circuit 400 is adjusted using the time adjustment logic 402 that adjusts the delay time for each signal. For example, the function event 100 shown in FIG.
In the case of, since the pattern appearing in SIGNAL_C is the latest in time, the check for the occurrence of this functional event is performed at this timing. That is, for example, INPUT_A
Must be delayed by two cycles to match this timing. Therefore, in the time adjustment logic 402, two edge-triggered latches synchronized with the reference clock T0 are connected so that INPUT_A is delayed by two cycles. Similarly, for INPUT_B and INPUT_D, 1
Two edge-triggered latches are connected. As described above, the time adjustment logic 402 enables pattern matching to be performed at the same timing.

Next, the pattern matching logic 403 compares the output signal from the time adjustment logic 402 whose timing has been adjusted with the pattern of the functional event.
In the case of the example of the function event 100 shown in FIG. 1, the output signal of the time adjustment logic 402 is checked for a match with “1101”. The pattern matching logic 403 is a comparison circuit, and its output signal becomes “1” only when the pattern matches, and the signal in the verification target logic circuit 401 indicates that the functional event 100 has occurred. Finally, the accumulation memory 404 records the number of occurrences of the functional event. The accumulation memory 404 outputs “1” to the output signal of the pattern matching logic 403.
Each time is generated, the value is counted up. As a result, the cumulative memory 404 holds the number of occurrences of the function event. As described above, the measurement logic circuit 400 has a function of checking occurrence of a function event defined in the function event pattern data 300 and holding the number of occurrences. The description level is the logic simulator 2
01 is a description level that can be handled.

FIG. 5 shows a specific example of the connection information data 500. The connection information data 500 is a correspondence table between signals in the logic circuit 401 to be verified, which constitute a functional event pattern, and input signals of the measurement logic circuit 400. The logic circuit data for measurement 400 is subjected to logic simulation later together with the logic circuit data 203 to be verified, but logical connection information between them is required. In the case of this example, for example, the signals SIGNAL_A and SIGNAL in the logic circuit 401 to be verified
_B, SIGNAL_C, and SIGNAL_D are connected to input signals INPUT_A, INPUT_B, INPUT_C, and INPUT_D of the measurement logic circuit, respectively.

FIG. 6 shows a specific example of the function event name data 600. The function event name data 600 is a correspondence table of the name and the corresponding cumulative memory name in the measurement logic circuit for each event. By executing the logic simulation, the number of occurrences of each event is held in the cumulative memory in the logic circuit for measurement 400, but it is necessary to register information indicating which functional event each cumulative memory corresponds to. There is. The function event name data 600 is a record of this information.
2. In the example of FIG. 6, the function event name EVEN
The number of occurrences of T1 and EVENT2 is the cumulative memory REG_A, R
Indicates that it is stored in EG_B. As described above in detail, the function coverage measurement preparation processing 1000 includes three pieces of data necessary for coverage measurement, that is, measurement logic circuit data 400 (FIG. 4) and connection information data 500 (FIG. ) And function event name data 600 (FIG. 6).

Next, in the logic verification sufficiency evaluation system 200 according to the present invention, a logic simulation is performed using a logic simulator 201. Dashed line 207 in FIG.
The part indicated by is a normal logic simulation system. In the ordinary logic simulation, as described above, a logic simulation is performed on the test data 204 with respect to the verification target logic circuit data 203, and the result is output to the simulation result data 205.

In the logic verification sufficiency evaluation system 200,
In addition to the “ordinary logic simulation” described above, the function coverage measurement preparation processing 1000 described above generates
The measurement logic circuit data 400 is also treated as a circuit to be simulated at the same time, and a simulation is performed. As a result, after the simulation is completed, the number of occurrences of each function event that occurred during the simulation is held in the cumulative memory corresponding to each function event in the measurement logic circuit data 400. The connection information data 50
0 is used to make a logical connection between the verification target logic circuit data 203 and the measurement logic circuit data 400. The connection method differs depending on the processing method of the logic simulator 201. For example, prior to the logic simulation,
A method of extracting the corresponding signal line from the logic circuit to be verified and connecting it to the input signal of the measurement logic as net information,
There is a method of propagating a waveform change of a signal by software. When the logic simulation is completed, the logic simulator 201 outputs the value of each accumulated memory (corresponding to the number of occurrences of the event) in the measurement logic circuit data 400 to the accumulated memory data 700 together with the name of the accumulated memory. FIG. 7 shows a specific example of the accumulated memory data 700. this is,
9 is a table showing the names of the accumulation memories and the values at the end of the simulation. In the example of FIG. 7, “3” is stored in the cumulative memory having the name “REG_A”, “0” is stored in “REG_B”,
“1” is stored in “C.” This value corresponds to the number of occurrences of the corresponding functional event that occurred during the simulation.
Then, the accumulated data 8
00 and outputs the function coverage measurement result 900.

FIG. 8 shows a specific example of the accumulated data 800.
The cumulative data 800 is a table of the names of the functional events to be measured and the cumulative number of occurrences. Result accumulation editing process 2
Numeral 02 denotes cumulative memory data 700 that records the number of occurrences of functional events for one test data, and functional event name data 60 that indicates the correspondence between functional event names and cumulative memory.
0 and cumulative data 800 as a past cumulative result are input. In the result accumulating editing process 202, first, referring to the function event name data 600,
The contents of the accumulated memory data, which is a correspondence table between the number of occurrences for one test data and the number of occurrences, are converted into the correspondence between the function name and the number of occurrences. Next, the number of occurrences of the corresponding function event is added to the contents of the read cumulative data 800, and the accumulated number of occurrences of the function event is calculated again.
Output to 00. In the example of the accumulated data in FIG.
The number of occurrences of the function event of “ENT1” is “3”, and “EVEN”
This indicates that the number of occurrences of "T2" is "0" and the number of occurrences of "EVENT3" is "4." 9 is edited and output as the function coverage measurement result 900. Fig. 9 shows a specific example of the function coverage measurement result 900. In the example of FIG. Percentage of the number of functional events (Figure 75.
Example of 0%) is replaced with (2) the number of occurrences of each functional event
ENT1 3 times, EVENT2 0 times, EVENT3 4 times)
In (3), names of functional events that have not occurred (EVENT2 in the figure) are shown.

As described above, in the logic verification sufficiency evaluation system 200, prior to the logic simulation,
The function event pattern data to be measured is read, occurrence of each function event is checked, and virtual measurement logic circuit data having a function of recording the number of occurrences is created. In the logic simulation, the circuit to be verified and the logic circuit for measurement are collectively simulated, and the number of occurrences of functional events for one test data is measured. Finally, after the end of the simulation, the number of occurrences of each functional event stored in the measurement logic circuit is read and the cumulative processing is performed to calculate the cumulative number of occurrences of the functional event. With the adoption of this method, from the viewpoint of the logic simulator, the check of the occurrence of a functional event and the process of retaining the number of times are realized by the same process as that of the normal logic circuit simulation. In general, in the logic simulator, since the speed of the simulation process of the logic circuit is increased, the process of measuring the number of occurrences of the functional event is also performed at a high speed. From this, compared to other measurement methods,
It is possible to minimize the overhead related to the processing speed.

FIG. 10 shows a function coverage measurement preparation process 10.
00 shows a processing flow of 00. In FIG. 10, a solid-line square indicates processing, a solid-line arrow indicates processing flow, a dashed-line square indicates data, and a dashed-line arrow indicates data flow. As described above, the function coverage measurement preparation processing 1000 receives the function event pattern data 300 as input, and performs measurement logic circuit data 400 necessary for function coverage measurement, connection information data 500, and function event name data 600.
Is output, and a more detailed process will be described below. The function coverage measurement preparation processing 1000 receives the function event pattern data 300 as input and outputs the pattern data analysis data 1007, and the function event pattern data analysis processing 1001 and the pattern data analysis data 1007.
, And outputs the measurement logic circuit data generation processing 1002 that outputs the measurement logic circuit data 400, and the pattern data analysis data 1007, and the connection information data 50.
It comprises a connection information data creation process 1003 for outputting 0, and a function event name data creation process 1004 for inputting pattern data analysis data 1007 and cumulative memory name data 1009 and outputting function event name data 600.

In the function coverage measurement preparation processing 1000,
First, the function event pattern data analysis processing 1001 reads the function event pattern data 300, performs lexical analysis / syntax analysis, and outputs pattern data analysis data 1007 as its internal data. This processing is an ordinary language analysis processing conventionally known. Next, the measurement logic circuit data creation processing 1002 reads the pattern data analysis data 1007, generates a measurement logic circuit having a function of measuring the occurrence and the number of occurrences of the defined function event, and generating the circuit information. Is output to the measurement logic circuit data 400. The measurement logic circuit data creation process 1002 includes a time adjustment logic creation process 1100 (detailed in FIG. 11), a pattern matching logic creation process 1200 (detailed in FIG. 12), a cumulative memory addition process 1005, and a measurement logic circuit data creation. The process 1006 is constituted.

In the measurement logic circuit data creation processing 1002, first, the time adjustment logic generation processing 1100 reads the pattern data analysis data 1007 and checks the time adjustment logic in the measurement logic circuit, that is, occurrence of a given function event. For this purpose, a logic circuit (corresponding to the time adjustment logic 402 in FIG. 4) having a function of adjusting the timing of the signals constituting the pattern is generated and output to the measurement circuit internal data 1008 as internal data.

Next, pattern matching logic generation processing 1200
Is a logic circuit having a function of checking whether the output signal of the pattern matching logic in the measurement logic circuit, that is, the time adjustment logic whose timing has been adjusted, matches the signal pattern of a given functional event (FIG. 4). (Corresponding to the pattern matching logic 403 of FIG. 3), and the measurement circuit internal data 100
8 is output. Next, cumulative memory addition processing 1005
A logic circuit having a function of being counted up by a circuit of an accumulation memory in the measurement logic circuit, that is, a signal indicating that a functional event which is an output signal of the pattern matching logic has occurred (accumulation memory 404 in FIG. 4) Is generated and output to the measurement circuit internal data 1008. Also,
The cumulative memory addition processing 1005 generates a correspondence table between the names of the functional events to be processed and the names of the corresponding cumulative memories.
Output to the accumulated memory name data 1009. Finally, the measurement logic circuit data generation processing 1006 reads the measurement circuit internal data 1008, converts the data into a description format that can be processed by the logic simulator 201, and outputs it as the measurement logic circuit data 400. In addition, as this description format,
For example, VHDL and EDIF (Electorical Design Int.
erchange Format) is known. The description level of the logic circuit in the above processing depends on the processing capability of the subsequent logic simulator.
nsfer) level or gate level. As described above, the measurement logic circuit data creation processing 1002 measures the number of occurrences of each function event defined in the function event pattern data 300, generates a logic circuit having a function of accumulating the number of occurrences, and generates the measurement logic. Output to the circuit data 400.

Next, in connection information data generation processing 1003, connection information data 500 defining the logical connection between the logic circuit to be verified and the measurement logic circuit is created. The connection information data generation processing 1003 receives the pattern data analysis data 1007 and the measurement circuit internal data 1008 as inputs, and receives the input signal name of the logic circuit created in the measurement logic circuit data creation processing 1002 and the observation signal of the functional event. And a pair with a signal name in the logic circuit to be verified is extracted and output. Finally, a function event name data generation process 1004
Thus, the function event name data 600 which is a correspondence table between each name of the function event and the name of the corresponding accumulation memory is created. The function event name data generation processing 1004 receives the cumulative memory name data 1009 as input, converts the data into a format as shown in FIG.

FIG. 11 shows a detailed processing flow of the time adjustment logic generation processing 1100. Time adjustment logic generation processing 110
At 0, the following processing is performed for all functional events in processing 1101. First, in process 1102, a difference between the timing of the appearance of the fastest pattern and the timing of the appearance of the slowest pattern among the patterns of the signal lines constituting the functional event (this is referred to as the maximum delay number) is examined. In the example of the function event 100 shown in FIG. 1, SIGNAL_A
This corresponds to the time difference between the appearance of the pattern and SIGNAL_C. In this example, this is two cycles.

Next, in processing 1103, the following processing is performed on all signal lines to be observed. First, in processing 1104, the number of cycles to be delayed is determined for each signal to be observed. Specifically, for each signal, the difference between the maximum delay number obtained in the process 1102 and the defined timing of the signal is obtained. In this example, SIGNAL_A is 2 cycles, SIGNAL_B is 1 cycle,
SIGNAL_C is 0 cycle and SIGNAL_D is 1 cycle.
Next, in processing 1105, an edge trigger type latch is inserted for each signal in order to realize the delay cycle determined in processing 1104. The number is the same as the number of delay cycles. Finally, by processing 1106,
The edge-triggered latches generated in the process 1105 are connected, and the derived signal is given a name. Through the above processing, the time adjustment logic generation processing 1100 generates, for example, the time adjustment logic 402 as shown in FIG. The output signal of the time adjustment logic is hereinafter referred to as a synchronization signal.

FIG. 12 shows a pattern matching logic generation process 12.
00 shows a processing flow of 00. Pattern matching logic generation processing 1
In step 2001, the following processing is performed for all function events in step 1201. First, in process 1202, for the synchronization signal that is the output of all the time adjustment logics,
The collation pattern is checked, and the branch control of the process 1203 is performed. That is, when the matching pattern is “0”, an inverter is connected to the synchronization signal. Thus, the check that the synchronization signal is "0" is
It has the same value as the inverter output signal being "1".
Finally, in processing 1205, one AND gate is added to all the synchronization signals or the output signals of the inverters. Since the output signal of the AND gate becomes "1" only when all the inputs are "1", the output of the AND gate being "1" means that the functional event whose number of occurrences needs to be measured has occurred. Means As described above, the pattern matching logic generation processing 1200 generates the pattern matching logic. As described above, prior to the execution of the logic simulation, the logic verification sufficiency evaluation system 200 first measures the occurrence of a given function event with respect to a given function event by the function coverage measurement preparation processing 1000 and generates the result. A measurement logic circuit having a function of holding the number of times is generated, and then, in a logic simulation, the verification target logic circuit and the previously generated measurement logic circuit are collectively simulated. .
Here, from the viewpoint of the simulator, it is possible to measure the occurrence of the functional event by performing the same processing as the normal gate evaluation. After completion of the logic simulation, the contents of the accumulation memory holding the number of occurrences are output, and accumulation / output is performed by a result accumulation editing process. Through the above processing, it is possible to minimize the overhead of the execution speed in the logic simulation related to the coverage measurement.

[0031]

According to the logic verification sufficiency evaluation method and system of the present invention, the logic verification sufficiency evaluation based on the function realized in the logic simulation is executed at high speed without adding any special processing to the logic simulator. It is possible. As a result, the overhead of the execution speed required for measuring the function coverage can be reduced, and a sufficiently practical system can be constructed. Therefore, the results of this function coverage measurement can be used to indicate unverified functions and to manage the progress of simulation, etc., and provide necessary and sufficient testing by selecting the test program to be executed and providing feedback such as creating a new test program. Efficient logic verification by a program can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a functional event to be measured for occurrence in the logic verification sufficiency evaluation method of the present invention.

FIG. 2 is a configuration diagram of a system that implements a logic verification sufficiency evaluation method of the present invention.

FIG. 3 is an illustration of functional event pattern data according to the present invention.

FIG. 4 is an exemplary diagram of a measurement logic circuit according to the present invention.

FIG. 5 is an exemplary diagram of connection information data according to the present invention.

FIG. 6 is an illustration of functional event name data according to the present invention.

FIG. 7 is an exemplary diagram of accumulated memory data according to the present invention.

FIG. 8 is an exemplary diagram of accumulated data according to the present invention.

FIG. 9 is an illustration of an output result according to the present invention.

FIG. 10 is a flowchart of a function coverage measurement preparation process according to the present invention.

FIG. 11 is a flowchart of a time adjustment logic generation process according to the present invention.

FIG. 12 is a flowchart of a pattern matching logic generation process according to the present invention.

FIG. 13 is an example of a hardware configuration of a logic verification sufficiency evaluation system according to the present invention.

[Explanation of symbols]

1: CPU, 2: output device, 3: keyboard, 4: main memory, 5: auxiliary storage device 5, 6: simulation-dedicated mechanism, 200: logic verification sufficiency evaluation system, 201: logic simulator, 20
2 ... Result cumulative editing process 203 ... Logic circuit data to be verified 204: Test data 205: Simulation result data 300: Function event pattern data 400
... Logic circuit data for measurement, 500 ... Connection information data, 6
00: Function event name data, 700: Cumulative memory data, 800: Cumulative data, 1000: Function coverage measurement preparation processing, 1100: Time adjustment logic generation processing, 1200
… Pattern matching logic generation processing

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-67165 (JP, A) JP-A-4-289974 (JP, A) JP-A-3-41565 (JP, A) JP-A 64-64 26243 (JP, A) Japanese Patent Laid-Open No. Hei 3-18776 (JP, A) "Transactions of the National Convention of the Information Processing Society of Japan" Vol. 43rd NO. 6 PAGE 6.263-6.264 "HW and FW coverage measurement system using HAL3" (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/50 G06F 11/25 G01R 31 / 28 JICST file (JOIS)

Claims (6)

(57) [Claims] 1. A function event pattern data representing a function of a logic circuit to be verified which is defined in advance is input, the number of occurrences of the function event during a logic simulation is measured, and the occurrence status data of the function event is output. A first step of previously creating virtual measurement logic circuit data having a function of measuring the number of occurrences of the functional event in the logic verification sufficiency evaluation method; and a logic circuit data to be verified and the virtual measurement. And a second step of simultaneously simulating the use logic circuit data and measuring the number of occurrences of the function event to output the occurrence state of the function event , and wherein the first step includes: The function event pattern data
Lexical analysis / syntax analysis by inputting
Pattern that outputs pattern data analysis data
A data analysis step, and the pattern data analysis data
To adjust the timing of the signals that make up the pattern
Performing a time adjustment logic generation process that performs
Output of the integer logic generation process and the given function event pattern data
Pattern matching logic generation processing step to match data
And time adjustment theory as a result of the pattern matching logic generation processing.
Output of logical generation processing and given function event pattern data
When the value of
Cumulative memory addition processing to increase product memory
And performing the time adjustment logic generation processing.
Pattern matching logic generation processing step and the accumulation memory
Measured based on data obtained by processing steps
Logic circuit data generation for generating logic circuit data
A logic verification sufficiency evaluation method characterized by comprising a processing step . 2. The logic verification sufficiency evaluation method according to claim 1 , wherein the first step further comprises: function event name data for associating a function event with a cumulative memory holding the number of occurrences of the function event; A logic verification sufficiency evaluation method, comprising the step of creating connection information data defining a logical connection relationship between a verification target logic circuit and the measurement logic circuit. 3. A logic verification adequacy evaluation method according to claim 1 or 2, wherein the second step, the simulation from verified logic circuit data and the test data and the measurement logic circuit data and the connection information data Third to output result data
And outputting a status of occurrence of a functional event from the output of the logic simulator and the functional event name data.
A logic verification sufficiency evaluation method characterized by comprising the steps of: 4. A logic for inputting function event pattern data representing a function of a logic circuit to be verified which is defined in advance, measuring the number of occurrences of the function event during a logic simulation, and outputting occurrence status data of the function event. A verification adequacy evaluation system, comprising: first means for creating virtual measurement logic circuit data having a function of measuring the number of occurrences of the functional event based on information on a pattern of the functional event; specific measurement logic circuit data and collectively the verification target logic circuit data to be verified and a second means for outputting the occurrence of to functional entity measures the number of occurrences of the functional entity by simulating And said first means comprises said function event pattern data
Enter lexical analysis / syntax analysis using
Third means for outputting certain pattern data analysis data
And the pattern data analysis data
Time adjustment logic to adjust the timing of the signals that make up
Means for performing the time adjustment processing, and the output of the time adjustment logic generation processing.
A putter that matches the given functional event pattern data
Pattern matching logic generation processing means, and the pattern matching logic generation
As a result of the processing, the output of the time adjustment logic generation processing and given
When the function event pattern data matches, the function event
The cumulative memory that holds the number of occurrences of
Accumulative memory addition processing means, and the time adjustment logic generation processing
Processing means, pattern matching logic generation processing means, and
Based on the data obtained by the product memory addition processing means
Logic circuit data to generate measurement logic circuit data
A logic verification sufficiency evaluation system, comprising: an evening generation processing means . 5. The logic verification sufficiency evaluation system according to claim 4 , wherein the first means further comprises: function event name data for associating a function event with a cumulative memory holding the number of occurrences of the function event; A logic verification sufficiency evaluation system including means for creating connection information data for associating a signal in a logic circuit to be verified with input data of the measurement logic circuit data. 6. The logic verification sufficiency evaluation system according to claim 4 , wherein the second means simulates the logic circuit data to be verified, test data, the measurement logic circuit data, and the connection information data. A logic verification sufficiency evaluation system comprising: third means for outputting result data; and fourth means for outputting a status of occurrence of a functional event from an output of the logic simulator and the functional event name data. .