JP3054888B2 - Auto-zero circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an auto-zero circuit for eliminating the influence of an offset voltage of an analog signal input to an AD converter. When an analog signal such as an audio signal is converted into a digital signal, a configuration is generally adopted in which the analog signal is input to an AD converter via an active filter for removing high-frequency noise components and low-frequency noise components. Such an active filter includes an operational amplifier and the like, and its offset voltage becomes a problem. Therefore, an auto-zero circuit for compensating the offset voltage is provided. It is desired to speed up the pull-in of the auto-zero circuit.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a main part of a conventional example.
31 is an AD converter (A / D), 32 is a low-pass filter (LPF), 33 is a high-pass filter (HPF), 34
Is an operational amplifier, 35 is an auto-zero circuit, 36 is a counter section, 37 is an operational amplifier, 38 is an attenuator (AT
T), SW1 and SW2 are switches composed of transistors and the like, R1 and R2 are resistors, and C1 and C2 are capacitors.

The analog signal Ain has a low-pass filter 32 for removing low-frequency noise components such as a frequency component of an AC power supply, and a high-pass filter 33 for removing high-frequency noise components. AD
For example, in the case of the audio analog signal Ain, the converter 31 is sampled at 8 kHz, and the sample and hold value is converted into an 8-bit digital signal Dout according to a companding rule such as A-law or μ-law. You. The most significant bit MSB is added to the counter 36 of the auto-zero circuit 35 as a sign bit SB.

The counter section 36 of the auto-zero circuit 35
Performs up-counting or down-counting in accordance with the sign bit SB, and when the count content reaches a set value,
The switching of the switches SW1 and SW2 is controlled. For example,
When the switches SW1 and SW2 are switched to the solid line positions,
When the voltage V _DD (for example, +5 V) is applied to the capacitor C2 via the resistor R2, and then the switch SW2 is switched to the dotted line position, the charge of the capacitor C2 is made up of the operational amplifier 37 and the capacitor C1. The integrated output is transferred to the integrating circuit, and the integrated output is supplied to the operational amplifier 34 at the final stage of the high-pass filter 33 via the attenuator 38 to obtain the compensation voltage C.
It is added as PV and offset voltage is compensated.

The counter section 36 counts up, for example, when the sign bit SB indicates a positive polarity, and counts down when the sign bit SB indicates a negative polarity. It indicates the difference in numbers. Generally, since the analog signal Ain has an amplitude centered on the signal ground potential, the sign bit S of the positive polarity and the negative polarity within a predetermined time period
The number of appearances of B is ideally the same. However, the low-pass filter 32 and the high-pass filter 33 are switched
Since an active filter configuration including the operational amplifier 34 is used like a capacitor filter, an offset voltage is generated, and this offset voltage is generated by the analog signal A.
When superimposed on “in”, the digital signal cannot be converted into a correct digital signal Dout, and the quality of reproduced voice is degraded.

When the offset voltage is superimposed on the analog signal Ain, a difference occurs in the number of appearances of the sign bit SB between the positive polarity and the negative polarity. The above-mentioned switches SW1 and SW2
In the case of controlling the switching, the preset value of the counter unit 36 is set to 16, whereby the borrow signal is output when the count becomes 0, and the carry signal is output when the count becomes 32. When counting up with the sign bit SB of the positive polarity and counting down with the sign bit SB of the negative polarity, a carry signal is output when the number of the sign bits SB of the positive polarity is large. Sign bit S
If B is large, a borrow signal will be output.
The carry signal or the borrow signal is applied to the preset terminal PS, and 16 is preset in the counter section 36.

When the carry signal is output, the switch S
W1 is switched to the solid line position, and switch SW2 is switched to the dotted line position after being switched to the solid line position. When the switch SW1 is switched to the solid line position, the voltage V _DD is applied to the capacitor C2 by being divided by the resistors R2 and R1, and when the switch SW2 is switched to the dotted line position,
The charge of the capacitor C2 is transferred to the capacitor C1. Therefore, the compensation voltage CPV increases.
When the borrow signal is output, the switch SW1 is switched to the position indicated by the dotted line, the switch SW2 is switched to the position indicated by the solid line, and then the switch SW2 is switched to the position indicated by the dotted line. Therefore, the switches SW2 and SW1 and the resistors R2 and R1 are connected. The capacitor C2 is charged with a negative charge and the switch SW
2 is switched to the position indicated by the dotted line, the charge of the capacitor C1 is transferred to the capacitor C2.
Drops. Therefore, the magnitude of the compensation voltage CPV is controlled so that the difference in the number of appearances of the sign bits SB of the positive and negative polarities becomes zero, and the offset voltage is compensated.

[0008]

In the above-described conventional example, the switch SW1 is switched every time the difference in the number of appearances of the sign bit SB of the positive / negative polarity indicated by the count content of the counter unit 36 reaches the set value of 16. , SW2 switching is controlled,
The compensation voltage CPV for compensating the offset voltage is increased or decreased. At the time of power-on at the time of power-down release or the like, the offset voltage may be large.
In this case, the analog signal Ain is largely shifted to the positive side or the negative side by the offset voltage. For example, when the analog signal Ain is shifted to the negative side, the number of appearances of the positive sign bits SB increases continuously. Even in this case, the switching of the switches SW1 and SW2 is controlled every time the difference in the number of appearances becomes 16, and the compensation voltage CPV changes by a step amount determined by the capacitors C1 and C2, the attenuator 38, and the like.

Therefore, it takes a considerable time to obtain a large compensation voltage CPV for compensating for a large offset voltage. That is, the auto-zero circuit 35
There is a drawback that the time required for pulling in is long. In order to eliminate such a defect, it is conceivable to increase the step amount of the compensation voltage CPV. However, after pulling in the auto-zero circuit 35, a step amount sufficient to compensate for a slightly fluctuating offset voltage is sufficient. When the step amount of the compensation voltage CPV is increased, it causes an unstable operation of the circuit. An object of the present invention is to reduce the pull-in time of an auto-zero circuit.

[0010]

The auto-zero circuit of the present invention will be described with reference to FIG. 1. Referring to FIG. 1, an analog signal is input to an AD converter 1 through an active filter 2, and the converted digital signal is Counts up and down according to the sign bit, and the initial value when the count reaches the set value
A counter portion 3 to return to, and controls the switch when the count contents of the counter 3 reaches the set value, the Sui
The integration output by the switching control of the pitch, as a compensation voltage for compensating the offset voltage of the analog signal inputted to the AD converter 1, operations which constitute the active filter 2
An automatic circuit having a compensation voltage forming section 4 for inputting to an amplifier ;
In the zero circuit, each time a predetermined number of sine bits of the same polarity of the digital signal continue for a predetermined number, the set value is sequentially reduced, and
The set value is sequentially increased or
A set value control unit 5 for restoring the original value is provided.

An input switching unit 6 for switching to the signal ground potential and inputting the signal to the AD converter 1 instead of the output signal of the active filter 2 from the time when the power down is released until the operation of the active filter 2 is stabilized. Is provided.

[0012]

The counter unit 3 which counts up or down according to the sign bit of the digital signal converted by the AD converter 1 indicates the difference in the number of sign bits of positive and negative polarity. Each time the difference reaches the set value, the compensation voltage changes by switching control of the switch of the compensation voltage forming unit 4. When the offset voltage is large, since the sign bits having the same polarity continue, the set value is sequentially reduced every predetermined number of consecutive times. Accordingly, the difference in the number of appearances of the sign bits of the positive and negative polarity in the counter unit 3 quickly reaches the set value, and the cycle of controlling the switches of the compensation voltage forming unit 4 is sequentially shortened. That is, since the compensation voltage can be rapidly increased in accordance with the large offset voltage, the speed of pulling in the auto-zero circuit can be increased. After the pull-in, a predetermined number of sine bits of the same polarity will not be continued, so that the set value is sequentially increased or the control is returned to the initial value, and the normal auto-zero circuit is controlled. .

The input switching unit 6 always has the active filter 2
Is switched so as to be input to the AD converter 1 at the time of power-down release. However, since the operation of the active filter 2 and the auto-zero circuit 3 is not stabilized at the time of power-down release, the AD converter 1 Switch the signal ground potential and input. That is, since the amplitude of the analog signal has an amplitude centered on the signal ground potential, the signal ground potential must be input to the AD converter 1 until the operation of the active filter 2 and the like is stabilized. Accordingly, it is possible to prevent a digital signal including noise from being output.

[0014]

FIG. 2 is a block diagram of a main part of an embodiment of the present invention, wherein 11 is an AD converter (A / D), 12 is a low-pass filter (LPF), and 13 is a high-pass filter (including an operational amplifier 14). HPF), 15 is an auto-zero circuit, 16
Is a counter unit, 17 is an operational amplifier, 18 is an attenuator (ATT), 19 is a set value control unit, 20 is an input switching unit,
21 is a detecting unit for detecting the number of consecutive sine bits of the same polarity, 22 is a set value switching unit, SW1, SW2, and SW3 are switches composed of transistors, C1 and C2 are capacitors, and R1 and R2.
2 is a resistor.

The low-pass filter 12 and the high-pass filter 13 have a configuration including an operational amplifier 14 and the like as in the conventional example, and the AD converter 11 also samples and holds an analog signal by an 8 kHz sample clock signal as in the conventional example. Then, the signal is converted into an 8-bit digital signal according to the companding rule of A-law or μ-law, and the most significant bit MSB thereof is set as a sign bit SB to the counter 16 of the auto-zero circuit 15 and the set value. It is added to the control unit 19.

The input switching unit 20 controls the switch SW3. The input switch 20 normally switches the switch SW3 to the position indicated by the solid line, and a predetermined period until the operation of the high-pass filter 13 and the like is stabilized by the power-down release signal PD. During the period, the switch SW3 is switched to the position indicated by the dotted line, and the signal ground potential is input to the AD converter 11. In this case, assuming that a single power supply is operated at V _DD = + 5 V, A
The analog signal input to the D converter 11 is set to + 2.5V
This is a waveform having an amplitude centered at (signal ground potential). Therefore, when the signal ground potential is input to the AD converter 11, the input is in a state of zero.
Therefore, a noise component or the like due to unstable operation of the low-pass filter 12 and the high-pass filter 13 when the power down is released is not input to the AD converter 11. The predetermined period until the operation of the high-pass filter 13 and the like is stabilized can be set by a timer or the like triggered by the power-down release signal PD.

The counter 16 has a set value control terminal CT.
The set value is switched by a control signal applied to the preset terminal PS, preset by a carry signal or a borrow signal applied to a preset terminal PS, and counts up or down in accordance with the polarity of the sign bit SB. And a carry signal or a borrow signal is output when the count content reaches a set value, and the switching of the switches SW1 and SW2 is controlled.
That is, a configuration in which the set value is switched by the control signal applied to the set value control terminal CT is added to the conventional counter unit 36, and the counter unit 36 can be easily realized by adding a slight logical configuration. be able to.

The detecting section 21 of the set value control section 19 detects, for example, that the sign bits SB of the same polarity have continued 16 times, and sets the sign bit SB of the positive polarity to "1".
Assuming that the sign bit SB of the negative polarity is “0”, 2
One of the counters is a counter that counts up “1” and is cleared by “0”, and the other is “0”.
Are counted up to be cleared by "1", and the carry signal when the count content reaches 16 can be used as a predetermined number of consecutive detection signals of the sign bit SB having the same polarity. Also, when the output of each stage is the same "1" or "0" using a 16-stage shift register, it is determined that the sign bit SB of the same polarity is continuous 16 times, and a detection signal is output. By inverting the output of the stage and inputting it to the first stage, it can be configured to detect whether it is repeated 16 times continuously.

The set value switching unit 22 switches the set value in the counter unit 16 according to the detection signal from the detection unit 21. If the initial set value of the counter unit 16 is 16, a sign bit of positive and negative polarity The difference in the number of SB occurrences is 16
, The switching control of the switches SW1 and SW2 is performed. When the offset voltage is large, the sign bits SB having the same polarity appear continuously. When the detecting unit 21 detects that the sign bits SB appear 16 times consecutively, the detecting unit 21 switches the detection signal to the set value. The setting value switching unit 22 outputs the control signal to the setting value control terminal C
In addition to T, the set value is switched to 8. As a result, the counter unit 16 controls the switching of the switches SW1 and SW2 each time the difference in the number of appearances of the sign bits SB of the positive and negative polarities reaches 8. The switching of the set value is performed, for example, by switching the preset value of the counter unit 16 from 16 to 8, and by switching the logic configuration to output a borrow signal when the count content is 0 and a carry signal when the count content is 16. Can be realized.

Further, when the sign signal SB of the same polarity continues and the detection signal from the detecting section 21 is applied to the set value switching section 22, the set value switching section 22 changes the set value of the counter section 16 from 8 to 4. Switch to Also in this case, the counter unit 1
This can be realized by switching the preset value of 6 from 8 to 4 and switching the logic configuration to output a borrow signal when the count content is 0 and a carry signal when the count content is 8.

Further, when the sign signal SB of the same polarity continues and the detection signal from the detection unit 21 is applied to the set value switching unit 22, the set value switching unit 22 changes the set value of the counter unit 16 from 4 to 2. Switch to Further, when the sine bits SB having the same polarity continue and the detection signal from the detection unit 21 is applied to the set value switching unit 22, the set value switching unit 22 switches the set value of the counter unit 16 from 2 to 1. When the set value is 1, the switching control of the switches SW1 and SW2 is performed every time the sign bit SB having the same polarity is input to the counter unit 16, and the compensation voltage CPV rapidly increases or decreases. become.

After or immediately before the pull-in state in which the compensation voltage CPV having a magnitude for compensating the offset voltage can be output, the sign bits SB of the same polarity do not continue. Therefore, the detecting unit 21 detects, for example, that a state in which the sign bits SB of the same polarity have continued 16 times or more but not even once has occurred, and adds the detection signal to the set value switching unit 22. , The set value switching unit 22 includes a set value control terminal CT of the counter unit 16.
, A control signal for returning the set value to the initial state is added, and the set value of the counter section 16 is returned to 16. Further, it is also possible to control to return the set value to the initial state when the sign bit SB having the same polarity is not added continuously plural times, for example, four times, from the state of continuous 16 times or more. Regarding such a return of the set value, instead of returning to the initial state at once, contrary to the case where the set value is sequentially reduced, 1 → 2 → 4 → 8 → 16
It is also possible to control so as to sequentially increase the set value and return to the initial state. Of course, it is also possible to use a value other than 16 as the initial set value, and the set value switching step may be a different step from the above-described embodiment. Also, the predetermined number of consecutive times detected by the detecting section 21 can be controlled to be switched together with the set value when the sign bit SB of the same polarity appears continuously.

[0023]

As described above, according to the present invention, the set value of the counter section 3 is sequentially reduced by the set value control section 5 every time a predetermined number of sine bits of the same polarity of the digital signal continue. , By reducing the set value,
Even if the difference between the number of appearances of the sign bit of the positive and negative signs of the count content of the counter unit 3 is small, the count value reaches the set value,
Since the switching control of the switch of the compensation voltage forming unit 4 is performed, the compensation voltage for compensating the offset voltage can be rapidly increased or decreased. That is, there is an advantage that the speed of pulling in the auto-zero circuit can be increased.

When the power-down is released, the signal ground potential is input to the AD converter 1 until the operation of the active filter 2 such as a low-pass filter or a high-pass filter is stabilized. Since the noise component is not output as a digital signal from the AD converter 1, there is an advantage that the operation of each unit can be stabilized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a main block diagram of an embodiment of the present invention.

FIG. 3 is a main part block diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 AD converter 2 Active filter 3 Counter part 4 Compensation voltage formation part 5 Set value control part 6 Input switching part

Claims (2)

(57) [Claims] An AD converter (1) includes an active filter (2).
Analog signal is input through and up / down counting corresponding to the sign bit of the converted digital signal
And, mosquitoes <br/> counter unit back to the initial value when the count content reaches a set value (3), and controls the switch when the counter unit counts the content of (3) reaches the set value the Switch
Switch output from the A / D converter (1)
As compensation voltage for compensating the offset voltage of the analog signal inputted to and configure the active filter (2)
An auto-zero circuit having a compensation voltage forming unit (4) for inputting the signal to an operational amplifier , wherein the set value is sequentially reduced each time a predetermined number of sine bits of the same polarity of the digital signal continue , And a certain number of reams
If the setting is not continued, increase the set value sequentially or immediately return to the original value.
Auto-zero circuit, characterized in that set value control unit (5) provided. 2. An output signal of the active filter (2) is switched to a signal ground potential during a period from the release of power down to the stabilization of the operation of the active filter (2). Input switching section (6)
The auto zero circuit according to claim 1, further comprising: