JP3057260B2 - Chassis structure of cathode ray tube display - Google Patents
Chassis structure of cathode ray tube displayInfo
- Publication number
- JP3057260B2 JP3057260B2 JP2203064A JP20306490A JP3057260B2 JP 3057260 B2 JP3057260 B2 JP 3057260B2 JP 2203064 A JP2203064 A JP 2203064A JP 20306490 A JP20306490 A JP 20306490A JP 3057260 B2 JP3057260 B2 JP 3057260B2
- Authority
- JP
- Japan
- Prior art keywords
- chassis structure
- circuit
- substrate
- ray tube
- cathode ray
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Description
【発明の詳細な説明】 [産業上の利用分野] この発明は、陰極線管表示装置の内部の電磁妨害を受
ける部品や回路をシールドするシャーシ構造に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chassis structure for shielding components and circuits in a cathode ray tube display device that are subject to electromagnetic interference.
[発明の概要] この発明は、基板の一面に回路等を設け、電磁妨害の
発生源に対向する他面に導電パターンを設けることによ
り、シールドケースやシールド板等の部品を使用せず、
電磁シールドのための部品点数・組み立て工数の低減及
びシャーシ構造のコンパクト化を図るものである。[Summary of the Invention] The present invention provides a circuit or the like on one surface of a substrate and a conductive pattern on the other surface facing a source of electromagnetic interference, thereby eliminating the use of components such as a shield case and a shield plate.
It is intended to reduce the number of parts and the number of assembling steps for the electromagnetic shield and to make the chassis structure compact.
[従来の技術] 陰極線管表示装置などの電子機器にはその機器内の回
路又は部品の一方が妨害発生源となり、他方が妨害の受
け手となる場合があり、機器内の回路又は部品間の電磁
妨害を防ぐ必要がある場合がある。このようなシャーシ
構造として従来は、電磁妨害を受けては困る回路や部品
を取付けた基板の電磁妨害の発生源側にシールド板を取
付けたり、基板をシールドケースで覆う構造が用いられ
ていた。2. Description of the Related Art In an electronic device such as a cathode ray tube display device, one of circuits or components in the device may be a source of interference and the other may be a recipient of the interference. It may be necessary to prevent interference. Conventionally, as such a chassis structure, a structure has been used in which a shield plate is mounted on a side of a substrate on which a circuit or a component which is not likely to be subjected to electromagnetic interference is attached, on the side of a source of electromagnetic interference, or the substrate is covered with a shield case.
[発明が解決しようとする課題] しかし、シールド板やシールドケースを用いると部品
点数の増加のみならず、前記基板に取り付けるための取
り付け部を必要とし、構造の複雑化、組み立て工数の増
加、及びスペースをとってしまう問題点があった。[Problems to be Solved by the Invention] However, the use of a shield plate or a shield case not only increases the number of components, but also requires a mounting portion for mounting on the substrate, complicating the structure, increasing the number of assembly steps, and There was a problem of taking up space.
そこで、この発明は、シャーシ構造の簡易化、部品点
数・組み立て工数の低減及びコンパクト化を図ることを
その課題とする。Therefore, an object of the present invention is to achieve simplification of a chassis structure, reduction of the number of parts and assembly steps, and downsizing.
[課題を解決するための手段] この発明は、一面に信号系の回路または部品が設けら
れた基板の反対面を電磁妨害の発生源に対向して配置
し、前記基板の他面には前記回路または部品が電磁妨害
の影響を受ける範囲に導電パターンを設けたことを、そ
の構成とする。[Means for Solving the Problems] According to the present invention, an opposite surface of a substrate provided with a signal system circuit or component on one surface is arranged to face a source of electromagnetic interference, and the other surface of the substrate is The configuration is such that a conductive pattern is provided in a range where a circuit or a component is affected by electromagnetic interference.
[作用] 電磁妨害の発生源からでた電磁波は、前記発生源に対
向する基板の他面に設けた導電パターンにより反射さ
れ、前記両面基板の一面に設けた部品や回路は電磁妨害
を受けない。[Effect] Electromagnetic waves emitted from a source of electromagnetic interference are reflected by a conductive pattern provided on the other surface of the substrate facing the source, and components and circuits provided on one surface of the double-sided substrate are not subjected to electromagnetic interference. .
[実施例] 以下、この発明の実施例を図面に基づいて説明する。Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
第1図乃至第3図には一実施例が示され、この実施例
では本発明をクリアビジョンのテレビ受信機にシャーシ
構造に適用した場合が示されている。クリアビジョンの
テレビ受信機はノーマルスキャン用の映像信号を倍速ス
キャン用の映像信号に変換して映像を再生する。FIGS. 1 to 3 show an embodiment, in which the present invention is applied to a clear vision television receiver in a chassis structure. A clear vision television receiver converts a video signal for normal scanning into a video signal for double-speed scanning and reproduces the video.
第2図にはテレビ受信機のシャーシ構造の概略構成図
が示されている。第2図において、1はブラウン管、2
は偏向回路、3はフライバックトランスである。偏向回
路2,フライバックトランス3は倍速スキャン系の回路と
なり、偏向回路2は第3図に示す如く倍速スキャン用映
像信号をスキャンするよう偏向電圧を印加し、フライバ
ックトランス3は第3図に示す如くフライバックパルス
を発生する。ノーマルスキャン用映像信号を処理するY
信号処理回路,クロマ信号処理回路等の電磁妨害を受け
ては困る回路又は部品4は基板5にマウントされ、この
基板5が第1図にも示す如く偏向回路2やフライバック
トランス3に対して略直交して配置されている。即ち、
電磁妨害を受けては困る回路又は部品4の反対面5aが偏
向回路2やフライバックトランス3に対向して配置され
ている。そして、基板5の反対面5aには前記回路又は部
品4に偏向回路2やフライバックトランス3より電磁波
が直接投射される範囲に導電パターン6が形成されてい
る。この実施例では基板5の反対面5aの一部範囲に導電
パターン6を形成したが全範囲に形成してもよい。FIG. 2 shows a schematic configuration diagram of a chassis structure of the television receiver. In FIG. 2, 1 is a cathode ray tube, 2
Is a deflection circuit, and 3 is a flyback transformer. The deflecting circuit 2 and the flyback transformer 3 are circuits of a double-speed scanning system. The deflecting circuit 2 applies a deflecting voltage to scan the double-speed scanning video signal as shown in FIG. A flyback pulse is generated as shown. Y for processing video signal for normal scan
Circuits or components 4 which are not susceptible to electromagnetic interference, such as a signal processing circuit and a chroma signal processing circuit, are mounted on a board 5, and this board 5 is connected to the deflection circuit 2 and the flyback transformer 3 as shown in FIG. They are arranged substantially orthogonally. That is,
The opposite surface 5a of the circuit or component 4 that is not susceptible to electromagnetic interference is arranged to face the deflection circuit 2 and the flyback transformer 3. A conductive pattern 6 is formed on an opposite surface 5a of the substrate 5 in a range where the electromagnetic wave is directly projected from the deflection circuit 2 or the flyback transformer 3 onto the circuit or component 4. In this embodiment, the conductive pattern 6 is formed in a partial area of the opposite surface 5a of the substrate 5, but may be formed in the entire area.
上記構成において、偏向回路2やフライバックトラン
ス3から放射される電磁波はこれらに対向する基板5の
導電パターン6により反射されるため基板5の一面にマ
ウントされる信号系の回路または部品4は電磁妨害によ
る影響を受けず、ノーマルスキャン用映像信号に第3図
にて破線で示すようなノイズが乗らない。In the above configuration, since the electromagnetic waves radiated from the deflection circuit 2 and the flyback transformer 3 are reflected by the conductive pattern 6 of the substrate 5 facing them, the circuit or component 4 of the signal system mounted on one surface of the substrate 5 has an electromagnetic wave. It is not affected by the interference, and the noise shown by the broken line in FIG. 3 does not appear on the video signal for normal scanning.
そして、前記シャーシ構造は、従来のように、シール
ド板やシールドケースを使用しないので前記シールド板
等を基板の一面に取り付けるための取り付け構造を必要
とせず、構造が簡易で部品点数・組み立て工数の低減及
び省スペース化に供する。Since the chassis structure does not use a shield plate or a shield case as in the related art, there is no need for a mounting structure for mounting the shield plate or the like on one surface of the substrate, the structure is simple, and the number of parts and assembly man-hours are reduced. Provide for reduction and space saving.
[発明の効果] 以上の説明から明らかなようにこの発明は、基板に信
号系の部品や回路を設け、電磁妨害の発生源である偏向
回路とフライバックトランスに対向する他面に導電パタ
ーンを設けて電磁波の妨害を阻止する構成としたので、
シャーシ構造の簡易化、部品点数・組み立て工数の低
減、および装置のコンパクト化を図るという効果があ
る。[Effects of the Invention] As is apparent from the above description, the present invention provides a signal-related component or circuit on a substrate and forms a conductive pattern on the other surface opposite to a deflection circuit which is a source of electromagnetic interference and a flyback transformer. Because it was configured to block electromagnetic interference,
This has the effect of simplifying the chassis structure, reducing the number of parts and assembling steps, and reducing the size of the device.
第1図乃至第3図は本発明の一実施例を示し、第1図は
基板の配置を示す斜視図、第2図はテレビ受信機の概略
構成図、第3図は波形図である。 1……回路又は信号系の部品、5……基板、5a……反対
面、6……導電パターン。1 to 3 show an embodiment of the present invention. FIG. 1 is a perspective view showing the arrangement of substrates, FIG. 2 is a schematic configuration diagram of a television receiver, and FIG. 3 is a waveform diagram. 1 ... circuit or signal components, 5 ... board, 5a ... opposite surface, 6 ... conductive pattern.
Claims (1)
て、一面に信号系の回路または部品が設けられた1以上
の基板の他面を電磁妨害の発生源である偏向回路とフラ
イバックトランスの少なくとも片方または両方に対向し
て配置し、前記基板の他面には前記信号系の回路または
部品が前記電磁妨害の影響を受ける範囲に導電パターン
を設けたことを特徴とする陰極線管表示装置のシャーシ
構造。In a chassis structure of a cathode ray tube display device, at least one of a deflection circuit and a flyback transformer, which is a source of electromagnetic interference, is provided on one surface of one or more substrates provided with signal circuits or components on one surface. Or a conductive pattern provided on the other surface of the substrate in a range where the signal circuit or component is affected by the electromagnetic interference. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2203064A JP3057260B2 (en) | 1990-07-31 | 1990-07-31 | Chassis structure of cathode ray tube display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2203064A JP3057260B2 (en) | 1990-07-31 | 1990-07-31 | Chassis structure of cathode ray tube display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0487397A JPH0487397A (en) | 1992-03-19 |
| JP3057260B2 true JP3057260B2 (en) | 2000-06-26 |
Family
ID=16467742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2203064A Expired - Lifetime JP3057260B2 (en) | 1990-07-31 | 1990-07-31 | Chassis structure of cathode ray tube display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3057260B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4935321B2 (en) * | 2006-11-24 | 2012-05-23 | 大日本印刷株式会社 | Mold for preform compression molding |
-
1990
- 1990-07-31 JP JP2203064A patent/JP3057260B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0487397A (en) | 1992-03-19 |
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